1Arm Fixed Virtual Platforms (FVP) 2================================= 3 4Fixed Virtual Platform (FVP) Support 5------------------------------------ 6 7This section lists the supported Arm |FVP| platforms. Please refer to the FVP 8documentation for a detailed description of the model parameter options. 9 10The latest version of the AArch64 build of TF-A has been tested on the following 11Arm FVPs without shifted affinities, and that do not support threaded CPU cores 12(64-bit host machine only). 13 14.. note:: 15 The FVP models used are Version 11.14 Build 21, unless otherwise stated. 16 17- ``FVP_Base_AEMvA`` 18- ``FVP_Base_AEMv8A-AEMv8A`` 19- ``FVP_Base_AEMv8A-AEMv8A-AEMv8A-AEMv8A-CCN502`` 20- ``FVP_Base_RevC-2xAEMvA`` 21- ``FVP_Base_Cortex-A32x4`` (Version 11.12 build 38) 22- ``FVP_Base_Cortex-A35x4`` 23- ``FVP_Base_Cortex-A53x4`` 24- ``FVP_Base_Cortex-A55x4+Cortex-A75x4`` 25- ``FVP_Base_Cortex-A55x4`` 26- ``FVP_Base_Cortex-A57x1-A53x1`` 27- ``FVP_Base_Cortex-A57x2-A53x4`` 28- ``FVP_Base_Cortex-A57x4-A53x4`` 29- ``FVP_Base_Cortex-A57x4`` 30- ``FVP_Base_Cortex-A65x4`` 31- ``FVP_Base_Cortex-A65AEx8`` 32- ``FVP_Base_Cortex-A72x4-A53x4`` 33- ``FVP_Base_Cortex-A72x4`` 34- ``FVP_Base_Cortex-A73x4-A53x4`` 35- ``FVP_Base_Cortex-A73x4`` 36- ``FVP_Base_Cortex-A75x4`` 37- ``FVP_Base_Cortex-A76x4`` 38- ``FVP_Base_Cortex-A76AEx4`` 39- ``FVP_Base_Cortex-A76AEx8`` 40- ``FVP_Base_Cortex-A77x4`` 41- ``FVP_Base_Cortex-A78x4`` 42- ``FVP_Base_Matterhornx4`` 43- ``FVP_Morello`` (Version 0.10 build 542) 44- ``FVP_Base_Neoverse-E1x1`` 45- ``FVP_Base_Neoverse-E1x2`` 46- ``FVP_Base_Neoverse-E1x4`` 47- ``FVP_Base_Neoverse-N1x4`` 48- ``FVP_Base_Neoverse-N2x4`` (Version 11.12 build 38) 49- ``FVP_Base_Neoverse-V1x4`` 50- ``FVP_CSS_SGI-575`` (Version 11.10 build 36) 51- ``FVP_CSS_SGM-775`` 52- ``FVP_RD_E1_edge`` (Version 11.9 build 41) 53- ``FVP_RD_N1_edge`` (Version 11.10 build 36) 54- ``FVP_RD_N1_edge_dual`` (Version 11.10 build 36) 55- ``FVP_RD_Daniel`` (Version 11.13 build 10) 56- ``FVP_RD_N2`` (Version 11.13 build 10) 57- ``FVP_TC0`` (Version 0.0 build 6509) 58- ``FVP_Base_AEMv8A-GIC600AE`` (Version 0.0 build 6415) 59- ``Foundation_Platform`` 60 61The latest version of the AArch32 build of TF-A has been tested on the 62following Arm FVPs without shifted affinities, and that do not support threaded 63CPU cores (64-bit host machine only). 64 65- ``FVP_Base_AEMvA`` 66- ``FVP_Base_AEMv8A-AEMv8A`` 67- ``FVP_Base_Cortex-A32x4`` 68 69.. note:: 70 The ``FVP_Base_RevC-2xAEMv8A`` FVP only supports shifted affinities, which 71 is not compatible with legacy GIC configurations. Therefore this FVP does not 72 support these legacy GIC configurations. 73 74The *Foundation* and *Base* FVPs can be downloaded free of charge. See the `Arm 75FVP website`_. The Cortex-A models listed above are also available to download 76from `Arm's website`_. 77 78.. note:: 79 The build numbers quoted above are those reported by launching the FVP 80 with the ``--version`` parameter. 81 82.. note:: 83 Linaro provides a ramdisk image in prebuilt FVP configurations and full 84 file systems that can be downloaded separately. To run an FVP with a virtio 85 file system image an additional FVP configuration option 86 ``-C bp.virtioblockdevice.image_path="<path-to>/<file-system-image>`` can be 87 used. 88 89.. note:: 90 The software will not work on Version 1.0 of the Foundation FVP. 91 The commands below would report an ``unhandled argument`` error in this case. 92 93.. note:: 94 FVPs can be launched with ``--cadi-server`` option such that a 95 CADI-compliant debugger (for example, Arm DS-5) can connect to and control 96 its execution. 97 98.. warning:: 99 Since FVP model Version 11.0 Build 11.0.34 and Version 8.5 Build 0.8.5202 100 the internal synchronisation timings changed compared to older versions of 101 the models. The models can be launched with ``-Q 100`` option if they are 102 required to match the run time characteristics of the older versions. 103 104All the above platforms have been tested with `Linaro Release 19.06`_. 105 106.. _build_options_arm_fvp_platform: 107 108Arm FVP Platform Specific Build Options 109--------------------------------------- 110 111- ``FVP_CLUSTER_COUNT`` : Configures the cluster count to be used to 112 build the topology tree within TF-A. By default TF-A is configured for dual 113 cluster topology and this option can be used to override the default value. 114 115- ``FVP_INTERCONNECT_DRIVER``: Selects the interconnect driver to be built. The 116 default interconnect driver depends on the value of ``FVP_CLUSTER_COUNT`` as 117 explained in the options below: 118 119 - ``FVP_CCI`` : The CCI driver is selected. This is the default 120 if 0 < ``FVP_CLUSTER_COUNT`` <= 2. 121 - ``FVP_CCN`` : The CCN driver is selected. This is the default 122 if ``FVP_CLUSTER_COUNT`` > 2. 123 124- ``FVP_MAX_CPUS_PER_CLUSTER``: Sets the maximum number of CPUs implemented in 125 a single cluster. This option defaults to 4. 126 127- ``FVP_MAX_PE_PER_CPU``: Sets the maximum number of PEs implemented on any CPU 128 in the system. This option defaults to 1. Note that the build option 129 ``ARM_PLAT_MT`` doesn't have any effect on FVP platforms. 130 131- ``FVP_USE_GIC_DRIVER`` : Selects the GIC driver to be built. Options: 132 133 - ``FVP_GICV2`` : The GICv2 only driver is selected 134 - ``FVP_GICV3`` : The GICv3 only driver is selected (default option) 135 136- ``FVP_HW_CONFIG_DTS`` : Specify the path to the DTS file to be compiled 137 to DTB and packaged in FIP as the HW_CONFIG. See :ref:`Firmware Design` for 138 details on HW_CONFIG. By default, this is initialized to a sensible DTS 139 file in ``fdts/`` folder depending on other build options. But some cases, 140 like shifted affinity format for MPIDR, cannot be detected at build time 141 and this option is needed to specify the appropriate DTS file. 142 143- ``FVP_HW_CONFIG`` : Specify the path to the HW_CONFIG blob to be packaged in 144 FIP. See :ref:`Firmware Design` for details on HW_CONFIG. This option is 145 similar to the ``FVP_HW_CONFIG_DTS`` option, but it directly specifies the 146 HW_CONFIG blob instead of the DTS file. This option is useful to override 147 the default HW_CONFIG selected by the build system. 148 149- ``FVP_GICR_REGION_PROTECTION``: Mark the redistributor pages of 150 inactive/fused CPU cores as read-only. The default value of this option 151 is ``0``, which means the redistributor pages of all CPU cores are marked 152 as read and write. 153 154Booting Firmware Update images 155------------------------------ 156 157When Firmware Update (FWU) is enabled there are at least 2 new images 158that have to be loaded, the Non-Secure FWU ROM (NS-BL1U), and the 159FWU FIP. 160 161The additional fip images must be loaded with: 162 163:: 164 165 --data cluster0.cpu0="<path_to>/ns_bl1u.bin"@0x0beb8000 [ns_bl1u_base_address] 166 --data cluster0.cpu0="<path_to>/fwu_fip.bin"@0x08400000 [ns_bl2u_base_address] 167 168The address ns_bl1u_base_address is the value of NS_BL1U_BASE. 169In the same way, the address ns_bl2u_base_address is the value of 170NS_BL2U_BASE. 171 172Booting an EL3 payload 173---------------------- 174 175The EL3 payloads boot flow requires the CPU's mailbox to be cleared at reset for 176the secondary CPUs holding pen to work properly. Unfortunately, its reset value 177is undefined on the FVP platform and the FVP platform code doesn't clear it. 178Therefore, one must modify the way the model is normally invoked in order to 179clear the mailbox at start-up. 180 181One way to do that is to create an 8-byte file containing all zero bytes using 182the following command: 183 184.. code:: shell 185 186 dd if=/dev/zero of=mailbox.dat bs=1 count=8 187 188and pre-load it into the FVP memory at the mailbox address (i.e. ``0x04000000``) 189using the following model parameters: 190 191:: 192 193 --data cluster0.cpu0=mailbox.dat@0x04000000 [Base FVPs] 194 --data=mailbox.dat@0x04000000 [Foundation FVP] 195 196To provide the model with the EL3 payload image, the following methods may be 197used: 198 199#. If the EL3 payload is able to execute in place, it may be programmed into 200 flash memory. On Base Cortex and AEM FVPs, the following model parameter 201 loads it at the base address of the NOR FLASH1 (the NOR FLASH0 is already 202 used for the FIP): 203 204 :: 205 206 -C bp.flashloader1.fname="<path-to>/<el3-payload>" 207 208 On Foundation FVP, there is no flash loader component and the EL3 payload 209 may be programmed anywhere in flash using method 3 below. 210 211#. When using the ``SPIN_ON_BL1_EXIT=1`` loading method, the following DS-5 212 command may be used to load the EL3 payload ELF image over JTAG: 213 214 :: 215 216 load <path-to>/el3-payload.elf 217 218#. The EL3 payload may be pre-loaded in volatile memory using the following 219 model parameters: 220 221 :: 222 223 --data cluster0.cpu0="<path-to>/el3-payload>"@address [Base FVPs] 224 --data="<path-to>/<el3-payload>"@address [Foundation FVP] 225 226 The address provided to the FVP must match the ``EL3_PAYLOAD_BASE`` address 227 used when building TF-A. 228 229Booting a preloaded kernel image (Base FVP) 230------------------------------------------- 231 232The following example uses a simplified boot flow by directly jumping from the 233TF-A to the Linux kernel, which will use a ramdisk as filesystem. This can be 234useful if both the kernel and the device tree blob (DTB) are already present in 235memory (like in FVP). 236 237For example, if the kernel is loaded at ``0x80080000`` and the DTB is loaded at 238address ``0x82000000``, the firmware can be built like this: 239 240.. code:: shell 241 242 CROSS_COMPILE=aarch64-none-elf- \ 243 make PLAT=fvp DEBUG=1 \ 244 RESET_TO_BL31=1 \ 245 ARM_LINUX_KERNEL_AS_BL33=1 \ 246 PRELOADED_BL33_BASE=0x80080000 \ 247 ARM_PRELOADED_DTB_BASE=0x82000000 \ 248 all fip 249 250Now, it is needed to modify the DTB so that the kernel knows the address of the 251ramdisk. The following script generates a patched DTB from the provided one, 252assuming that the ramdisk is loaded at address ``0x84000000``. Note that this 253script assumes that the user is using a ramdisk image prepared for U-Boot, like 254the ones provided by Linaro. If using a ramdisk without this header,the ``0x40`` 255offset in ``INITRD_START`` has to be removed. 256 257.. code:: bash 258 259 #!/bin/bash 260 261 # Path to the input DTB 262 KERNEL_DTB=<path-to>/<fdt> 263 # Path to the output DTB 264 PATCHED_KERNEL_DTB=<path-to>/<patched-fdt> 265 # Base address of the ramdisk 266 INITRD_BASE=0x84000000 267 # Path to the ramdisk 268 INITRD=<path-to>/<ramdisk.img> 269 270 # Skip uboot header (64 bytes) 271 INITRD_START=$(printf "0x%x" $((${INITRD_BASE} + 0x40)) ) 272 INITRD_SIZE=$(stat -Lc %s ${INITRD}) 273 INITRD_END=$(printf "0x%x" $((${INITRD_BASE} + ${INITRD_SIZE})) ) 274 275 CHOSEN_NODE=$(echo \ 276 "/ { \ 277 chosen { \ 278 linux,initrd-start = <${INITRD_START}>; \ 279 linux,initrd-end = <${INITRD_END}>; \ 280 }; \ 281 };") 282 283 echo $(dtc -O dts -I dtb ${KERNEL_DTB}) ${CHOSEN_NODE} | \ 284 dtc -O dtb -o ${PATCHED_KERNEL_DTB} - 285 286And the FVP binary can be run with the following command: 287 288.. code:: shell 289 290 <path-to>/FVP_Base_AEMv8A-AEMv8A \ 291 -C pctl.startup=0.0.0.0 \ 292 -C bp.secure_memory=1 \ 293 -C cluster0.NUM_CORES=4 \ 294 -C cluster1.NUM_CORES=4 \ 295 -C cache_state_modelled=1 \ 296 -C cluster0.cpu0.RVBAR=0x04001000 \ 297 -C cluster0.cpu1.RVBAR=0x04001000 \ 298 -C cluster0.cpu2.RVBAR=0x04001000 \ 299 -C cluster0.cpu3.RVBAR=0x04001000 \ 300 -C cluster1.cpu0.RVBAR=0x04001000 \ 301 -C cluster1.cpu1.RVBAR=0x04001000 \ 302 -C cluster1.cpu2.RVBAR=0x04001000 \ 303 -C cluster1.cpu3.RVBAR=0x04001000 \ 304 --data cluster0.cpu0="<path-to>/bl31.bin"@0x04001000 \ 305 --data cluster0.cpu0="<path-to>/<patched-fdt>"@0x82000000 \ 306 --data cluster0.cpu0="<path-to>/<kernel-binary>"@0x80080000 \ 307 --data cluster0.cpu0="<path-to>/<ramdisk.img>"@0x84000000 308 309Obtaining the Flattened Device Trees 310^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ 311 312Depending on the FVP configuration and Linux configuration used, different 313FDT files are required. FDT source files for the Foundation and Base FVPs can 314be found in the TF-A source directory under ``fdts/``. The Foundation FVP has 315a subset of the Base FVP components. For example, the Foundation FVP lacks 316CLCD and MMC support, and has only one CPU cluster. 317 318.. note:: 319 It is not recommended to use the FDTs built along the kernel because not 320 all FDTs are available from there. 321 322The dynamic configuration capability is enabled in the firmware for FVPs. 323This means that the firmware can authenticate and load the FDT if present in 324FIP. A default FDT is packaged into FIP during the build based on 325the build configuration. This can be overridden by using the ``FVP_HW_CONFIG`` 326or ``FVP_HW_CONFIG_DTS`` build options (refer to 327:ref:`build_options_arm_fvp_platform` for details on the options). 328 329- ``fvp-base-gicv2-psci.dts`` 330 331 For use with models such as the Cortex-A57-A53 Base FVPs without shifted 332 affinities and with Base memory map configuration. 333 334- ``fvp-base-gicv2-psci-aarch32.dts`` 335 336 For use with models such as the Cortex-A32 Base FVPs without shifted 337 affinities and running Linux in AArch32 state with Base memory map 338 configuration. 339 340- ``fvp-base-gicv3-psci.dts`` 341 342 For use with models such as the Cortex-A57-A53 Base FVPs without shifted 343 affinities and with Base memory map configuration and Linux GICv3 support. 344 345- ``fvp-base-gicv3-psci-1t.dts`` 346 347 For use with models such as the AEMv8-RevC Base FVP with shifted affinities, 348 single threaded CPUs, Base memory map configuration and Linux GICv3 support. 349 350- ``fvp-base-gicv3-psci-dynamiq.dts`` 351 352 For use with models as the Cortex-A55-A75 Base FVPs with shifted affinities, 353 single cluster, single threaded CPUs, Base memory map configuration and Linux 354 GICv3 support. 355 356- ``fvp-base-gicv3-psci-aarch32.dts`` 357 358 For use with models such as the Cortex-A32 Base FVPs without shifted 359 affinities and running Linux in AArch32 state with Base memory map 360 configuration and Linux GICv3 support. 361 362- ``fvp-foundation-gicv2-psci.dts`` 363 364 For use with Foundation FVP with Base memory map configuration. 365 366- ``fvp-foundation-gicv3-psci.dts`` 367 368 (Default) For use with Foundation FVP with Base memory map configuration 369 and Linux GICv3 support. 370 371 372Running on the Foundation FVP with reset to BL1 entrypoint 373^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ 374 375The following ``Foundation_Platform`` parameters should be used to boot Linux with 3764 CPUs using the AArch64 build of TF-A. 377 378.. code:: shell 379 380 <path-to>/Foundation_Platform \ 381 --cores=4 \ 382 --arm-v8.0 \ 383 --secure-memory \ 384 --visualization \ 385 --gicv3 \ 386 --data="<path-to>/<bl1-binary>"@0x0 \ 387 --data="<path-to>/<FIP-binary>"@0x08000000 \ 388 --data="<path-to>/<kernel-binary>"@0x80080000 \ 389 --data="<path-to>/<ramdisk-binary>"@0x84000000 390 391Notes: 392 393- BL1 is loaded at the start of the Trusted ROM. 394- The Firmware Image Package is loaded at the start of NOR FLASH0. 395- The firmware loads the FDT packaged in FIP to the DRAM. The FDT load address 396 is specified via the ``hw_config_addr`` property in `TB_FW_CONFIG for FVP`_. 397- The default use-case for the Foundation FVP is to use the ``--gicv3`` option 398 and enable the GICv3 device in the model. Note that without this option, 399 the Foundation FVP defaults to legacy (Versatile Express) memory map which 400 is not supported by TF-A. 401- In order for TF-A to run correctly on the Foundation FVP, the architecture 402 versions must match. The Foundation FVP defaults to the highest v8.x 403 version it supports but the default build for TF-A is for v8.0. To avoid 404 issues either start the Foundation FVP to use v8.0 architecture using the 405 ``--arm-v8.0`` option, or build TF-A with an appropriate value for 406 ``ARM_ARCH_MINOR``. 407 408Running on the AEMv8 Base FVP with reset to BL1 entrypoint 409^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ 410 411The following ``FVP_Base_RevC-2xAEMv8A`` parameters should be used to boot Linux 412with 8 CPUs using the AArch64 build of TF-A. 413 414.. code:: shell 415 416 <path-to>/FVP_Base_RevC-2xAEMv8A \ 417 -C pctl.startup=0.0.0.0 \ 418 -C bp.secure_memory=1 \ 419 -C bp.tzc_400.diagnostics=1 \ 420 -C cluster0.NUM_CORES=4 \ 421 -C cluster1.NUM_CORES=4 \ 422 -C cache_state_modelled=1 \ 423 -C bp.secureflashloader.fname="<path-to>/<bl1-binary>" \ 424 -C bp.flashloader0.fname="<path-to>/<FIP-binary>" \ 425 --data cluster0.cpu0="<path-to>/<kernel-binary>"@0x80080000 \ 426 --data cluster0.cpu0="<path-to>/<ramdisk>"@0x84000000 427 428.. note:: 429 The ``FVP_Base_RevC-2xAEMv8A`` has shifted affinities and requires 430 a specific DTS for all the CPUs to be loaded. 431 432Running on the AEMv8 Base FVP (AArch32) with reset to BL1 entrypoint 433^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ 434 435The following ``FVP_Base_AEMv8A-AEMv8A`` parameters should be used to boot Linux 436with 8 CPUs using the AArch32 build of TF-A. 437 438.. code:: shell 439 440 <path-to>/FVP_Base_AEMv8A-AEMv8A \ 441 -C pctl.startup=0.0.0.0 \ 442 -C bp.secure_memory=1 \ 443 -C bp.tzc_400.diagnostics=1 \ 444 -C cluster0.NUM_CORES=4 \ 445 -C cluster1.NUM_CORES=4 \ 446 -C cache_state_modelled=1 \ 447 -C cluster0.cpu0.CONFIG64=0 \ 448 -C cluster0.cpu1.CONFIG64=0 \ 449 -C cluster0.cpu2.CONFIG64=0 \ 450 -C cluster0.cpu3.CONFIG64=0 \ 451 -C cluster1.cpu0.CONFIG64=0 \ 452 -C cluster1.cpu1.CONFIG64=0 \ 453 -C cluster1.cpu2.CONFIG64=0 \ 454 -C cluster1.cpu3.CONFIG64=0 \ 455 -C bp.secureflashloader.fname="<path-to>/<bl1-binary>" \ 456 -C bp.flashloader0.fname="<path-to>/<FIP-binary>" \ 457 --data cluster0.cpu0="<path-to>/<kernel-binary>"@0x80080000 \ 458 --data cluster0.cpu0="<path-to>/<ramdisk>"@0x84000000 459 460Running on the Cortex-A57-A53 Base FVP with reset to BL1 entrypoint 461^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ 462 463The following ``FVP_Base_Cortex-A57x4-A53x4`` model parameters should be used to 464boot Linux with 8 CPUs using the AArch64 build of TF-A. 465 466.. code:: shell 467 468 <path-to>/FVP_Base_Cortex-A57x4-A53x4 \ 469 -C pctl.startup=0.0.0.0 \ 470 -C bp.secure_memory=1 \ 471 -C bp.tzc_400.diagnostics=1 \ 472 -C cache_state_modelled=1 \ 473 -C bp.secureflashloader.fname="<path-to>/<bl1-binary>" \ 474 -C bp.flashloader0.fname="<path-to>/<FIP-binary>" \ 475 --data cluster0.cpu0="<path-to>/<kernel-binary>"@0x80080000 \ 476 --data cluster0.cpu0="<path-to>/<ramdisk>"@0x84000000 477 478Running on the Cortex-A32 Base FVP (AArch32) with reset to BL1 entrypoint 479^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ 480 481The following ``FVP_Base_Cortex-A32x4`` model parameters should be used to 482boot Linux with 4 CPUs using the AArch32 build of TF-A. 483 484.. code:: shell 485 486 <path-to>/FVP_Base_Cortex-A32x4 \ 487 -C pctl.startup=0.0.0.0 \ 488 -C bp.secure_memory=1 \ 489 -C bp.tzc_400.diagnostics=1 \ 490 -C cache_state_modelled=1 \ 491 -C bp.secureflashloader.fname="<path-to>/<bl1-binary>" \ 492 -C bp.flashloader0.fname="<path-to>/<FIP-binary>" \ 493 --data cluster0.cpu0="<path-to>/<kernel-binary>"@0x80080000 \ 494 --data cluster0.cpu0="<path-to>/<ramdisk>"@0x84000000 495 496 497Running on the AEMv8 Base FVP with reset to BL31 entrypoint 498^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ 499 500The following ``FVP_Base_RevC-2xAEMv8A`` parameters should be used to boot Linux 501with 8 CPUs using the AArch64 build of TF-A. 502 503.. code:: shell 504 505 <path-to>/FVP_Base_RevC-2xAEMv8A \ 506 -C pctl.startup=0.0.0.0 \ 507 -C bp.secure_memory=1 \ 508 -C bp.tzc_400.diagnostics=1 \ 509 -C cluster0.NUM_CORES=4 \ 510 -C cluster1.NUM_CORES=4 \ 511 -C cache_state_modelled=1 \ 512 -C cluster0.cpu0.RVBAR=0x04010000 \ 513 -C cluster0.cpu1.RVBAR=0x04010000 \ 514 -C cluster0.cpu2.RVBAR=0x04010000 \ 515 -C cluster0.cpu3.RVBAR=0x04010000 \ 516 -C cluster1.cpu0.RVBAR=0x04010000 \ 517 -C cluster1.cpu1.RVBAR=0x04010000 \ 518 -C cluster1.cpu2.RVBAR=0x04010000 \ 519 -C cluster1.cpu3.RVBAR=0x04010000 \ 520 --data cluster0.cpu0="<path-to>/<bl31-binary>"@0x04010000 \ 521 --data cluster0.cpu0="<path-to>/<bl32-binary>"@0xff000000 \ 522 --data cluster0.cpu0="<path-to>/<bl33-binary>"@0x88000000 \ 523 --data cluster0.cpu0="<path-to>/<fdt>"@0x82000000 \ 524 --data cluster0.cpu0="<path-to>/<kernel-binary>"@0x80080000 \ 525 --data cluster0.cpu0="<path-to>/<ramdisk>"@0x84000000 526 527Notes: 528 529- If Position Independent Executable (PIE) support is enabled for BL31 530 in this config, it can be loaded at any valid address for execution. 531 532- Since a FIP is not loaded when using BL31 as reset entrypoint, the 533 ``--data="<path-to><bl31|bl32|bl33-binary>"@<base-address-of-binary>`` 534 parameter is needed to load the individual bootloader images in memory. 535 BL32 image is only needed if BL31 has been built to expect a Secure-EL1 536 Payload. For the same reason, the FDT needs to be compiled from the DT source 537 and loaded via the ``--data cluster0.cpu0="<path-to>/<fdt>"@0x82000000`` 538 parameter. 539 540- The ``FVP_Base_RevC-2xAEMv8A`` has shifted affinities and requires a 541 specific DTS for all the CPUs to be loaded. 542 543- The ``-C cluster<X>.cpu<Y>.RVBAR=@<base-address-of-bl31>`` parameter, where 544 X and Y are the cluster and CPU numbers respectively, is used to set the 545 reset vector for each core. 546 547- Changing the default value of ``ARM_TSP_RAM_LOCATION`` will also require 548 changing the value of 549 ``--data="<path-to><bl32-binary>"@<base-address-of-bl32>`` to the new value of 550 ``BL32_BASE``. 551 552 553Running on the AEMv8 Base FVP (AArch32) with reset to SP_MIN entrypoint 554^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ 555 556The following ``FVP_Base_AEMv8A-AEMv8A`` parameters should be used to boot Linux 557with 8 CPUs using the AArch32 build of TF-A. 558 559.. code:: shell 560 561 <path-to>/FVP_Base_AEMv8A-AEMv8A \ 562 -C pctl.startup=0.0.0.0 \ 563 -C bp.secure_memory=1 \ 564 -C bp.tzc_400.diagnostics=1 \ 565 -C cluster0.NUM_CORES=4 \ 566 -C cluster1.NUM_CORES=4 \ 567 -C cache_state_modelled=1 \ 568 -C cluster0.cpu0.CONFIG64=0 \ 569 -C cluster0.cpu1.CONFIG64=0 \ 570 -C cluster0.cpu2.CONFIG64=0 \ 571 -C cluster0.cpu3.CONFIG64=0 \ 572 -C cluster1.cpu0.CONFIG64=0 \ 573 -C cluster1.cpu1.CONFIG64=0 \ 574 -C cluster1.cpu2.CONFIG64=0 \ 575 -C cluster1.cpu3.CONFIG64=0 \ 576 -C cluster0.cpu0.RVBAR=0x04002000 \ 577 -C cluster0.cpu1.RVBAR=0x04002000 \ 578 -C cluster0.cpu2.RVBAR=0x04002000 \ 579 -C cluster0.cpu3.RVBAR=0x04002000 \ 580 -C cluster1.cpu0.RVBAR=0x04002000 \ 581 -C cluster1.cpu1.RVBAR=0x04002000 \ 582 -C cluster1.cpu2.RVBAR=0x04002000 \ 583 -C cluster1.cpu3.RVBAR=0x04002000 \ 584 --data cluster0.cpu0="<path-to>/<bl32-binary>"@0x04002000 \ 585 --data cluster0.cpu0="<path-to>/<bl33-binary>"@0x88000000 \ 586 --data cluster0.cpu0="<path-to>/<fdt>"@0x82000000 \ 587 --data cluster0.cpu0="<path-to>/<kernel-binary>"@0x80080000 \ 588 --data cluster0.cpu0="<path-to>/<ramdisk>"@0x84000000 589 590.. note:: 591 The load address of ``<bl32-binary>`` depends on the value ``BL32_BASE``. 592 It should match the address programmed into the RVBAR register as well. 593 594Running on the Cortex-A57-A53 Base FVP with reset to BL31 entrypoint 595^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ 596 597The following ``FVP_Base_Cortex-A57x4-A53x4`` model parameters should be used to 598boot Linux with 8 CPUs using the AArch64 build of TF-A. 599 600.. code:: shell 601 602 <path-to>/FVP_Base_Cortex-A57x4-A53x4 \ 603 -C pctl.startup=0.0.0.0 \ 604 -C bp.secure_memory=1 \ 605 -C bp.tzc_400.diagnostics=1 \ 606 -C cache_state_modelled=1 \ 607 -C cluster0.cpu0.RVBARADDR=0x04010000 \ 608 -C cluster0.cpu1.RVBARADDR=0x04010000 \ 609 -C cluster0.cpu2.RVBARADDR=0x04010000 \ 610 -C cluster0.cpu3.RVBARADDR=0x04010000 \ 611 -C cluster1.cpu0.RVBARADDR=0x04010000 \ 612 -C cluster1.cpu1.RVBARADDR=0x04010000 \ 613 -C cluster1.cpu2.RVBARADDR=0x04010000 \ 614 -C cluster1.cpu3.RVBARADDR=0x04010000 \ 615 --data cluster0.cpu0="<path-to>/<bl31-binary>"@0x04010000 \ 616 --data cluster0.cpu0="<path-to>/<bl32-binary>"@0xff000000 \ 617 --data cluster0.cpu0="<path-to>/<bl33-binary>"@0x88000000 \ 618 --data cluster0.cpu0="<path-to>/<fdt>"@0x82000000 \ 619 --data cluster0.cpu0="<path-to>/<kernel-binary>"@0x80080000 \ 620 --data cluster0.cpu0="<path-to>/<ramdisk>"@0x84000000 621 622Running on the Cortex-A32 Base FVP (AArch32) with reset to SP_MIN entrypoint 623^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ 624 625The following ``FVP_Base_Cortex-A32x4`` model parameters should be used to 626boot Linux with 4 CPUs using the AArch32 build of TF-A. 627 628.. code:: shell 629 630 <path-to>/FVP_Base_Cortex-A32x4 \ 631 -C pctl.startup=0.0.0.0 \ 632 -C bp.secure_memory=1 \ 633 -C bp.tzc_400.diagnostics=1 \ 634 -C cache_state_modelled=1 \ 635 -C cluster0.cpu0.RVBARADDR=0x04002000 \ 636 -C cluster0.cpu1.RVBARADDR=0x04002000 \ 637 -C cluster0.cpu2.RVBARADDR=0x04002000 \ 638 -C cluster0.cpu3.RVBARADDR=0x04002000 \ 639 --data cluster0.cpu0="<path-to>/<bl32-binary>"@0x04002000 \ 640 --data cluster0.cpu0="<path-to>/<bl33-binary>"@0x88000000 \ 641 --data cluster0.cpu0="<path-to>/<fdt>"@0x82000000 \ 642 --data cluster0.cpu0="<path-to>/<kernel-binary>"@0x80080000 \ 643 --data cluster0.cpu0="<path-to>/<ramdisk>"@0x84000000 644 645-------------- 646 647*Copyright (c) 2019-2021, Arm Limited. All rights reserved.* 648 649.. _TB_FW_CONFIG for FVP: https://git.trustedfirmware.org/TF-A/trusted-firmware-a.git/tree/plat/arm/board/fvp/fdts/fvp_tb_fw_config.dts 650.. _Arm's website: `FVP models`_ 651.. _FVP models: https://developer.arm.com/products/system-design/fixed-virtual-platforms 652.. _Linaro Release 19.06: http://releases.linaro.org/members/arm/platforms/19.06 653.. _Arm FVP website: https://developer.arm.com/products/system-design/fixed-virtual-platforms 654