1 /* 2 * Copyright (c) 2019, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef PLATFORM_DEF_H 8 #define PLATFORM_DEF_H 9 10 #include <arch.h> 11 #include <drivers/arm/gic_common.h> 12 13 #define PLAT_PRIMARY_CPU 0x0 14 15 #define IO_PHYS 0x10000000 16 #define INFRACFG_AO_BASE (IO_PHYS + 0x1000) 17 #define PERI_BASE (IO_PHYS + 0x3000) 18 #define GPIO_BASE (IO_PHYS + 0x5000) 19 #define SPM_BASE (IO_PHYS + 0x6000) 20 #define SLEEP_REG_MD_BASE (IO_PHYS + 0xf000) 21 #define RGU_BASE (IO_PHYS + 0x7000) 22 #define I2C4_BASE_SE (IO_PHYS + 0x1008000) 23 #define I2C2_BASE_SE (IO_PHYS + 0x1009000) 24 #define PMIC_WRAP_BASE (IO_PHYS + 0xd000) 25 #define MCUCFG_BASE 0x0c530000 26 #define CFG_SF_CTRL 0x0c510014 27 #define CFG_SF_INI 0x0c510010 28 #define EMI_BASE (IO_PHYS + 0x219000) 29 #define EMI_MPU_BASE (IO_PHYS + 0x226000) 30 #define TRNG_base (IO_PHYS + 0x20f000) 31 #define MT_GIC_BASE 0x0c000000 32 #define PLAT_MT_CCI_BASE 0x0c500000 33 #define CCI_SIZE 0x00010000 34 #define EINT_BASE 0x1000b000 35 #define DVFSRC_BASE (IO_PHYS + 0x12000) 36 37 #define SSPM_CFGREG_BASE (IO_PHYS + 0x440000) 38 #define SSPM_MBOX_3_BASE (IO_PHYS + 0x480000) 39 40 #define INFRACFG_AO_BASE (IO_PHYS + 0x1000) 41 42 #define TOPCKGEN_BASE (IO_PHYS + 0x0) 43 #define CLK_SCP_CFG_0 (TOPCKGEN_BASE + 0x200) 44 #define CLK_SCP_CFG_1 (TOPCKGEN_BASE + 0x204) 45 46 #define APMIXEDSYS (IO_PHYS + 0xC000) 47 #define AP_PLL_CON3 (APMIXEDSYS + 0xC) 48 #define AP_PLL_CON4 (APMIXEDSYS + 0x10) 49 #define AP_PLL_CON6 (APMIXEDSYS + 0x18) 50 #define ARMPLL_LL_CON0 (APMIXEDSYS + 0x200) 51 #define ARMPLL_L_CON0 (APMIXEDSYS + 0x210) 52 #define ARMPLL_L_PWR_CON0 (APMIXEDSYS + 0x21c) 53 #define MAINPLL_CON0 (APMIXEDSYS + 0x220) 54 #define CCIPLL_CON0 (APMIXEDSYS + 0x290) 55 56 #define TOP_CKMUXSEL (INFRACFG_AO_BASE + 0x0) 57 58 #define armpll_mux1_sel_big_mask (0xf << 4) 59 #define armpll_mux1_sel_big_ARMSPLL (0x1 << 4) 60 #define armpll_mux1_sel_sml_mask (0xf << 8) 61 #define armpll_mux1_sel_sml_ARMSPLL (0x1 << 8) 62 63 64 /* Aggregate of all devices in the first GB */ 65 #define MTK_DEV_RNG0_BASE IO_PHYS 66 #define MTK_DEV_RNG0_SIZE 0x490000 67 #define MTK_DEV_RNG1_BASE (IO_PHYS + 0x1000000) 68 #define MTK_DEV_RNG1_SIZE 0x4000000 69 #define MTK_DEV_RNG2_BASE 0x0c000000 70 #define MTK_DEV_RNG2_SIZE 0x600000 71 #define MT_MCUSYS_SIZE 0x90000 72 #define RAM_CONSOLE_BASE 0x11d000 73 #define RAM_CONSOLE_SIZE 0x1000 74 75 /******************************************************************************* 76 * MSDC 77 ******************************************************************************/ 78 #define MSDC0_BASE (IO_PHYS + 0x01230000) 79 80 /******************************************************************************* 81 * MCUSYS related constants 82 ******************************************************************************/ 83 #define MT_L2_WRITE_ACCESS_RATE (MCUCFG_BASE + 0x604) 84 #define MP0_CA7L_CACHE_CONFIG (MCUCFG_BASE + 0x7f0) 85 #define MP1_CA7L_CACHE_CONFIG (MCUCFG_BASE + 0x7f4) 86 #define EMI_WFIFO (MCUCFG_BASE + 0x0b5c) 87 88 /******************************************************************************* 89 * GIC related constants 90 ******************************************************************************/ 91 #define MT_POLARITY_LOW 0 92 #define MT_POLARITY_HIGH 1 93 #define MT_EDGE_SENSITIVE 1 94 #define MT_LEVEL_SENSITIVE 0 95 96 /******************************************************************************* 97 * UART related constants 98 ******************************************************************************/ 99 #define UART0_BASE (IO_PHYS + 0x01002000) 100 #define UART1_BASE (IO_PHYS + 0x01003000) 101 102 #define UART_BAUDRATE 115200 103 #define UART_CLOCK 26000000 104 105 /******************************************************************************* 106 * System counter frequency related constants 107 ******************************************************************************/ 108 #define SYS_COUNTER_FREQ_IN_TICKS 13000000 109 #define SYS_COUNTER_FREQ_IN_MHZ 13 110 111 /******************************************************************************* 112 * GIC-400 & interrupt handling related constants 113 ******************************************************************************/ 114 115 /* Base MTK_platform compatible GIC memory map */ 116 #define BASE_GICD_BASE MT_GIC_BASE 117 #define BASE_GICC_BASE (MT_GIC_BASE + 0x400000) 118 #define MT_GIC_RDIST_BASE (MT_GIC_BASE + 0x100000) 119 #define BASE_GICR_BASE (MT_GIC_BASE + 0x100000) 120 #define BASE_GICH_BASE (MT_GIC_BASE + 0x4000) 121 #define BASE_GICV_BASE (MT_GIC_BASE + 0x6000) 122 #define INT_POL_CTL0 (MCUCFG_BASE + 0xa80) 123 #define SEC_POL_CTL_EN0 (MCUCFG_BASE + 0xa00) 124 #define GIC_SYNC_DCM (MCUCFG_BASE + 0x758) 125 #define GIC_SYNC_DCM_MASK 0x3 126 #define GIC_SYNC_DCM_ON 0x3 127 #define GIC_SYNC_DCM_OFF 0x0 128 #define GIC_PRIVATE_SIGNALS 32 129 130 #define PLAT_ARM_GICD_BASE BASE_GICD_BASE 131 #define PLAT_ARM_GICC_BASE BASE_GICC_BASE 132 133 #define PLAT_ARM_G1S_IRQ_PROPS(grp) ( \ 134 INTR_PROP_DESC(MT_IRQ_SEC_SGI_0, GIC_HIGHEST_SEC_PRIORITY, grp, \ 135 GIC_INTR_CFG_EDGE), \ 136 INTR_PROP_DESC(MT_IRQ_SEC_SGI_1, GIC_HIGHEST_SEC_PRIORITY, grp, \ 137 GIC_INTR_CFG_EDGE), \ 138 INTR_PROP_DESC(MT_IRQ_SEC_SGI_2, GIC_HIGHEST_SEC_PRIORITY, grp, \ 139 GIC_INTR_CFG_EDGE), \ 140 INTR_PROP_DESC(MT_IRQ_SEC_SGI_3, GIC_HIGHEST_SEC_PRIORITY, grp, \ 141 GIC_INTR_CFG_EDGE), \ 142 INTR_PROP_DESC(MT_IRQ_SEC_SGI_4, GIC_HIGHEST_SEC_PRIORITY, grp, \ 143 GIC_INTR_CFG_EDGE), \ 144 INTR_PROP_DESC(MT_IRQ_SEC_SGI_5, GIC_HIGHEST_SEC_PRIORITY, grp, \ 145 GIC_INTR_CFG_EDGE), \ 146 INTR_PROP_DESC(MT_IRQ_SEC_SGI_6, GIC_HIGHEST_SEC_PRIORITY, grp, \ 147 GIC_INTR_CFG_EDGE), \ 148 INTR_PROP_DESC(MT_IRQ_SEC_SGI_7, GIC_HIGHEST_SEC_PRIORITY, grp, \ 149 GIC_INTR_CFG_EDGE)) \ 150 151 #define PLAT_ARM_G0_IRQ_PROPS(grp) 152 153 /******************************************************************************* 154 * CCI-400 related constants 155 ******************************************************************************/ 156 #define PLAT_MT_CCI_CLUSTER0_SL_IFACE_IX 4 157 #define PLAT_MT_CCI_CLUSTER1_SL_IFACE_IX 3 158 159 /******************************************************************************* 160 * WDT Registers 161 ******************************************************************************/ 162 #define MTK_WDT_BASE (IO_PHYS + 0x00007000) 163 #define MTK_WDT_SIZE 0x1000 164 #define MTK_WDT_MODE (MTK_WDT_BASE + 0x0000) 165 #define MTK_WDT_LENGTH (MTK_WDT_BASE + 0x0004) 166 #define MTK_WDT_RESTART (MTK_WDT_BASE + 0x0008) 167 #define MTK_WDT_STATUS (MTK_WDT_BASE + 0x000C) 168 #define MTK_WDT_INTERVAL (MTK_WDT_BASE + 0x0010) 169 #define MTK_WDT_SWRST (MTK_WDT_BASE + 0x0014) 170 #define MTK_WDT_SWSYSRST (MTK_WDT_BASE + 0x0018) 171 #define MTK_WDT_NONRST_REG (MTK_WDT_BASE + 0x0020) 172 #define MTK_WDT_NONRST_REG2 (MTK_WDT_BASE + 0x0024) 173 #define MTK_WDT_REQ_MODE (MTK_WDT_BASE + 0x0030) 174 #define MTK_WDT_REQ_IRQ_EN (MTK_WDT_BASE + 0x0034) 175 #define MTK_WDT_EXT_REQ_CON (MTK_WDT_BASE + 0x0038) 176 #define MTK_WDT_DEBUG_CTL (MTK_WDT_BASE + 0x0040) 177 #define MTK_WDT_LATCH_CTL (MTK_WDT_BASE + 0x0044) 178 #define MTK_WDT_DEBUG_CTL2 (MTK_WDT_BASE + 0x00A0) 179 #define MTK_WDT_COUNTER (MTK_WDT_BASE + 0x0514) 180 181 /* WDT_STATUS */ 182 #define MTK_WDT_STATUS_SPM_THERMAL_RST (1 << 0) 183 #define MTK_WDT_STATUS_SPM_RST (1 << 1) 184 #define MTK_WDT_STATUS_EINT_RST (1 << 2) 185 #define MTK_WDT_STATUS_SYSRST_RST (1 << 3) /* from PMIC */ 186 #define MTK_WDT_STATUS_DVFSP_RST (1 << 4) 187 #define MTK_WDT_STATUS_PMCU_RST (1 << 16) 188 #define MTK_WDT_STATUS_MDDBG_RST (1 << 17) 189 #define MTK_WDT_STATUS_THERMAL_DIRECT_RST (1 << 18) 190 #define MTK_WDT_STATUS_DEBUG_RST (1 << 19) 191 #define MTK_WDT_STATUS_SECURITY_RST (1 << 28) 192 #define MTK_WDT_STATUS_IRQ_ASSERT (1 << 29) 193 #define MTK_WDT_STATUS_SW_WDT_RST (1 << 30) 194 #define MTK_WDT_STATUS_HW_WDT_RST (1U << 31) 195 196 /* RGU other related */ 197 #define MTK_WDT_MODE_DUAL_MODE 0x0040 198 #define MTK_WDT_MODE_IRQ 0x0008 199 #define MTK_WDT_MODE_KEY 0x22000000 200 #define MTK_WDT_MODE_EXTEN 0x0004 201 #define MTK_WDT_SWRST_KEY 0x1209 202 #define MTK_WDT_RESTART_KEY 0x1971 203 204 /******************************************************************************* 205 * TRNG Registers 206 ******************************************************************************/ 207 #define TRNG_BASE_ADDR TRNG_base 208 #define TRNG_BASE_SIZE 0x1000 209 #define TRNG_CTRL (TRNG_base + 0x0000) 210 #define TRNG_TIME (TRNG_base + 0x0004) 211 #define TRNG_DATA (TRNG_base + 0x0008) 212 #define TRNG_PDN_base 0x10001000 213 #define TRNG_PDN_BASE_ADDR TRNG_PDN_BASE_ADDR 214 #define TRNG_PDN_BASE_SIZE 0x1000 215 #define TRNG_PDN_SET (TRNG_PDN_base + 0x0088) 216 #define TRNG_PDN_CLR (TRNG_PDN_base + 0x008c) 217 #define TRNG_PDN_STATUS (TRNG_PDN_base + 0x0094) 218 #define TRNG_CTRL_RDY 0x80000000 219 #define TRNG_CTRL_START 0x00000001 220 #define TRNG_PDN_VALUE 0x200 221 222 /* FIQ platform related define */ 223 #define MT_IRQ_SEC_SGI_0 8 224 #define MT_IRQ_SEC_SGI_1 9 225 #define MT_IRQ_SEC_SGI_2 10 226 #define MT_IRQ_SEC_SGI_3 11 227 #define MT_IRQ_SEC_SGI_4 12 228 #define MT_IRQ_SEC_SGI_5 13 229 #define MT_IRQ_SEC_SGI_6 14 230 #define MT_IRQ_SEC_SGI_7 15 231 232 #define FIQ_SMP_CALL_SGI 13 233 #define WDT_IRQ_BIT_ID 174 234 #define ATF_LOG_IRQ_ID 277 235 236 #define ATF_AMMS_IRQ_ID 338 237 #define PCCIF1_IRQ0_BIT_ID 185 238 #define PCCIF1_IRQ1_BIT_ID 186 239 240 #define DEBUG_XLAT_TABLE 0 241 242 /******************************************************************************* 243 * Platform binary types for linking 244 ******************************************************************************/ 245 #define PLATFORM_LINKER_FORMAT "elf64-littleaarch64" 246 #define PLATFORM_LINKER_ARCH aarch64 247 248 /******************************************************************************* 249 * Generic platform constants 250 ******************************************************************************/ 251 252 /* Size of cacheable stacks */ 253 #if DEBUG_XLAT_TABLE 254 #define PLATFORM_STACK_SIZE 0x800 255 #elif IMAGE_BL1 256 #define PLATFORM_STACK_SIZE 0x440 257 #elif IMAGE_BL2 258 #define PLATFORM_STACK_SIZE 0x400 259 #elif IMAGE_BL31 260 #define PLATFORM_STACK_SIZE 0x800 261 #elif IMAGE_BL32 262 #define PLATFORM_STACK_SIZE 0x440 263 #endif 264 265 #define FIRMWARE_WELCOME_STR "Booting Trusted Firmware\n" 266 #define PLAT_MAX_PWR_LVL U(2) 267 #define PLAT_MAX_RET_STATE U(1) 268 #define PLAT_MAX_OFF_STATE U(2) 269 270 #define PLATFORM_CACHE_LINE_SIZE 64 271 #define PLATFORM_SYSTEM_COUNT U(1) 272 #define PLATFORM_CLUSTER_COUNT U(2) 273 #define PLATFORM_CLUSTER0_CORE_COUNT U(4) 274 #define PLATFORM_CLUSTER1_CORE_COUNT U(4) 275 #define PLATFORM_CORE_COUNT (PLATFORM_CLUSTER1_CORE_COUNT + \ 276 PLATFORM_CLUSTER0_CORE_COUNT) 277 #define PLATFORM_MAX_CPUS_PER_CLUSTER U(4) 278 #define PLATFORM_NUM_AFFS (PLATFORM_SYSTEM_COUNT + \ 279 PLATFORM_CLUSTER_COUNT + \ 280 PLATFORM_CORE_COUNT) 281 282 #define SOC_CHIP_ID U(0x8183) 283 284 /******************************************************************************* 285 * Platform memory map related constants 286 ******************************************************************************/ 287 288 #define TZRAM_BASE 0x54600000 289 #define TZRAM_SIZE 0x00030000 290 291 /******************************************************************************* 292 * BL31 specific defines. 293 ******************************************************************************/ 294 /* 295 * Put BL31 at the top of the Trusted SRAM (just below the shared memory, if 296 * present). BL31_BASE is calculated using the current BL31 debug size plus a 297 * little space for growth. 298 */ 299 #define BL31_BASE (TZRAM_BASE + 0x1000) 300 #define BL31_LIMIT (TZRAM_BASE + TZRAM_SIZE) 301 302 /******************************************************************************* 303 * Platform specific page table and MMU setup constants 304 ******************************************************************************/ 305 #define PLAT_PHY_ADDR_SPACE_SIZE (1ULL << 32) 306 #define PLAT_VIRT_ADDR_SPACE_SIZE (1ULL << 32) 307 #define MAX_XLAT_TABLES 16 308 #define MAX_MMAP_REGIONS 16 309 310 /******************************************************************************* 311 * Declarations and constants to access the mailboxes safely. Each mailbox is 312 * aligned on the biggest cache line size in the platform. This is known only 313 * to the platform as it might have a combination of integrated and external 314 * caches. Such alignment ensures that two maiboxes do not sit on the same cache 315 * line at any cache level. They could belong to different cpus/clusters & 316 * get written while being protected by different locks causing corruption of 317 * a valid mailbox address. 318 ******************************************************************************/ 319 #define CACHE_WRITEBACK_SHIFT 6 320 #define CACHE_WRITEBACK_GRANULE (1 << CACHE_WRITEBACK_SHIFT) 321 #endif /* PLATFORM_DEF_H */ 322