1 /*
2 * Copyright (c) 2015-2021, ARM Limited and Contributors. All rights reserved.
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7 #include <assert.h>
8 #include <string.h>
9
10 #include <platform_def.h>
11
12 #include <arch_helpers.h>
13 #include <common/bl_common.h>
14 #include <common/debug.h>
15 #include <common/desc_image_load.h>
16 #include <drivers/delay_timer.h>
17 #include <drivers/generic_delay_timer.h>
18 #include <drivers/st/bsec.h>
19 #include <drivers/st/stm32_console.h>
20 #include <drivers/st/stm32_iwdg.h>
21 #include <drivers/st/stm32mp_pmic.h>
22 #include <drivers/st/stm32mp_reset.h>
23 #include <drivers/st/stm32mp1_clk.h>
24 #include <drivers/st/stm32mp1_pwr.h>
25 #include <drivers/st/stm32mp1_ram.h>
26 #include <lib/mmio.h>
27 #include <lib/optee_utils.h>
28 #include <lib/xlat_tables/xlat_tables_v2.h>
29 #include <plat/common/platform.h>
30
31 #include <stm32mp1_context.h>
32 #include <stm32mp1_dbgmcu.h>
33
34 #define RESET_TIMEOUT_US_1MS 1000U
35
36 static console_t console;
37 static struct stm32mp_auth_ops stm32mp1_auth_ops;
38
print_reset_reason(void)39 static void print_reset_reason(void)
40 {
41 uint32_t rstsr = mmio_read_32(stm32mp_rcc_base() + RCC_MP_RSTSCLRR);
42
43 if (rstsr == 0U) {
44 WARN("Reset reason unknown\n");
45 return;
46 }
47
48 INFO("Reset reason (0x%x):\n", rstsr);
49
50 if ((rstsr & RCC_MP_RSTSCLRR_PADRSTF) == 0U) {
51 if ((rstsr & RCC_MP_RSTSCLRR_STDBYRSTF) != 0U) {
52 INFO("System exits from STANDBY\n");
53 return;
54 }
55
56 if ((rstsr & RCC_MP_RSTSCLRR_CSTDBYRSTF) != 0U) {
57 INFO("MPU exits from CSTANDBY\n");
58 return;
59 }
60 }
61
62 if ((rstsr & RCC_MP_RSTSCLRR_PORRSTF) != 0U) {
63 INFO(" Power-on Reset (rst_por)\n");
64 return;
65 }
66
67 if ((rstsr & RCC_MP_RSTSCLRR_BORRSTF) != 0U) {
68 INFO(" Brownout Reset (rst_bor)\n");
69 return;
70 }
71
72 if ((rstsr & RCC_MP_RSTSCLRR_MCSYSRSTF) != 0U) {
73 if ((rstsr & RCC_MP_RSTSCLRR_PADRSTF) != 0U) {
74 INFO(" System reset generated by MCU (MCSYSRST)\n");
75 } else {
76 INFO(" Local reset generated by MCU (MCSYSRST)\n");
77 }
78 return;
79 }
80
81 if ((rstsr & RCC_MP_RSTSCLRR_MPSYSRSTF) != 0U) {
82 INFO(" System reset generated by MPU (MPSYSRST)\n");
83 return;
84 }
85
86 if ((rstsr & RCC_MP_RSTSCLRR_HCSSRSTF) != 0U) {
87 INFO(" Reset due to a clock failure on HSE\n");
88 return;
89 }
90
91 if ((rstsr & RCC_MP_RSTSCLRR_IWDG1RSTF) != 0U) {
92 INFO(" IWDG1 Reset (rst_iwdg1)\n");
93 return;
94 }
95
96 if ((rstsr & RCC_MP_RSTSCLRR_IWDG2RSTF) != 0U) {
97 INFO(" IWDG2 Reset (rst_iwdg2)\n");
98 return;
99 }
100
101 if ((rstsr & RCC_MP_RSTSCLRR_MPUP0RSTF) != 0U) {
102 INFO(" MPU Processor 0 Reset\n");
103 return;
104 }
105
106 if ((rstsr & RCC_MP_RSTSCLRR_MPUP1RSTF) != 0U) {
107 INFO(" MPU Processor 1 Reset\n");
108 return;
109 }
110
111 if ((rstsr & RCC_MP_RSTSCLRR_PADRSTF) != 0U) {
112 INFO(" Pad Reset from NRST\n");
113 return;
114 }
115
116 if ((rstsr & RCC_MP_RSTSCLRR_VCORERSTF) != 0U) {
117 INFO(" Reset due to a failure of VDD_CORE\n");
118 return;
119 }
120
121 ERROR(" Unidentified reset reason\n");
122 }
123
bl2_el3_early_platform_setup(u_register_t arg0,u_register_t arg1 __unused,u_register_t arg2 __unused,u_register_t arg3 __unused)124 void bl2_el3_early_platform_setup(u_register_t arg0,
125 u_register_t arg1 __unused,
126 u_register_t arg2 __unused,
127 u_register_t arg3 __unused)
128 {
129 stm32mp_save_boot_ctx_address(arg0);
130 }
131
bl2_platform_setup(void)132 void bl2_platform_setup(void)
133 {
134 int ret;
135 uint32_t ddr_ns_size;
136
137 if (dt_pmic_status() > 0) {
138 initialize_pmic();
139 }
140
141 ret = stm32mp1_ddr_probe();
142 if (ret < 0) {
143 ERROR("Invalid DDR init: error %d\n", ret);
144 panic();
145 }
146
147 ddr_ns_size = stm32mp_get_ddr_ns_size();
148 assert(ddr_ns_size > 0U);
149
150 /* Map non secure DDR for BL33 load, now with cacheable attribute */
151 ret = mmap_add_dynamic_region(STM32MP_DDR_BASE, STM32MP_DDR_BASE,
152 ddr_ns_size, MT_MEMORY | MT_RW | MT_NS);
153 assert(ret == 0);
154
155 #ifdef AARCH32_SP_OPTEE
156 INFO("BL2 runs OP-TEE setup\n");
157
158 /* Map secure DDR for OP-TEE paged area */
159 ret = mmap_add_dynamic_region(STM32MP_DDR_BASE + ddr_ns_size,
160 STM32MP_DDR_BASE + ddr_ns_size,
161 STM32MP_DDR_S_SIZE,
162 MT_MEMORY | MT_RW | MT_SECURE);
163 assert(ret == 0);
164
165 /* Initialize tzc400 after DDR initialization */
166 stm32mp1_security_setup();
167 #else
168 INFO("BL2 runs SP_MIN setup\n");
169 #endif
170 }
171
bl2_el3_plat_arch_setup(void)172 void bl2_el3_plat_arch_setup(void)
173 {
174 int32_t result;
175 struct dt_node_info dt_uart_info;
176 const char *board_model;
177 boot_api_context_t *boot_context =
178 (boot_api_context_t *)stm32mp_get_boot_ctx_address();
179 uint32_t clk_rate;
180 uintptr_t pwr_base;
181 uintptr_t rcc_base;
182
183 mmap_add_region(BL_CODE_BASE, BL_CODE_BASE,
184 BL_CODE_END - BL_CODE_BASE,
185 MT_CODE | MT_SECURE);
186
187 #ifdef AARCH32_SP_OPTEE
188 mmap_add_region(STM32MP_OPTEE_BASE, STM32MP_OPTEE_BASE,
189 STM32MP_OPTEE_SIZE,
190 MT_MEMORY | MT_RW | MT_SECURE);
191 #endif
192 /* Prevent corruption of preloaded Device Tree */
193 mmap_add_region(DTB_BASE, DTB_BASE,
194 DTB_LIMIT - DTB_BASE,
195 MT_RO_DATA | MT_SECURE);
196
197 configure_mmu();
198
199 if (dt_open_and_check() < 0) {
200 panic();
201 }
202
203 pwr_base = stm32mp_pwr_base();
204 rcc_base = stm32mp_rcc_base();
205
206 /*
207 * Disable the backup domain write protection.
208 * The protection is enable at each reset by hardware
209 * and must be disabled by software.
210 */
211 mmio_setbits_32(pwr_base + PWR_CR1, PWR_CR1_DBP);
212
213 while ((mmio_read_32(pwr_base + PWR_CR1) & PWR_CR1_DBP) == 0U) {
214 ;
215 }
216
217 if (bsec_probe() != 0) {
218 panic();
219 }
220
221 /* Reset backup domain on cold boot cases */
222 if ((mmio_read_32(rcc_base + RCC_BDCR) & RCC_BDCR_RTCSRC_MASK) == 0U) {
223 mmio_setbits_32(rcc_base + RCC_BDCR, RCC_BDCR_VSWRST);
224
225 while ((mmio_read_32(rcc_base + RCC_BDCR) & RCC_BDCR_VSWRST) ==
226 0U) {
227 ;
228 }
229
230 mmio_clrbits_32(rcc_base + RCC_BDCR, RCC_BDCR_VSWRST);
231 }
232
233 /* Disable MCKPROT */
234 mmio_clrbits_32(rcc_base + RCC_TZCR, RCC_TZCR_MCKPROT);
235
236 generic_delay_timer_init();
237
238 if (stm32mp1_clk_probe() < 0) {
239 panic();
240 }
241
242 if (stm32mp1_clk_init() < 0) {
243 panic();
244 }
245
246 stm32mp1_syscfg_init();
247
248 result = dt_get_stdout_uart_info(&dt_uart_info);
249
250 if ((result <= 0) ||
251 (dt_uart_info.status == 0U) ||
252 (dt_uart_info.clock < 0) ||
253 (dt_uart_info.reset < 0)) {
254 goto skip_console_init;
255 }
256
257 if (dt_set_stdout_pinctrl() != 0) {
258 goto skip_console_init;
259 }
260
261 stm32mp_clk_enable((unsigned long)dt_uart_info.clock);
262
263 if (stm32mp_reset_assert((uint32_t)dt_uart_info.reset,
264 RESET_TIMEOUT_US_1MS) != 0) {
265 panic();
266 }
267
268 udelay(2);
269
270 if (stm32mp_reset_deassert((uint32_t)dt_uart_info.reset,
271 RESET_TIMEOUT_US_1MS) != 0) {
272 panic();
273 }
274
275 mdelay(1);
276
277 clk_rate = stm32mp_clk_get_rate((unsigned long)dt_uart_info.clock);
278
279 if (console_stm32_register(dt_uart_info.base, clk_rate,
280 STM32MP_UART_BAUDRATE, &console) == 0) {
281 panic();
282 }
283
284 console_set_scope(&console, CONSOLE_FLAG_BOOT |
285 CONSOLE_FLAG_CRASH | CONSOLE_FLAG_TRANSLATE_CRLF);
286
287 stm32mp_print_cpuinfo();
288
289 board_model = dt_get_board_model();
290 if (board_model != NULL) {
291 NOTICE("Model: %s\n", board_model);
292 }
293
294 stm32mp_print_boardinfo();
295
296 if (boot_context->auth_status != BOOT_API_CTX_AUTH_NO) {
297 NOTICE("Bootrom authentication %s\n",
298 (boot_context->auth_status == BOOT_API_CTX_AUTH_FAILED) ?
299 "failed" : "succeeded");
300 }
301
302 skip_console_init:
303 if (stm32_iwdg_init() < 0) {
304 panic();
305 }
306
307 stm32_iwdg_refresh();
308
309 result = stm32mp1_dbgmcu_freeze_iwdg2();
310 if (result != 0) {
311 INFO("IWDG2 freeze error : %i\n", result);
312 }
313
314 if (stm32_save_boot_interface(boot_context->boot_interface_selected,
315 boot_context->boot_interface_instance) !=
316 0) {
317 ERROR("Cannot save boot interface\n");
318 }
319
320 stm32mp1_auth_ops.check_key = boot_context->bootrom_ecdsa_check_key;
321 stm32mp1_auth_ops.verify_signature =
322 boot_context->bootrom_ecdsa_verify_signature;
323
324 stm32mp_init_auth(&stm32mp1_auth_ops);
325
326 stm32mp1_arch_security_setup();
327
328 print_reset_reason();
329
330 stm32mp_io_setup();
331 }
332
333 #if defined(AARCH32_SP_OPTEE)
334 /*******************************************************************************
335 * This function can be used by the platforms to update/use image
336 * information for given `image_id`.
337 ******************************************************************************/
bl2_plat_handle_post_image_load(unsigned int image_id)338 int bl2_plat_handle_post_image_load(unsigned int image_id)
339 {
340 int err = 0;
341 bl_mem_params_node_t *bl_mem_params = get_bl_mem_params_node(image_id);
342 bl_mem_params_node_t *bl32_mem_params;
343 bl_mem_params_node_t *pager_mem_params;
344 bl_mem_params_node_t *paged_mem_params;
345
346 assert(bl_mem_params != NULL);
347
348 switch (image_id) {
349 case BL32_IMAGE_ID:
350 bl_mem_params->ep_info.pc =
351 bl_mem_params->image_info.image_base;
352
353 pager_mem_params = get_bl_mem_params_node(BL32_EXTRA1_IMAGE_ID);
354 assert(pager_mem_params != NULL);
355 pager_mem_params->image_info.image_base = STM32MP_OPTEE_BASE;
356 pager_mem_params->image_info.image_max_size =
357 STM32MP_OPTEE_SIZE;
358
359 paged_mem_params = get_bl_mem_params_node(BL32_EXTRA2_IMAGE_ID);
360 assert(paged_mem_params != NULL);
361 paged_mem_params->image_info.image_base = STM32MP_DDR_BASE +
362 stm32mp_get_ddr_ns_size();
363 paged_mem_params->image_info.image_max_size =
364 STM32MP_DDR_S_SIZE;
365
366 err = parse_optee_header(&bl_mem_params->ep_info,
367 &pager_mem_params->image_info,
368 &paged_mem_params->image_info);
369 if (err) {
370 ERROR("OPTEE header parse error.\n");
371 panic();
372 }
373
374 /* Set optee boot info from parsed header data */
375 bl_mem_params->ep_info.pc =
376 pager_mem_params->image_info.image_base;
377 bl_mem_params->ep_info.args.arg0 =
378 paged_mem_params->image_info.image_base;
379 bl_mem_params->ep_info.args.arg1 = 0; /* Unused */
380 bl_mem_params->ep_info.args.arg2 = 0; /* No DT supported */
381 break;
382
383 case BL33_IMAGE_ID:
384 bl32_mem_params = get_bl_mem_params_node(BL32_IMAGE_ID);
385 assert(bl32_mem_params != NULL);
386 bl32_mem_params->ep_info.lr_svc = bl_mem_params->ep_info.pc;
387 break;
388
389 default:
390 /* Do nothing in default case */
391 break;
392 }
393
394 return err;
395 }
396 #endif
397