1 /*
2 * Copyright (c) 2020, ARM Limited and Contributors. All rights reserved.
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7 #include <assert.h>
8 #include <bl31/interrupt_mgmt.h>
9 #include <common/bl_common.h>
10 #include <common/ep_info.h>
11 #include <lib/mmio.h>
12 #include <lib/xlat_tables/xlat_tables_v2.h>
13 #include <platform_def.h>
14 #include <stdint.h>
15
16 /*******************************************************************************
17 * Platform memory map regions
18 ******************************************************************************/
19 #define MAP_NSDRAM0 MAP_REGION_FLAT(AML_NSDRAM0_BASE, \
20 AML_NSDRAM0_SIZE, \
21 MT_MEMORY | MT_RW | MT_NS)
22
23 #define MAP_NS_SHARE_MEM MAP_REGION_FLAT(AML_NS_SHARE_MEM_BASE, \
24 AML_NS_SHARE_MEM_SIZE, \
25 MT_MEMORY | MT_RW | MT_NS)
26
27 #define MAP_SEC_SHARE_MEM MAP_REGION_FLAT(AML_SEC_SHARE_MEM_BASE, \
28 AML_SEC_SHARE_MEM_SIZE, \
29 MT_MEMORY | MT_RW | MT_SECURE)
30
31 #define MAP_SEC_DEVICE0 MAP_REGION_FLAT(AML_SEC_DEVICE0_BASE, \
32 AML_SEC_DEVICE0_SIZE, \
33 MT_DEVICE | MT_RW)
34
35 #define MAP_GIC_DEVICE MAP_REGION_FLAT(AML_GIC_DEVICE_BASE, \
36 AML_GIC_DEVICE_SIZE, \
37 MT_DEVICE | MT_RW | MT_SECURE)
38
39 #define MAP_SEC_DEVICE1 MAP_REGION_FLAT(AML_SEC_DEVICE1_BASE, \
40 AML_SEC_DEVICE1_SIZE, \
41 MT_DEVICE | MT_RW | MT_SECURE)
42
43 #define MAP_SEC_DEVICE2 MAP_REGION_FLAT(AML_SEC_DEVICE2_BASE, \
44 AML_SEC_DEVICE2_SIZE, \
45 MT_DEVICE | MT_RW | MT_SECURE)
46
47 #define MAP_TZRAM MAP_REGION_FLAT(AML_TZRAM_BASE, \
48 AML_TZRAM_SIZE, \
49 MT_DEVICE | MT_RW | MT_SECURE)
50
51 static const mmap_region_t axg_mmap[] = {
52 MAP_NSDRAM0,
53 MAP_NS_SHARE_MEM,
54 MAP_SEC_SHARE_MEM,
55 MAP_SEC_DEVICE0,
56 MAP_GIC_DEVICE,
57 MAP_SEC_DEVICE1,
58 MAP_SEC_DEVICE2,
59 MAP_TZRAM,
60 {0}
61 };
62
63 /*******************************************************************************
64 * Per-image regions
65 ******************************************************************************/
66 #define MAP_BL31 MAP_REGION_FLAT(BL31_BASE, \
67 BL31_END - BL31_BASE, \
68 MT_MEMORY | MT_RW | MT_SECURE)
69
70 #define MAP_BL_CODE MAP_REGION_FLAT(BL_CODE_BASE, \
71 BL_CODE_END - BL_CODE_BASE, \
72 MT_CODE | MT_SECURE)
73
74 #define MAP_BL_RO_DATA MAP_REGION_FLAT(BL_RO_DATA_BASE, \
75 BL_RO_DATA_END - BL_RO_DATA_BASE, \
76 MT_RO_DATA | MT_SECURE)
77
78 #define MAP_BL_COHERENT MAP_REGION_FLAT(BL_COHERENT_RAM_BASE, \
79 BL_COHERENT_RAM_END - BL_COHERENT_RAM_BASE, \
80 MT_DEVICE | MT_RW | MT_SECURE)
81
82 /*******************************************************************************
83 * Function that sets up the translation tables.
84 ******************************************************************************/
aml_setup_page_tables(void)85 void aml_setup_page_tables(void)
86 {
87 #if IMAGE_BL31
88 const mmap_region_t axg_bl_mmap[] = {
89 MAP_BL31,
90 MAP_BL_CODE,
91 MAP_BL_RO_DATA,
92 #if USE_COHERENT_MEM
93 MAP_BL_COHERENT,
94 #endif
95 {0}
96 };
97 #endif
98
99 mmap_add(axg_bl_mmap);
100
101 mmap_add(axg_mmap);
102
103 init_xlat_tables();
104 }
105
106 /*******************************************************************************
107 * Function that returns the system counter frequency
108 ******************************************************************************/
plat_get_syscnt_freq2(void)109 unsigned int plat_get_syscnt_freq2(void)
110 {
111 mmio_clrbits_32(AML_SYS_CPU_CFG7, PLAT_SYS_CPU_CFG7);
112 mmio_clrbits_32(AML_AO_TIMESTAMP_CNTL, PLAT_AO_TIMESTAMP_CNTL);
113
114 return AML_OSC24M_CLK_IN_HZ;
115 }
116