1 /* 2 * Copyright (c) 2017-2020, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef XLAT_TABLES_DEFS_H 8 #define XLAT_TABLES_DEFS_H 9 10 #include <arch.h> 11 #include <lib/utils_def.h> 12 #include <lib/xlat_tables/xlat_mmu_helpers.h> 13 14 /* Miscellaneous MMU related constants */ 15 #define NUM_2MB_IN_GB (U(1) << 9) 16 #define NUM_4K_IN_2MB (U(1) << 9) 17 #define NUM_GB_IN_4GB (U(1) << 2) 18 19 #define TWO_MB_SHIFT U(21) 20 #define ONE_GB_SHIFT U(30) 21 #define FOUR_KB_SHIFT U(12) 22 23 #define ONE_GB_INDEX(x) ((x) >> ONE_GB_SHIFT) 24 #define TWO_MB_INDEX(x) ((x) >> TWO_MB_SHIFT) 25 #define FOUR_KB_INDEX(x) ((x) >> FOUR_KB_SHIFT) 26 27 #define PAGE_SIZE_4KB U(4096) 28 #define PAGE_SIZE_16KB U(16384) 29 #define PAGE_SIZE_64KB U(65536) 30 31 #define INVALID_DESC U(0x0) 32 /* 33 * A block descriptor points to a region of memory bigger than the granule size 34 * (e.g. a 2MB region when the granule size is 4KB). 35 */ 36 #define BLOCK_DESC U(0x1) /* Table levels 0-2 */ 37 /* A table descriptor points to the next level of translation table. */ 38 #define TABLE_DESC U(0x3) /* Table levels 0-2 */ 39 /* 40 * A page descriptor points to a page, i.e. a memory region whose size is the 41 * translation granule size (e.g. 4KB). 42 */ 43 #define PAGE_DESC U(0x3) /* Table level 3 */ 44 45 #define DESC_MASK U(0x3) 46 47 #define FIRST_LEVEL_DESC_N ONE_GB_SHIFT 48 #define SECOND_LEVEL_DESC_N TWO_MB_SHIFT 49 #define THIRD_LEVEL_DESC_N FOUR_KB_SHIFT 50 51 /* XN: Translation regimes that support one VA range (EL2 and EL3). */ 52 #define XN (ULL(1) << 2) 53 /* UXN, PXN: Translation regimes that support two VA ranges (EL1&0). */ 54 #define UXN (ULL(1) << 2) 55 #define PXN (ULL(1) << 1) 56 #define CONT_HINT (ULL(1) << 0) 57 #define UPPER_ATTRS(x) (((x) & ULL(0x7)) << 52) 58 59 #define NON_GLOBAL (U(1) << 9) 60 #define ACCESS_FLAG (U(1) << 8) 61 #define NSH (U(0x0) << 6) 62 #define OSH (U(0x2) << 6) 63 #define ISH (U(0x3) << 6) 64 65 #ifdef __aarch64__ 66 /* Guarded Page bit */ 67 #define GP (ULL(1) << 50) 68 #endif 69 70 #define TABLE_ADDR_MASK ULL(0x0000FFFFFFFFF000) 71 72 /* 73 * The ARMv8-A architecture allows translation granule sizes of 4KB, 16KB or 74 * 64KB. However, only 4KB are supported at the moment. 75 */ 76 #define PAGE_SIZE_SHIFT FOUR_KB_SHIFT 77 #define PAGE_SIZE (UL(1) << PAGE_SIZE_SHIFT) 78 #define PAGE_SIZE_MASK (PAGE_SIZE - UL(1)) 79 #define IS_PAGE_ALIGNED(addr) (((addr) & PAGE_SIZE_MASK) == U(0)) 80 81 #if (ARM_ARCH_MAJOR == 7) && !ARMV7_SUPPORTS_LARGE_PAGE_ADDRESSING 82 #define XLAT_ENTRY_SIZE_SHIFT U(2) /* Each MMU table entry is 4 bytes */ 83 #else 84 #define XLAT_ENTRY_SIZE_SHIFT U(3) /* Each MMU table entry is 8 bytes */ 85 #endif 86 #define XLAT_ENTRY_SIZE (U(1) << XLAT_ENTRY_SIZE_SHIFT) 87 88 #define XLAT_TABLE_SIZE_SHIFT PAGE_SIZE_SHIFT /* Size of one complete table */ 89 #define XLAT_TABLE_SIZE (U(1) << XLAT_TABLE_SIZE_SHIFT) 90 91 #define XLAT_TABLE_LEVEL_MAX U(3) 92 93 /* Values for number of entries in each MMU translation table */ 94 #define XLAT_TABLE_ENTRIES_SHIFT (XLAT_TABLE_SIZE_SHIFT - XLAT_ENTRY_SIZE_SHIFT) 95 #define XLAT_TABLE_ENTRIES (U(1) << XLAT_TABLE_ENTRIES_SHIFT) 96 #define XLAT_TABLE_ENTRIES_MASK (XLAT_TABLE_ENTRIES - U(1)) 97 98 /* Values to convert a memory address to an index into a translation table */ 99 #define L3_XLAT_ADDRESS_SHIFT PAGE_SIZE_SHIFT 100 #define L2_XLAT_ADDRESS_SHIFT (L3_XLAT_ADDRESS_SHIFT + XLAT_TABLE_ENTRIES_SHIFT) 101 #define L1_XLAT_ADDRESS_SHIFT (L2_XLAT_ADDRESS_SHIFT + XLAT_TABLE_ENTRIES_SHIFT) 102 #define L0_XLAT_ADDRESS_SHIFT (L1_XLAT_ADDRESS_SHIFT + XLAT_TABLE_ENTRIES_SHIFT) 103 #define XLAT_ADDR_SHIFT(level) (PAGE_SIZE_SHIFT + \ 104 ((XLAT_TABLE_LEVEL_MAX - (level)) * XLAT_TABLE_ENTRIES_SHIFT)) 105 106 #define XLAT_BLOCK_SIZE(level) (UL(1) << XLAT_ADDR_SHIFT(level)) 107 /* Mask to get the bits used to index inside a block of a certain level */ 108 #define XLAT_BLOCK_MASK(level) (XLAT_BLOCK_SIZE(level) - UL(1)) 109 /* Mask to get the address bits common to a block of a certain table level*/ 110 #define XLAT_ADDR_MASK(level) (~XLAT_BLOCK_MASK(level)) 111 /* 112 * Extract from the given virtual address the index into the given lookup level. 113 * This macro assumes the system is using the 4KB translation granule. 114 */ 115 #define XLAT_TABLE_IDX(virtual_addr, level) \ 116 (((virtual_addr) >> XLAT_ADDR_SHIFT(level)) & ULL(0x1FF)) 117 118 /* 119 * The ARMv8 translation table descriptor format defines AP[2:1] as the Access 120 * Permissions bits, and does not define an AP[0] bit. 121 * 122 * AP[1] is valid only for a stage 1 translation that supports two VA ranges 123 * (i.e. in the ARMv8A.0 architecture, that is the S-EL1&0 regime). It is RES1 124 * when stage 1 translations can only support one VA range. 125 */ 126 #define AP2_SHIFT U(0x7) 127 #define AP2_RO ULL(0x1) 128 #define AP2_RW ULL(0x0) 129 130 #define AP1_SHIFT U(0x6) 131 #define AP1_ACCESS_UNPRIVILEGED ULL(0x1) 132 #define AP1_NO_ACCESS_UNPRIVILEGED ULL(0x0) 133 #define AP1_RES1 ULL(0x1) 134 135 /* 136 * The following definitions must all be passed to the LOWER_ATTRS() macro to 137 * get the right bitmask. 138 */ 139 #define AP_RO (AP2_RO << 5) 140 #define AP_RW (AP2_RW << 5) 141 #define AP_ACCESS_UNPRIVILEGED (AP1_ACCESS_UNPRIVILEGED << 4) 142 #define AP_NO_ACCESS_UNPRIVILEGED (AP1_NO_ACCESS_UNPRIVILEGED << 4) 143 #define AP_ONE_VA_RANGE_RES1 (AP1_RES1 << 4) 144 #define NS (U(0x1) << 3) 145 #define ATTR_NON_CACHEABLE_INDEX ULL(0x2) 146 #define ATTR_DEVICE_INDEX ULL(0x1) 147 #define ATTR_IWBWA_OWBWA_NTR_INDEX ULL(0x0) 148 #define LOWER_ATTRS(x) (((x) & U(0xfff)) << 2) 149 150 /* Normal Memory, Outer Write-Through non-transient, Inner Non-cacheable */ 151 #define ATTR_NON_CACHEABLE MAKE_MAIR_NORMAL_MEMORY(MAIR_NORM_NC, MAIR_NORM_NC) 152 /* Device-nGnRE */ 153 #define ATTR_DEVICE MAIR_DEV_nGnRE 154 /* Normal Memory, Outer Write-Back non-transient, Inner Write-Back non-transient */ 155 #define ATTR_IWBWA_OWBWA_NTR MAKE_MAIR_NORMAL_MEMORY(MAIR_NORM_WB_NTR_RWA, MAIR_NORM_WB_NTR_RWA) 156 #define MAIR_ATTR_SET(attr, index) ((attr) << ((index) << 3)) 157 #define ATTR_INDEX_MASK U(0x3) 158 #define ATTR_INDEX_GET(attr) (((attr) >> 2) & ATTR_INDEX_MASK) 159 160 /* 161 * Shift values for the attributes fields in a block or page descriptor. 162 * See section D4.3.3 in the ARMv8-A ARM (issue B.a). 163 */ 164 165 /* Memory attributes index field, AttrIndx[2:0]. */ 166 #define ATTR_INDEX_SHIFT 2 167 /* Non-secure bit, NS. */ 168 #define NS_SHIFT 5 169 /* Shareability field, SH[1:0] */ 170 #define SHAREABILITY_SHIFT 8 171 /* The Access Flag, AF. */ 172 #define ACCESS_FLAG_SHIFT 10 173 /* The not global bit, nG. */ 174 #define NOT_GLOBAL_SHIFT 11 175 /* Contiguous hint bit. */ 176 #define CONT_HINT_SHIFT 52 177 /* Execute-never bits, XN. */ 178 #define PXN_SHIFT 53 179 #define XN_SHIFT 54 180 #define UXN_SHIFT XN_SHIFT 181 182 #endif /* XLAT_TABLES_DEFS_H */ 183