1 /*
2 * Copyright (c) 2015-2020, Renesas Electronics Corporation. All rights reserved.
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7 #include <assert.h>
8 #include <string.h>
9
10 #include <arch.h>
11 #include <arch_helpers.h>
12 #include <common/debug.h>
13 #include <lib/bakery_lock.h>
14 #include <lib/mmio.h>
15 #include <lib/xlat_tables/xlat_tables_v2.h>
16 #include <plat/common/platform.h>
17
18 #include "iic_dvfs.h"
19 #include "micro_delay.h"
20 #include "pwrc.h"
21 #include "rcar_def.h"
22 #include "rcar_private.h"
23
24 /*
25 * Someday there will be a generic power controller api. At the moment each
26 * platform has its own pwrc so just exporting functions should be acceptable.
27 */
28 RCAR_INSTANTIATE_LOCK
29
30 #define WUP_IRQ_SHIFT (0U)
31 #define WUP_FIQ_SHIFT (8U)
32 #define WUP_CSD_SHIFT (16U)
33 #define BIT_SOFTRESET (1U << 15)
34 #define BIT_CA53_SCU (1U << 21)
35 #define BIT_CA57_SCU (1U << 12)
36 #define REQ_RESUME (1U << 1)
37 #define REQ_OFF (1U << 0)
38 #define STATUS_PWRUP (1U << 4)
39 #define STATUS_PWRDOWN (1U << 0)
40 #define STATE_CA57_CPU (27U)
41 #define STATE_CA53_CPU (22U)
42 #define MODE_L2_DOWN (0x00000002U)
43 #define CPU_PWR_OFF (0x00000003U)
44 #define RCAR_PSTR_MASK (0x00000003U)
45 #define ST_ALL_STANDBY (0x00003333U)
46 /* Suspend to ram */
47 #define DBSC4_REG_BASE (0xE6790000U)
48 #define DBSC4_REG_DBSYSCNT0 (DBSC4_REG_BASE + 0x0100U)
49 #define DBSC4_REG_DBACEN (DBSC4_REG_BASE + 0x0200U)
50 #define DBSC4_REG_DBCMD (DBSC4_REG_BASE + 0x0208U)
51 #define DBSC4_REG_DBRFEN (DBSC4_REG_BASE + 0x0204U)
52 #define DBSC4_REG_DBWAIT (DBSC4_REG_BASE + 0x0210U)
53 #define DBSC4_REG_DBCALCNF (DBSC4_REG_BASE + 0x0424U)
54 #define DBSC4_REG_DBDFIPMSTRCNF (DBSC4_REG_BASE + 0x0520U)
55 #define DBSC4_REG_DBPDLK0 (DBSC4_REG_BASE + 0x0620U)
56 #define DBSC4_REG_DBPDRGA0 (DBSC4_REG_BASE + 0x0624U)
57 #define DBSC4_REG_DBPDRGD0 (DBSC4_REG_BASE + 0x0628U)
58 #define DBSC4_REG_DBCAM0CTRL0 (DBSC4_REG_BASE + 0x0940U)
59 #define DBSC4_REG_DBCAM0STAT0 (DBSC4_REG_BASE + 0x0980U)
60 #define DBSC4_REG_DBCAM1STAT0 (DBSC4_REG_BASE + 0x0990U)
61 #define DBSC4_REG_DBCAM2STAT0 (DBSC4_REG_BASE + 0x09A0U)
62 #define DBSC4_REG_DBCAM3STAT0 (DBSC4_REG_BASE + 0x09B0U)
63 #define DBSC4_BIT_DBACEN_ACCEN ((uint32_t)(1U << 0))
64 #define DBSC4_BIT_DBRFEN_ARFEN ((uint32_t)(1U << 0))
65 #define DBSC4_BIT_DBCAMxSTAT0 (0x00000001U)
66 #define DBSC4_BIT_DBDFIPMSTRCNF_PMSTREN (0x00000001U)
67 #define DBSC4_SET_DBCMD_OPC_PRE (0x04000000U)
68 #define DBSC4_SET_DBCMD_OPC_SR (0x0A000000U)
69 #define DBSC4_SET_DBCMD_OPC_PD (0x08000000U)
70 #define DBSC4_SET_DBCMD_OPC_MRW (0x0E000000U)
71 #define DBSC4_SET_DBCMD_CH_ALL (0x00800000U)
72 #define DBSC4_SET_DBCMD_RANK_ALL (0x00040000U)
73 #define DBSC4_SET_DBCMD_ARG_ALL (0x00000010U)
74 #define DBSC4_SET_DBCMD_ARG_ENTER (0x00000000U)
75 #define DBSC4_SET_DBCMD_ARG_MRW_ODTC (0x00000B00U)
76 #define DBSC4_SET_DBSYSCNT0_WRITE_ENABLE (0x00001234U)
77 #define DBSC4_SET_DBSYSCNT0_WRITE_DISABLE (0x00000000U)
78 #define DBSC4_SET_DBPDLK0_PHY_ACCESS (0x0000A55AU)
79 #define DBSC4_SET_DBPDRGA0_ACIOCR0 (0x0000001AU)
80 #define DBSC4_SET_DBPDRGD0_ACIOCR0 (0x33C03C11U)
81 #define DBSC4_SET_DBPDRGA0_DXCCR (0x00000020U)
82 #define DBSC4_SET_DBPDRGD0_DXCCR (0x00181006U)
83 #define DBSC4_SET_DBPDRGA0_PGCR1 (0x00000003U)
84 #define DBSC4_SET_DBPDRGD0_PGCR1 (0x0380C600U)
85 #define DBSC4_SET_DBPDRGA0_ACIOCR1 (0x0000001BU)
86 #define DBSC4_SET_DBPDRGD0_ACIOCR1 (0xAAAAAAAAU)
87 #define DBSC4_SET_DBPDRGA0_ACIOCR3 (0x0000001DU)
88 #define DBSC4_SET_DBPDRGD0_ACIOCR3 (0xAAAAAAAAU)
89 #define DBSC4_SET_DBPDRGA0_ACIOCR5 (0x0000001FU)
90 #define DBSC4_SET_DBPDRGD0_ACIOCR5 (0x000000AAU)
91 #define DBSC4_SET_DBPDRGA0_DX0GCR2 (0x000000A2U)
92 #define DBSC4_SET_DBPDRGD0_DX0GCR2 (0xAAAA0000U)
93 #define DBSC4_SET_DBPDRGA0_DX1GCR2 (0x000000C2U)
94 #define DBSC4_SET_DBPDRGD0_DX1GCR2 (0xAAAA0000U)
95 #define DBSC4_SET_DBPDRGA0_DX2GCR2 (0x000000E2U)
96 #define DBSC4_SET_DBPDRGD0_DX2GCR2 (0xAAAA0000U)
97 #define DBSC4_SET_DBPDRGA0_DX3GCR2 (0x00000102U)
98 #define DBSC4_SET_DBPDRGD0_DX3GCR2 (0xAAAA0000U)
99 #define DBSC4_SET_DBPDRGA0_ZQCR (0x00000090U)
100 #define DBSC4_SET_DBPDRGD0_ZQCR_MD19_0 (0x04058904U)
101 #define DBSC4_SET_DBPDRGD0_ZQCR_MD19_1 (0x04058A04U)
102 #define DBSC4_SET_DBPDRGA0_DX0GCR0 (0x000000A0U)
103 #define DBSC4_SET_DBPDRGD0_DX0GCR0 (0x7C0002E5U)
104 #define DBSC4_SET_DBPDRGA0_DX1GCR0 (0x000000C0U)
105 #define DBSC4_SET_DBPDRGD0_DX1GCR0 (0x7C0002E5U)
106 #define DBSC4_SET_DBPDRGA0_DX2GCR0 (0x000000E0U)
107 #define DBSC4_SET_DBPDRGD0_DX2GCR0 (0x7C0002E5U)
108 #define DBSC4_SET_DBPDRGA0_DX3GCR0 (0x00000100U)
109 #define DBSC4_SET_DBPDRGD0_DX3GCR0 (0x7C0002E5U)
110 #define DBSC4_SET_DBPDRGA0_DX0GCR1 (0x000000A1U)
111 #define DBSC4_SET_DBPDRGD0_DX0GCR1 (0x55550000U)
112 #define DBSC4_SET_DBPDRGA0_DX1GCR1 (0x000000C1U)
113 #define DBSC4_SET_DBPDRGD0_DX1GCR1 (0x55550000U)
114 #define DBSC4_SET_DBPDRGA0_DX2GCR1 (0x000000E1U)
115 #define DBSC4_SET_DBPDRGD0_DX2GCR1 (0x55550000U)
116 #define DBSC4_SET_DBPDRGA0_DX3GCR1 (0x00000101U)
117 #define DBSC4_SET_DBPDRGD0_DX3GCR1 (0x55550000U)
118 #define DBSC4_SET_DBPDRGA0_DX0GCR3 (0x000000A3U)
119 #define DBSC4_SET_DBPDRGD0_DX0GCR3 (0x00008484U)
120 #define DBSC4_SET_DBPDRGA0_DX1GCR3 (0x000000C3U)
121 #define DBSC4_SET_DBPDRGD0_DX1GCR3 (0x00008484U)
122 #define DBSC4_SET_DBPDRGA0_DX2GCR3 (0x000000E3U)
123 #define DBSC4_SET_DBPDRGD0_DX2GCR3 (0x00008484U)
124 #define DBSC4_SET_DBPDRGA0_DX3GCR3 (0x00000103U)
125 #define DBSC4_SET_DBPDRGD0_DX3GCR3 (0x00008484U)
126 #define RST_BASE (0xE6160000U)
127 #define RST_MODEMR (RST_BASE + 0x0060U)
128 #define RST_MODEMR_BIT0 (0x00000001U)
129
130 #define RCAR_CNTCR_OFF (0x00U)
131 #define RCAR_CNTCVL_OFF (0x08U)
132 #define RCAR_CNTCVU_OFF (0x0CU)
133 #define RCAR_CNTFID_OFF (0x20U)
134
135 #define RCAR_CNTCR_EN ((uint32_t)1U << 0U)
136 #define RCAR_CNTCR_FCREQ(x) ((uint32_t)(x) << 8U)
137
138 #if PMIC_ROHM_BD9571
139 #define BIT_BKUP_CTRL_OUT ((uint8_t)(1U << 4))
140 #define PMIC_BKUP_MODE_CNT (0x20U)
141 #define PMIC_QLLM_CNT (0x27U)
142 #define PMIC_RETRY_MAX (100U)
143 #endif /* PMIC_ROHM_BD9571 */
144 #define SCTLR_EL3_M_BIT ((uint32_t)1U << 0)
145 #define RCAR_CA53CPU_NUM_MAX (4U)
146 #define RCAR_CA57CPU_NUM_MAX (4U)
147 #define IS_A53A57(c) ((c) == RCAR_CLUSTER_A53A57)
148 #define IS_CA57(c) ((c) == RCAR_CLUSTER_CA57)
149 #define IS_CA53(c) ((c) == RCAR_CLUSTER_CA53)
150
151 #ifndef __ASSEMBLER__
152 IMPORT_SYM(unsigned long, __system_ram_start__, SYSTEM_RAM_START);
153 IMPORT_SYM(unsigned long, __system_ram_end__, SYSTEM_RAM_END);
154 IMPORT_SYM(unsigned long, __SRAM_COPY_START__, SRAM_COPY_START);
155 #endif
156
rcar_pwrc_status(uint64_t mpidr)157 uint32_t rcar_pwrc_status(uint64_t mpidr)
158 {
159 uint32_t ret = 0;
160 uint64_t cm, cpu;
161 uint32_t reg;
162 uint32_t c;
163
164 rcar_lock_get();
165
166 c = rcar_pwrc_get_cluster();
167 cm = mpidr & MPIDR_CLUSTER_MASK;
168
169 if (!IS_A53A57(c) && cm != 0) {
170 ret = RCAR_INVALID;
171 goto done;
172 }
173
174 reg = mmio_read_32(RCAR_PRR);
175 cpu = mpidr & MPIDR_CPU_MASK;
176
177 if (IS_CA53(c))
178 if (reg & (1 << (STATE_CA53_CPU + cpu)))
179 ret = RCAR_INVALID;
180 if (IS_CA57(c))
181 if (reg & (1 << (STATE_CA57_CPU + cpu)))
182 ret = RCAR_INVALID;
183 done:
184 rcar_lock_release();
185
186 return ret;
187 }
188
scu_power_up(uint64_t mpidr)189 static void scu_power_up(uint64_t mpidr)
190 {
191 uintptr_t reg_pwrsr, reg_cpumcr, reg_pwron, reg_pwrer;
192 uint32_t c, sysc_reg_bit;
193
194 c = rcar_pwrc_get_mpidr_cluster(mpidr);
195 reg_cpumcr = IS_CA57(c) ? RCAR_CA57CPUCMCR : RCAR_CA53CPUCMCR;
196 sysc_reg_bit = IS_CA57(c) ? BIT_CA57_SCU : BIT_CA53_SCU;
197 reg_pwron = IS_CA57(c) ? RCAR_PWRONCR5 : RCAR_PWRONCR3;
198 reg_pwrer = IS_CA57(c) ? RCAR_PWRER5 : RCAR_PWRER3;
199 reg_pwrsr = IS_CA57(c) ? RCAR_PWRSR5 : RCAR_PWRSR3;
200
201 if ((mmio_read_32(reg_pwrsr) & STATUS_PWRDOWN) == 0)
202 return;
203
204 if (mmio_read_32(reg_cpumcr) != 0)
205 mmio_write_32(reg_cpumcr, 0);
206
207 mmio_setbits_32(RCAR_SYSCIER, sysc_reg_bit);
208 mmio_setbits_32(RCAR_SYSCIMR, sysc_reg_bit);
209
210 do {
211 while ((mmio_read_32(RCAR_SYSCSR) & REQ_RESUME) == 0)
212 ;
213 mmio_write_32(reg_pwron, 1);
214 } while (mmio_read_32(reg_pwrer) & 1);
215
216 while ((mmio_read_32(RCAR_SYSCISR) & sysc_reg_bit) == 0)
217 ;
218 mmio_write_32(RCAR_SYSCISR, sysc_reg_bit);
219 while ((mmio_read_32(reg_pwrsr) & STATUS_PWRUP) == 0)
220 ;
221 }
222
rcar_pwrc_cpuon(uint64_t mpidr)223 void rcar_pwrc_cpuon(uint64_t mpidr)
224 {
225 uint32_t res_data, on_data;
226 uintptr_t res_reg, on_reg;
227 uint32_t limit, c;
228 uint64_t cpu;
229
230 rcar_lock_get();
231
232 c = rcar_pwrc_get_mpidr_cluster(mpidr);
233 res_reg = IS_CA53(c) ? RCAR_CA53RESCNT : RCAR_CA57RESCNT;
234 on_reg = IS_CA53(c) ? RCAR_CA53WUPCR : RCAR_CA57WUPCR;
235 limit = IS_CA53(c) ? 0x5A5A0000 : 0xA5A50000;
236
237 res_data = mmio_read_32(res_reg) | limit;
238 scu_power_up(mpidr);
239 cpu = mpidr & MPIDR_CPU_MASK;
240 on_data = 1 << cpu;
241 mmio_write_32(RCAR_CPGWPR, ~on_data);
242 mmio_write_32(on_reg, on_data);
243 mmio_write_32(res_reg, res_data & (~(1 << (3 - cpu))));
244
245 rcar_lock_release();
246 }
247
rcar_pwrc_cpuoff(uint64_t mpidr)248 void rcar_pwrc_cpuoff(uint64_t mpidr)
249 {
250 uint32_t c;
251 uintptr_t reg;
252 uint64_t cpu;
253
254 rcar_lock_get();
255
256 cpu = mpidr & MPIDR_CPU_MASK;
257 c = rcar_pwrc_get_mpidr_cluster(mpidr);
258 reg = IS_CA53(c) ? RCAR_CA53CPU0CR : RCAR_CA57CPU0CR;
259
260 if (read_mpidr_el1() != mpidr)
261 panic();
262
263 mmio_write_32(RCAR_CPGWPR, ~CPU_PWR_OFF);
264 mmio_write_32(reg + cpu * 0x0010, CPU_PWR_OFF);
265
266 rcar_lock_release();
267 }
268
rcar_pwrc_enable_interrupt_wakeup(uint64_t mpidr)269 void rcar_pwrc_enable_interrupt_wakeup(uint64_t mpidr)
270 {
271 uint32_t c, shift_irq, shift_fiq;
272 uintptr_t reg;
273 uint64_t cpu;
274
275 rcar_lock_get();
276
277 cpu = mpidr & MPIDR_CPU_MASK;
278 c = rcar_pwrc_get_mpidr_cluster(mpidr);
279 reg = IS_CA53(c) ? RCAR_WUPMSKCA53 : RCAR_WUPMSKCA57;
280
281 shift_irq = WUP_IRQ_SHIFT + cpu;
282 shift_fiq = WUP_FIQ_SHIFT + cpu;
283
284 mmio_write_32(reg, ~((uint32_t) 1 << shift_irq) &
285 ~((uint32_t) 1 << shift_fiq));
286 rcar_lock_release();
287 }
288
rcar_pwrc_disable_interrupt_wakeup(uint64_t mpidr)289 void rcar_pwrc_disable_interrupt_wakeup(uint64_t mpidr)
290 {
291 uint32_t c, shift_irq, shift_fiq;
292 uintptr_t reg;
293 uint64_t cpu;
294
295 rcar_lock_get();
296
297 cpu = mpidr & MPIDR_CPU_MASK;
298 c = rcar_pwrc_get_mpidr_cluster(mpidr);
299 reg = IS_CA53(c) ? RCAR_WUPMSKCA53 : RCAR_WUPMSKCA57;
300
301 shift_irq = WUP_IRQ_SHIFT + cpu;
302 shift_fiq = WUP_FIQ_SHIFT + cpu;
303
304 mmio_write_32(reg, ((uint32_t) 1 << shift_irq) |
305 ((uint32_t) 1 << shift_fiq));
306 rcar_lock_release();
307 }
308
rcar_pwrc_clusteroff(uint64_t mpidr)309 void rcar_pwrc_clusteroff(uint64_t mpidr)
310 {
311 uint32_t c, product, cut, reg;
312 uintptr_t dst;
313
314 rcar_lock_get();
315
316 reg = mmio_read_32(RCAR_PRR);
317 product = reg & PRR_PRODUCT_MASK;
318 cut = reg & PRR_CUT_MASK;
319
320 c = rcar_pwrc_get_mpidr_cluster(mpidr);
321 dst = IS_CA53(c) ? RCAR_CA53CPUCMCR : RCAR_CA57CPUCMCR;
322
323 if (product == PRR_PRODUCT_M3 && cut < PRR_PRODUCT_30) {
324 goto done;
325 }
326
327 if (product == PRR_PRODUCT_H3 && cut <= PRR_PRODUCT_20) {
328 goto done;
329 }
330
331 /* all of the CPUs in the cluster is in the CoreStandby mode */
332 mmio_write_32(dst, MODE_L2_DOWN);
333 done:
334 rcar_lock_release();
335 }
336
337 static uint64_t rcar_pwrc_saved_cntpct_el0;
338 static uint32_t rcar_pwrc_saved_cntfid;
339
340 #if RCAR_SYSTEM_SUSPEND
rcar_pwrc_save_timer_state(void)341 static void rcar_pwrc_save_timer_state(void)
342 {
343 rcar_pwrc_saved_cntpct_el0 = read_cntpct_el0();
344
345 rcar_pwrc_saved_cntfid =
346 mmio_read_32((uintptr_t)(RCAR_CNTC_BASE + RCAR_CNTFID_OFF));
347 }
348 #endif /* RCAR_SYSTEM_SUSPEND */
349
rcar_pwrc_restore_timer_state(void)350 void rcar_pwrc_restore_timer_state(void)
351 {
352 /* Stop timer before restoring counter value */
353 mmio_write_32((uintptr_t)(RCAR_CNTC_BASE + RCAR_CNTCR_OFF), 0U);
354
355 mmio_write_32((uintptr_t)(RCAR_CNTC_BASE + RCAR_CNTCVL_OFF),
356 (uint32_t)(rcar_pwrc_saved_cntpct_el0 & 0xFFFFFFFFU));
357 mmio_write_32((uintptr_t)(RCAR_CNTC_BASE + RCAR_CNTCVU_OFF),
358 (uint32_t)(rcar_pwrc_saved_cntpct_el0 >> 32U));
359
360 mmio_write_32((uintptr_t)(RCAR_CNTC_BASE + RCAR_CNTFID_OFF),
361 rcar_pwrc_saved_cntfid);
362
363 /* Start generic timer back */
364 write_cntfrq_el0((u_register_t)plat_get_syscnt_freq2());
365
366 mmio_write_32((uintptr_t)(RCAR_CNTC_BASE + RCAR_CNTCR_OFF),
367 (RCAR_CNTCR_FCREQ(0U) | RCAR_CNTCR_EN));
368 }
369
370 #if !PMIC_ROHM_BD9571
rcar_pwrc_system_reset(void)371 void rcar_pwrc_system_reset(void)
372 {
373 mmio_write_32(RCAR_SRESCR, 0x5AA50000U | BIT_SOFTRESET);
374 }
375 #endif /* PMIC_ROHM_BD9571 */
376
377 #define RST_CA53_CPU0_BARH (0xE6160080U)
378 #define RST_CA53_CPU0_BARL (0xE6160084U)
379 #define RST_CA57_CPU0_BARH (0xE61600C0U)
380 #define RST_CA57_CPU0_BARL (0xE61600C4U)
381
rcar_pwrc_setup(void)382 void rcar_pwrc_setup(void)
383 {
384 uintptr_t rst_barh;
385 uintptr_t rst_barl;
386 uint32_t i, j;
387 uint64_t reset = (uint64_t) (&plat_secondary_reset) & 0xFFFFFFFF;
388
389 const uint32_t cluster[PLATFORM_CLUSTER_COUNT] = {
390 RCAR_CLUSTER_CA53,
391 RCAR_CLUSTER_CA57
392 };
393 const uintptr_t reg_barh[PLATFORM_CLUSTER_COUNT] = {
394 RST_CA53_CPU0_BARH,
395 RST_CA57_CPU0_BARH
396 };
397 const uintptr_t reg_barl[PLATFORM_CLUSTER_COUNT] = {
398 RST_CA53_CPU0_BARL,
399 RST_CA57_CPU0_BARL
400 };
401
402 for (i = 0; i < PLATFORM_CLUSTER_COUNT; i++) {
403 rst_barh = reg_barh[i];
404 rst_barl = reg_barl[i];
405 for (j = 0; j < rcar_pwrc_get_cpu_num(cluster[i]); j++) {
406 mmio_write_32(rst_barh, 0);
407 mmio_write_32(rst_barl, (uint32_t) reset);
408 rst_barh += 0x10;
409 rst_barl += 0x10;
410 }
411 }
412
413 rcar_lock_init();
414 }
415
416 #if RCAR_SYSTEM_SUSPEND
417 #define DBCAM_FLUSH(__bit) \
418 do { \
419 ; \
420 } while (!(mmio_read_32(DBSC4_REG_DBCAM##__bit##STAT0) & DBSC4_BIT_DBCAMxSTAT0))
421
422
423 static void __attribute__ ((section(".system_ram")))
rcar_pwrc_set_self_refresh(void)424 rcar_pwrc_set_self_refresh(void)
425 {
426 uint32_t reg = mmio_read_32(RCAR_PRR);
427 uint32_t cut, product;
428
429 product = reg & PRR_PRODUCT_MASK;
430 cut = reg & PRR_CUT_MASK;
431
432 if (product == PRR_PRODUCT_M3 && cut < PRR_PRODUCT_30) {
433 goto self_refresh;
434 }
435
436 if (product == PRR_PRODUCT_H3 && cut < PRR_PRODUCT_20) {
437 goto self_refresh;
438 }
439
440 mmio_write_32(DBSC4_REG_DBSYSCNT0, DBSC4_SET_DBSYSCNT0_WRITE_ENABLE);
441
442 self_refresh:
443
444 /* DFI_PHYMSTR_ACK setting */
445 mmio_write_32(DBSC4_REG_DBDFIPMSTRCNF,
446 mmio_read_32(DBSC4_REG_DBDFIPMSTRCNF) &
447 (~DBSC4_BIT_DBDFIPMSTRCNF_PMSTREN));
448
449 /* Set the Self-Refresh mode */
450 mmio_write_32(DBSC4_REG_DBACEN, 0);
451
452 if (product == PRR_PRODUCT_H3 && cut < PRR_PRODUCT_20)
453 rcar_micro_delay(100);
454 else if (product == PRR_PRODUCT_H3) {
455 mmio_write_32(DBSC4_REG_DBCAM0CTRL0, 1);
456 DBCAM_FLUSH(0);
457 DBCAM_FLUSH(1);
458 DBCAM_FLUSH(2);
459 DBCAM_FLUSH(3);
460 mmio_write_32(DBSC4_REG_DBCAM0CTRL0, 0);
461 } else if (product == PRR_PRODUCT_M3) {
462 mmio_write_32(DBSC4_REG_DBCAM0CTRL0, 1);
463 DBCAM_FLUSH(0);
464 DBCAM_FLUSH(1);
465 mmio_write_32(DBSC4_REG_DBCAM0CTRL0, 0);
466 } else {
467 mmio_write_32(DBSC4_REG_DBCAM0CTRL0, 1);
468 DBCAM_FLUSH(0);
469 mmio_write_32(DBSC4_REG_DBCAM0CTRL0, 0);
470 }
471
472 /* Set the SDRAM calibration configuration register */
473 mmio_write_32(DBSC4_REG_DBCALCNF, 0);
474
475 reg = DBSC4_SET_DBCMD_OPC_PRE | DBSC4_SET_DBCMD_CH_ALL |
476 DBSC4_SET_DBCMD_RANK_ALL | DBSC4_SET_DBCMD_ARG_ALL;
477 mmio_write_32(DBSC4_REG_DBCMD, reg);
478 while (mmio_read_32(DBSC4_REG_DBWAIT))
479 ;
480
481 /* Self-Refresh entry command */
482 reg = DBSC4_SET_DBCMD_OPC_SR | DBSC4_SET_DBCMD_CH_ALL |
483 DBSC4_SET_DBCMD_RANK_ALL | DBSC4_SET_DBCMD_ARG_ENTER;
484 mmio_write_32(DBSC4_REG_DBCMD, reg);
485 while (mmio_read_32(DBSC4_REG_DBWAIT))
486 ;
487
488 /* Mode Register Write command. (ODT disabled) */
489 reg = DBSC4_SET_DBCMD_OPC_MRW | DBSC4_SET_DBCMD_CH_ALL |
490 DBSC4_SET_DBCMD_RANK_ALL | DBSC4_SET_DBCMD_ARG_MRW_ODTC;
491 mmio_write_32(DBSC4_REG_DBCMD, reg);
492 while (mmio_read_32(DBSC4_REG_DBWAIT))
493 ;
494
495 /* Power Down entry command */
496 reg = DBSC4_SET_DBCMD_OPC_PD | DBSC4_SET_DBCMD_CH_ALL |
497 DBSC4_SET_DBCMD_RANK_ALL | DBSC4_SET_DBCMD_ARG_ENTER;
498 mmio_write_32(DBSC4_REG_DBCMD, reg);
499 while (mmio_read_32(DBSC4_REG_DBWAIT))
500 ;
501
502 /* Set the auto-refresh enable register */
503 mmio_write_32(DBSC4_REG_DBRFEN, 0U);
504 rcar_micro_delay(1U);
505
506 if (product == PRR_PRODUCT_M3 && cut < PRR_PRODUCT_30)
507 return;
508
509 if (product == PRR_PRODUCT_H3 && cut < PRR_PRODUCT_20)
510 return;
511
512 mmio_write_32(DBSC4_REG_DBSYSCNT0, DBSC4_SET_DBSYSCNT0_WRITE_DISABLE);
513 }
514
515 static void __attribute__ ((section(".system_ram")))
rcar_pwrc_set_self_refresh_e3(void)516 rcar_pwrc_set_self_refresh_e3(void)
517 {
518 uint32_t ddr_md;
519 uint32_t reg;
520
521 ddr_md = (mmio_read_32(RST_MODEMR) >> 19) & RST_MODEMR_BIT0;
522
523 /* Write enable */
524 mmio_write_32(DBSC4_REG_DBSYSCNT0, DBSC4_SET_DBSYSCNT0_WRITE_ENABLE);
525 mmio_write_32(DBSC4_REG_DBACEN, 0);
526 DBCAM_FLUSH(0);
527
528 reg = DBSC4_SET_DBCMD_OPC_PRE | DBSC4_SET_DBCMD_CH_ALL |
529 DBSC4_SET_DBCMD_RANK_ALL | DBSC4_SET_DBCMD_ARG_ALL;
530 mmio_write_32(DBSC4_REG_DBCMD, reg);
531 while (mmio_read_32(DBSC4_REG_DBWAIT))
532 ;
533
534 reg = DBSC4_SET_DBCMD_OPC_SR | DBSC4_SET_DBCMD_CH_ALL |
535 DBSC4_SET_DBCMD_RANK_ALL | DBSC4_SET_DBCMD_ARG_ENTER;
536 mmio_write_32(DBSC4_REG_DBCMD, reg);
537 while (mmio_read_32(DBSC4_REG_DBWAIT))
538 ;
539
540 /*
541 * Set the auto-refresh enable register
542 * Set the ARFEN bit to 0 in the DBRFEN
543 */
544 mmio_write_32(DBSC4_REG_DBRFEN, 0);
545
546 mmio_write_32(DBSC4_REG_DBPDLK0, DBSC4_SET_DBPDLK0_PHY_ACCESS);
547
548 mmio_write_32(DBSC4_REG_DBPDRGA0, DBSC4_SET_DBPDRGA0_ACIOCR0);
549 mmio_write_32(DBSC4_REG_DBPDRGD0, DBSC4_SET_DBPDRGD0_ACIOCR0);
550
551 /* DDR_DXCCR */
552 mmio_write_32(DBSC4_REG_DBPDRGA0, DBSC4_SET_DBPDRGA0_DXCCR);
553 mmio_write_32(DBSC4_REG_DBPDRGD0, DBSC4_SET_DBPDRGD0_DXCCR);
554
555 /* DDR_PGCR1 */
556 mmio_write_32(DBSC4_REG_DBPDRGA0, DBSC4_SET_DBPDRGA0_PGCR1);
557 mmio_write_32(DBSC4_REG_DBPDRGD0, DBSC4_SET_DBPDRGD0_PGCR1);
558
559 /* DDR_ACIOCR1 */
560 mmio_write_32(DBSC4_REG_DBPDRGA0, DBSC4_SET_DBPDRGA0_ACIOCR1);
561 mmio_write_32(DBSC4_REG_DBPDRGD0, DBSC4_SET_DBPDRGD0_ACIOCR1);
562
563 /* DDR_ACIOCR3 */
564 mmio_write_32(DBSC4_REG_DBPDRGA0, DBSC4_SET_DBPDRGA0_ACIOCR3);
565 mmio_write_32(DBSC4_REG_DBPDRGD0, DBSC4_SET_DBPDRGD0_ACIOCR3);
566
567 /* DDR_ACIOCR5 */
568 mmio_write_32(DBSC4_REG_DBPDRGA0, DBSC4_SET_DBPDRGA0_ACIOCR5);
569 mmio_write_32(DBSC4_REG_DBPDRGD0, DBSC4_SET_DBPDRGD0_ACIOCR5);
570
571 /* DDR_DX0GCR2 */
572 mmio_write_32(DBSC4_REG_DBPDRGA0, DBSC4_SET_DBPDRGA0_DX0GCR2);
573 mmio_write_32(DBSC4_REG_DBPDRGD0, DBSC4_SET_DBPDRGD0_DX0GCR2);
574
575 /* DDR_DX1GCR2 */
576 mmio_write_32(DBSC4_REG_DBPDRGA0, DBSC4_SET_DBPDRGA0_DX1GCR2);
577 mmio_write_32(DBSC4_REG_DBPDRGD0, DBSC4_SET_DBPDRGD0_DX1GCR2);
578
579 /* DDR_DX2GCR2 */
580 mmio_write_32(DBSC4_REG_DBPDRGA0, DBSC4_SET_DBPDRGA0_DX2GCR2);
581 mmio_write_32(DBSC4_REG_DBPDRGD0, DBSC4_SET_DBPDRGD0_DX2GCR2);
582
583 /* DDR_DX3GCR2 */
584 mmio_write_32(DBSC4_REG_DBPDRGA0, DBSC4_SET_DBPDRGA0_DX3GCR2);
585 mmio_write_32(DBSC4_REG_DBPDRGD0, DBSC4_SET_DBPDRGD0_DX3GCR2);
586
587 /* DDR_ZQCR */
588 mmio_write_32(DBSC4_REG_DBPDRGA0, DBSC4_SET_DBPDRGA0_ZQCR);
589
590 mmio_write_32(DBSC4_REG_DBPDRGD0, ddr_md == 0 ?
591 DBSC4_SET_DBPDRGD0_ZQCR_MD19_0 :
592 DBSC4_SET_DBPDRGD0_ZQCR_MD19_1);
593
594 /* DDR_DX0GCR0 */
595 mmio_write_32(DBSC4_REG_DBPDRGA0, DBSC4_SET_DBPDRGA0_DX0GCR0);
596 mmio_write_32(DBSC4_REG_DBPDRGD0, DBSC4_SET_DBPDRGD0_DX0GCR0);
597
598 /* DDR_DX1GCR0 */
599 mmio_write_32(DBSC4_REG_DBPDRGA0, DBSC4_SET_DBPDRGA0_DX1GCR0);
600 mmio_write_32(DBSC4_REG_DBPDRGD0, DBSC4_SET_DBPDRGD0_DX1GCR0);
601
602 /* DDR_DX2GCR0 */
603 mmio_write_32(DBSC4_REG_DBPDRGA0, DBSC4_SET_DBPDRGA0_DX2GCR0);
604 mmio_write_32(DBSC4_REG_DBPDRGD0, DBSC4_SET_DBPDRGD0_DX2GCR0);
605
606 /* DDR_DX3GCR0 */
607 mmio_write_32(DBSC4_REG_DBPDRGA0, DBSC4_SET_DBPDRGA0_DX3GCR0);
608 mmio_write_32(DBSC4_REG_DBPDRGD0, DBSC4_SET_DBPDRGD0_DX3GCR0);
609
610 /* DDR_DX0GCR1 */
611 mmio_write_32(DBSC4_REG_DBPDRGA0, DBSC4_SET_DBPDRGA0_DX0GCR1);
612 mmio_write_32(DBSC4_REG_DBPDRGD0, DBSC4_SET_DBPDRGD0_DX0GCR1);
613
614 /* DDR_DX1GCR1 */
615 mmio_write_32(DBSC4_REG_DBPDRGA0, DBSC4_SET_DBPDRGA0_DX1GCR1);
616 mmio_write_32(DBSC4_REG_DBPDRGD0, DBSC4_SET_DBPDRGD0_DX1GCR1);
617
618 /* DDR_DX2GCR1 */
619 mmio_write_32(DBSC4_REG_DBPDRGA0, DBSC4_SET_DBPDRGA0_DX2GCR1);
620 mmio_write_32(DBSC4_REG_DBPDRGD0, DBSC4_SET_DBPDRGD0_DX2GCR1);
621
622 /* DDR_DX3GCR1 */
623 mmio_write_32(DBSC4_REG_DBPDRGA0, DBSC4_SET_DBPDRGA0_DX3GCR1);
624 mmio_write_32(DBSC4_REG_DBPDRGD0, DBSC4_SET_DBPDRGD0_DX3GCR1);
625
626 /* DDR_DX0GCR3 */
627 mmio_write_32(DBSC4_REG_DBPDRGA0, DBSC4_SET_DBPDRGA0_DX0GCR3);
628 mmio_write_32(DBSC4_REG_DBPDRGD0, DBSC4_SET_DBPDRGD0_DX0GCR3);
629
630 /* DDR_DX1GCR3 */
631 mmio_write_32(DBSC4_REG_DBPDRGA0, DBSC4_SET_DBPDRGA0_DX1GCR3);
632 mmio_write_32(DBSC4_REG_DBPDRGD0, DBSC4_SET_DBPDRGD0_DX1GCR3);
633
634 /* DDR_DX2GCR3 */
635 mmio_write_32(DBSC4_REG_DBPDRGA0, DBSC4_SET_DBPDRGA0_DX2GCR3);
636 mmio_write_32(DBSC4_REG_DBPDRGD0, DBSC4_SET_DBPDRGD0_DX2GCR3);
637
638 /* DDR_DX3GCR3 */
639 mmio_write_32(DBSC4_REG_DBPDRGA0, DBSC4_SET_DBPDRGA0_DX3GCR3);
640 mmio_write_32(DBSC4_REG_DBPDRGD0, DBSC4_SET_DBPDRGD0_DX3GCR3);
641
642 /* Write disable */
643 mmio_write_32(DBSC4_REG_DBSYSCNT0, DBSC4_SET_DBSYSCNT0_WRITE_DISABLE);
644 }
645
646 void __attribute__ ((section(".system_ram"))) __attribute__ ((noinline))
rcar_pwrc_go_suspend_to_ram(void)647 rcar_pwrc_go_suspend_to_ram(void)
648 {
649 #if PMIC_ROHM_BD9571
650 int32_t rc = -1, qllm = -1;
651 uint8_t mode;
652 uint32_t i;
653 #endif
654 uint32_t reg, product;
655
656 reg = mmio_read_32(RCAR_PRR);
657 product = reg & PRR_PRODUCT_MASK;
658
659 if (product != PRR_PRODUCT_E3)
660 rcar_pwrc_set_self_refresh();
661 else
662 rcar_pwrc_set_self_refresh_e3();
663
664 #if PMIC_ROHM_BD9571
665 /* Set QLLM Cnt Disable */
666 for (i = 0; (i < PMIC_RETRY_MAX) && (qllm != 0); i++)
667 qllm = rcar_iic_dvfs_send(PMIC, PMIC_QLLM_CNT, 0);
668
669 /* Set trigger of power down to PMIV */
670 for (i = 0; (i < PMIC_RETRY_MAX) && (rc != 0) && (qllm == 0); i++) {
671 rc = rcar_iic_dvfs_receive(PMIC, PMIC_BKUP_MODE_CNT, &mode);
672 if (rc == 0) {
673 mode |= BIT_BKUP_CTRL_OUT;
674 rc = rcar_iic_dvfs_send(PMIC, PMIC_BKUP_MODE_CNT, mode);
675 }
676 }
677 #endif
678 wfi();
679
680 while (1)
681 ;
682 }
683
rcar_pwrc_set_suspend_to_ram(void)684 void rcar_pwrc_set_suspend_to_ram(void)
685 {
686 uintptr_t jump = (uintptr_t) &rcar_pwrc_go_suspend_to_ram;
687 uintptr_t stack = (uintptr_t) (DEVICE_SRAM_STACK_BASE +
688 DEVICE_SRAM_STACK_SIZE);
689 uint32_t sctlr;
690
691 rcar_pwrc_save_timer_state();
692
693 /* disable MMU */
694 sctlr = (uint32_t) read_sctlr_el3();
695 sctlr &= (uint32_t) ~SCTLR_EL3_M_BIT;
696 write_sctlr_el3((uint64_t) sctlr);
697
698 rcar_pwrc_switch_stack(jump, stack, NULL);
699 }
700
rcar_pwrc_init_suspend_to_ram(void)701 void rcar_pwrc_init_suspend_to_ram(void)
702 {
703 #if PMIC_ROHM_BD9571
704 uint8_t mode;
705
706 if (rcar_iic_dvfs_receive(PMIC, PMIC_BKUP_MODE_CNT, &mode))
707 panic();
708
709 mode &= (uint8_t) (~BIT_BKUP_CTRL_OUT);
710 if (rcar_iic_dvfs_send(PMIC, PMIC_BKUP_MODE_CNT, mode))
711 panic();
712 #endif
713 }
714
rcar_pwrc_suspend_to_ram(void)715 void rcar_pwrc_suspend_to_ram(void)
716 {
717 #if RCAR_SYSTEM_RESET_KEEPON_DDR
718 int32_t error;
719
720 error = rcar_iic_dvfs_send(PMIC, REG_KEEP10, 0);
721 if (error) {
722 ERROR("Failed send KEEP10 init ret=%d\n", error);
723 return;
724 }
725 #endif
726 rcar_pwrc_set_suspend_to_ram();
727 }
728 #endif
729
rcar_pwrc_code_copy_to_system_ram(void)730 void rcar_pwrc_code_copy_to_system_ram(void)
731 {
732 int ret __attribute__ ((unused)); /* in assert */
733 uint32_t attr;
734 struct device_sram_t {
735 uintptr_t base;
736 size_t len;
737 } sram = {
738 .base = (uintptr_t) DEVICE_SRAM_BASE,
739 .len = DEVICE_SRAM_SIZE,
740 };
741 struct ddr_code_t {
742 void *base;
743 size_t len;
744 } code = {
745 .base = (void *) SRAM_COPY_START,
746 .len = SYSTEM_RAM_END - SYSTEM_RAM_START,
747 };
748
749 attr = MT_MEMORY | MT_RW | MT_SECURE | MT_EXECUTE_NEVER;
750 ret = xlat_change_mem_attributes(sram.base, sram.len, attr);
751 assert(ret == 0);
752
753 memcpy((void *)sram.base, code.base, code.len);
754 flush_dcache_range((uint64_t) sram.base, code.len);
755
756 /* Invalidate instruction cache */
757 plat_invalidate_icache();
758 dsb();
759 isb();
760
761 attr = MT_MEMORY | MT_RO | MT_SECURE | MT_EXECUTE;
762 ret = xlat_change_mem_attributes(sram.base, sram.len, attr);
763 assert(ret == 0);
764 }
765
rcar_pwrc_get_cluster(void)766 uint32_t rcar_pwrc_get_cluster(void)
767 {
768 uint32_t reg;
769
770 reg = mmio_read_32(RCAR_PRR);
771
772 if (reg & (1U << (STATE_CA53_CPU + RCAR_CA53CPU_NUM_MAX)))
773 return RCAR_CLUSTER_CA57;
774
775 if (reg & (1U << (STATE_CA57_CPU + RCAR_CA57CPU_NUM_MAX)))
776 return RCAR_CLUSTER_CA53;
777
778 return RCAR_CLUSTER_A53A57;
779 }
780
rcar_pwrc_get_mpidr_cluster(uint64_t mpidr)781 uint32_t rcar_pwrc_get_mpidr_cluster(uint64_t mpidr)
782 {
783 uint32_t c = rcar_pwrc_get_cluster();
784
785 if (IS_A53A57(c)) {
786 if (mpidr & MPIDR_CLUSTER_MASK)
787 return RCAR_CLUSTER_CA53;
788
789 return RCAR_CLUSTER_CA57;
790 }
791
792 return c;
793 }
794
795 #if RCAR_LSI == RCAR_D3
rcar_pwrc_get_cpu_num(uint32_t c)796 uint32_t rcar_pwrc_get_cpu_num(uint32_t c)
797 {
798 return 1;
799 }
800 #else
rcar_pwrc_get_cpu_num(uint32_t c)801 uint32_t rcar_pwrc_get_cpu_num(uint32_t c)
802 {
803 uint32_t reg = mmio_read_32(RCAR_PRR);
804 uint32_t count = 0, i;
805
806 if (IS_A53A57(c) || IS_CA53(c)) {
807 if (reg & (1 << (STATE_CA53_CPU + RCAR_CA53CPU_NUM_MAX)))
808 goto count_ca57;
809
810 for (i = 0; i < RCAR_CA53CPU_NUM_MAX; i++) {
811 if (reg & (1 << (STATE_CA53_CPU + i)))
812 continue;
813 count++;
814 }
815 }
816
817 count_ca57:
818 if (IS_A53A57(c) || IS_CA57(c)) {
819 if (reg & (1U << (STATE_CA57_CPU + RCAR_CA57CPU_NUM_MAX)))
820 goto done;
821
822 for (i = 0; i < RCAR_CA57CPU_NUM_MAX; i++) {
823 if (reg & (1 << (STATE_CA57_CPU + i)))
824 continue;
825 count++;
826 }
827 }
828
829 done:
830 return count;
831 }
832 #endif
833
rcar_pwrc_cpu_on_check(uint64_t mpidr)834 int32_t rcar_pwrc_cpu_on_check(uint64_t mpidr)
835 {
836 uint64_t i;
837 uint64_t j;
838 uint64_t cpu_count;
839 uintptr_t reg_PSTR;
840 uint32_t status;
841 uint64_t my_cpu;
842 int32_t rtn;
843 uint32_t my_cluster_type;
844 const uint32_t cluster_type[PLATFORM_CLUSTER_COUNT] = {
845 RCAR_CLUSTER_CA53,
846 RCAR_CLUSTER_CA57
847 };
848 const uintptr_t registerPSTR[PLATFORM_CLUSTER_COUNT] = {
849 RCAR_CA53PSTR,
850 RCAR_CA57PSTR
851 };
852
853 my_cluster_type = rcar_pwrc_get_cluster();
854
855 rtn = 0;
856 my_cpu = mpidr & ((uint64_t)(MPIDR_CPU_MASK));
857 for (i = 0U; i < ((uint64_t)(PLATFORM_CLUSTER_COUNT)); i++) {
858 cpu_count = rcar_pwrc_get_cpu_num(cluster_type[i]);
859 reg_PSTR = registerPSTR[i];
860 for (j = 0U; j < cpu_count; j++) {
861 if ((my_cluster_type != cluster_type[i]) || (my_cpu != j)) {
862 status = mmio_read_32(reg_PSTR) >> (j * 4U);
863 if ((status & 0x00000003U) == 0U) {
864 rtn--;
865 }
866 }
867 }
868 }
869
870 return rtn;
871 }
872