1 /*
2 * Copyright (c) 2019-2020, NVIDIA CORPORATION. All rights reserved.
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7 #include <arch_helpers.h>
8 #include <assert.h>
9 #include <bl31/bl31.h>
10 #include <common/bl_common.h>
11 #include <common/interrupt_props.h>
12 #include <drivers/console.h>
13 #include <context.h>
14 #include <lib/el3_runtime/context_mgmt.h>
15 #include <cortex_a57.h>
16 #include <common/debug.h>
17 #include <denver.h>
18 #include <drivers/arm/gic_common.h>
19 #include <drivers/arm/gicv2.h>
20 #include <bl31/interrupt_mgmt.h>
21 #include <mce.h>
22 #include <mce_private.h>
23 #include <memctrl.h>
24 #include <plat/common/platform.h>
25 #include <smmu.h>
26 #include <spe.h>
27 #include <tegra_def.h>
28 #include <tegra_platform.h>
29 #include <tegra_private.h>
30 #include <lib/xlat_tables/xlat_tables_v2.h>
31
32 /* ID for spe-console */
33 #define TEGRA_CONSOLE_SPE_ID 0xFE
34
35 /*******************************************************************************
36 * Structure to store the SCR addresses and its expected settings.
37 *******************************************************************************
38 */
39 typedef struct {
40 uint32_t scr_addr;
41 uint32_t scr_val;
42 } scr_settings_t;
43
44 static const scr_settings_t t194_scr_settings[] = {
45 { SCRATCH_RSV68_SCR, SCRATCH_RSV68_SCR_VAL },
46 { SCRATCH_RSV71_SCR, SCRATCH_RSV71_SCR_VAL },
47 { SCRATCH_RSV72_SCR, SCRATCH_RSV72_SCR_VAL },
48 { SCRATCH_RSV75_SCR, SCRATCH_RSV75_SCR_VAL },
49 { SCRATCH_RSV81_SCR, SCRATCH_RSV81_SCR_VAL },
50 { SCRATCH_RSV97_SCR, SCRATCH_RSV97_SCR_VAL },
51 { SCRATCH_RSV99_SCR, SCRATCH_RSV99_SCR_VAL },
52 { SCRATCH_RSV109_SCR, SCRATCH_RSV109_SCR_VAL },
53 { MISCREG_SCR_SCRTZWELCK, MISCREG_SCR_SCRTZWELCK_VAL }
54 };
55
56 /*******************************************************************************
57 * The Tegra power domain tree has a single system level power domain i.e. a
58 * single root node. The first entry in the power domain descriptor specifies
59 * the number of power domains at the highest power level.
60 *******************************************************************************
61 */
62 static const uint8_t tegra_power_domain_tree_desc[] = {
63 /* No of root nodes */
64 1,
65 /* No of clusters */
66 PLATFORM_CLUSTER_COUNT,
67 /* No of CPU cores - cluster0 */
68 PLATFORM_MAX_CPUS_PER_CLUSTER,
69 /* No of CPU cores - cluster1 */
70 PLATFORM_MAX_CPUS_PER_CLUSTER,
71 /* No of CPU cores - cluster2 */
72 PLATFORM_MAX_CPUS_PER_CLUSTER,
73 /* No of CPU cores - cluster3 */
74 PLATFORM_MAX_CPUS_PER_CLUSTER
75 };
76
77 /*******************************************************************************
78 * This function returns the Tegra default topology tree information.
79 ******************************************************************************/
plat_get_power_domain_tree_desc(void)80 const uint8_t *plat_get_power_domain_tree_desc(void)
81 {
82 return tegra_power_domain_tree_desc;
83 }
84
85 /*
86 * Table of regions to map using the MMU.
87 */
88 static const mmap_region_t tegra_mmap[] = {
89 MAP_REGION_FLAT(TEGRA_MISC_BASE, 0x4000U, /* 16KB */
90 (uint8_t)MT_DEVICE | (uint8_t)MT_RW | (uint8_t)MT_SECURE),
91 MAP_REGION_FLAT(TEGRA_GPCDMA_BASE, 0x10000U, /* 64KB */
92 (uint8_t)MT_DEVICE | (uint8_t)MT_RW | (uint8_t)MT_SECURE),
93 MAP_REGION_FLAT(TEGRA_MC_STREAMID_BASE, 0x8000U, /* 32KB */
94 (uint8_t)MT_DEVICE | (uint8_t)MT_RW | (uint8_t)MT_SECURE),
95 MAP_REGION_FLAT(TEGRA_MC_BASE, 0x8000U, /* 32KB */
96 (uint8_t)MT_DEVICE | (uint8_t)MT_RW | (uint8_t)MT_SECURE),
97 #if !ENABLE_CONSOLE_SPE
98 MAP_REGION_FLAT(TEGRA_UARTA_BASE, 0x20000U, /* 128KB - UART A, B*/
99 (uint8_t)MT_DEVICE | (uint8_t)MT_RW | (uint8_t)MT_SECURE),
100 MAP_REGION_FLAT(TEGRA_UARTC_BASE, 0x20000U, /* 128KB - UART C, G */
101 (uint8_t)MT_DEVICE | (uint8_t)MT_RW | (uint8_t)MT_SECURE),
102 MAP_REGION_FLAT(TEGRA_UARTD_BASE, 0x30000U, /* 192KB - UART D, E, F */
103 (uint8_t)MT_DEVICE | (uint8_t)MT_RW | (uint8_t)MT_SECURE),
104 #endif
105 MAP_REGION_FLAT(TEGRA_XUSB_PADCTL_BASE, 0x2000U, /* 8KB */
106 (uint8_t)MT_DEVICE | (uint8_t)MT_RW | (uint8_t)MT_SECURE),
107 MAP_REGION_FLAT(TEGRA_GICD_BASE, 0x1000, /* 4KB */
108 (uint8_t)MT_DEVICE | (uint8_t)MT_RW | (uint8_t)MT_SECURE),
109 MAP_REGION_FLAT(TEGRA_GICC_BASE, 0x1000, /* 4KB */
110 (uint8_t)MT_DEVICE | (uint8_t)MT_RW | (uint8_t)MT_SECURE),
111 MAP_REGION_FLAT(TEGRA_SE0_BASE, 0x1000U, /* 4KB */
112 (uint8_t)MT_DEVICE | (uint8_t)MT_RW | (uint8_t)MT_SECURE),
113 MAP_REGION_FLAT(TEGRA_PKA1_BASE, 0x1000U, /* 4KB */
114 (uint8_t)MT_DEVICE | (uint8_t)MT_RW | (uint8_t)MT_SECURE),
115 MAP_REGION_FLAT(TEGRA_RNG1_BASE, 0x1000U, /* 4KB */
116 (uint8_t)MT_DEVICE | (uint8_t)MT_RW | (uint8_t)MT_SECURE),
117 MAP_REGION_FLAT(TEGRA_HSP_DBELL_BASE, 0x1000U, /* 4KB */
118 (uint8_t)MT_DEVICE | (uint8_t)MT_RW | (uint8_t)MT_SECURE),
119 #if ENABLE_CONSOLE_SPE
120 MAP_REGION_FLAT(TEGRA_CONSOLE_SPE_BASE, 0x1000U, /* 4KB */
121 (uint8_t)MT_DEVICE | (uint8_t)MT_RW | (uint8_t)MT_SECURE),
122 #endif
123 MAP_REGION_FLAT(TEGRA_TMRUS_BASE, TEGRA_TMRUS_SIZE, /* 4KB */
124 (uint8_t)MT_DEVICE | (uint8_t)MT_RW | (uint8_t)MT_SECURE),
125 MAP_REGION_FLAT(TEGRA_SCRATCH_BASE, 0x1000U, /* 4KB */
126 (uint8_t)MT_DEVICE | (uint8_t)MT_RW | (uint8_t)MT_SECURE),
127 MAP_REGION_FLAT(TEGRA_SMMU2_BASE, 0x800000U, /* 8MB */
128 (uint8_t)MT_DEVICE | (uint8_t)MT_RW | (uint8_t)MT_SECURE),
129 MAP_REGION_FLAT(TEGRA_SMMU1_BASE, 0x800000U, /* 8MB */
130 (uint8_t)MT_DEVICE | (uint8_t)MT_RW | (uint8_t)MT_SECURE),
131 MAP_REGION_FLAT(TEGRA_SMMU0_BASE, 0x800000U, /* 8MB */
132 (uint8_t)MT_DEVICE | (uint8_t)MT_RW | (uint8_t)MT_SECURE),
133 MAP_REGION_FLAT(TEGRA_BPMP_IPC_TX_PHYS_BASE, 0x10000U, /* 64KB */
134 (uint8_t)MT_DEVICE | (uint8_t)MT_RW | (uint8_t)MT_SECURE),
135 MAP_REGION_FLAT(TEGRA_CAR_RESET_BASE, 0x10000U, /* 64KB */
136 (uint8_t)MT_DEVICE | (uint8_t)MT_RW | (uint8_t)MT_SECURE),
137 {0}
138 };
139
140 /*******************************************************************************
141 * Set up the pagetables as per the platform memory map & initialize the MMU
142 ******************************************************************************/
plat_get_mmio_map(void)143 const mmap_region_t *plat_get_mmio_map(void)
144 {
145 /* MMIO space */
146 return tegra_mmap;
147 }
148
149 /*******************************************************************************
150 * Handler to get the System Counter Frequency
151 ******************************************************************************/
plat_get_syscnt_freq2(void)152 uint32_t plat_get_syscnt_freq2(void)
153 {
154 return 31250000;
155 }
156
157 #if !ENABLE_CONSOLE_SPE
158 /*******************************************************************************
159 * Maximum supported UART controllers
160 ******************************************************************************/
161 #define TEGRA194_MAX_UART_PORTS 7
162
163 /*******************************************************************************
164 * This variable holds the UART port base addresses
165 ******************************************************************************/
166 static uint32_t tegra194_uart_addresses[TEGRA194_MAX_UART_PORTS + 1] = {
167 0, /* undefined - treated as an error case */
168 TEGRA_UARTA_BASE,
169 TEGRA_UARTB_BASE,
170 TEGRA_UARTC_BASE,
171 TEGRA_UARTD_BASE,
172 TEGRA_UARTE_BASE,
173 TEGRA_UARTF_BASE,
174 TEGRA_UARTG_BASE
175 };
176 #endif
177
178 /*******************************************************************************
179 * Enable console corresponding to the console ID
180 ******************************************************************************/
plat_enable_console(int32_t id)181 void plat_enable_console(int32_t id)
182 {
183 uint32_t console_clock = 0U;
184
185 #if ENABLE_CONSOLE_SPE
186 static console_t spe_console;
187
188 if (id == TEGRA_CONSOLE_SPE_ID) {
189 (void)console_spe_register(TEGRA_CONSOLE_SPE_BASE,
190 console_clock,
191 TEGRA_CONSOLE_BAUDRATE,
192 &spe_console);
193 console_set_scope(&spe_console, CONSOLE_FLAG_BOOT |
194 CONSOLE_FLAG_RUNTIME | CONSOLE_FLAG_CRASH);
195 }
196 #else
197 static console_t uart_console;
198
199 if ((id > 0) && (id < TEGRA194_MAX_UART_PORTS)) {
200 /*
201 * Reference clock used by the FPGAs is a lot slower.
202 */
203 if (tegra_platform_is_fpga()) {
204 console_clock = TEGRA_BOOT_UART_CLK_13_MHZ;
205 } else {
206 console_clock = TEGRA_BOOT_UART_CLK_408_MHZ;
207 }
208
209 (void)console_16550_register(tegra194_uart_addresses[id],
210 console_clock,
211 TEGRA_CONSOLE_BAUDRATE,
212 &uart_console);
213 console_set_scope(&uart_console, CONSOLE_FLAG_BOOT |
214 CONSOLE_FLAG_RUNTIME | CONSOLE_FLAG_CRASH);
215 }
216 #endif
217 }
218
219 /*******************************************************************************
220 * Verify SCR settings
221 ******************************************************************************/
tegra194_is_scr_valid(void)222 static inline bool tegra194_is_scr_valid(void)
223 {
224 uint32_t scr_val;
225 bool ret = true;
226
227 for (uint8_t i = 0U; i < ARRAY_SIZE(t194_scr_settings); i++) {
228 scr_val = mmio_read_32((uintptr_t)t194_scr_settings[i].scr_addr);
229 if (scr_val != t194_scr_settings[i].scr_val) {
230 ERROR("Mismatch at SCR addr = 0x%x\n", t194_scr_settings[i].scr_addr);
231 ret = false;
232 }
233 }
234 return ret;
235 }
236
237 /*******************************************************************************
238 * Handler for early platform setup
239 ******************************************************************************/
plat_early_platform_setup(void)240 void plat_early_platform_setup(void)
241 {
242 const plat_params_from_bl2_t *params_from_bl2 = bl31_get_plat_params();
243 uint8_t enable_ccplex_lock_step = params_from_bl2->enable_ccplex_lock_step;
244 uint64_t actlr_elx;
245
246 /* Verify chip id is t194 */
247 assert(tegra_chipid_is_t194());
248
249 /* Verify SCR settings */
250 if (tegra_platform_is_silicon()) {
251 assert(tegra194_is_scr_valid());
252 }
253
254 /* sanity check MCE firmware compatibility */
255 mce_verify_firmware_version();
256
257 #if RAS_EXTENSION
258 /* Enable Uncorrectable RAS error */
259 tegra194_ras_enable();
260 #endif
261
262 /*
263 * Program XUSB STREAMIDs
264 * ======================
265 * T19x XUSB has support for XUSB virtualization. It will have one
266 * physical function (PF) and four Virtual function (VF)
267 *
268 * There were below two SIDs for XUSB until T186.
269 * 1) #define TEGRA_SID_XUSB_HOST 0x1bU
270 * 2) #define TEGRA_SID_XUSB_DEV 0x1cU
271 *
272 * We have below four new SIDs added for VF(s)
273 * 3) #define TEGRA_SID_XUSB_VF0 0x5dU
274 * 4) #define TEGRA_SID_XUSB_VF1 0x5eU
275 * 5) #define TEGRA_SID_XUSB_VF2 0x5fU
276 * 6) #define TEGRA_SID_XUSB_VF3 0x60U
277 *
278 * When virtualization is enabled then we have to disable SID override
279 * and program above SIDs in below newly added SID registers in XUSB
280 * PADCTL MMIO space. These registers are TZ protected and so need to
281 * be done in ATF.
282 * a) #define XUSB_PADCTL_HOST_AXI_STREAMID_PF_0 (0x136cU)
283 * b) #define XUSB_PADCTL_DEV_AXI_STREAMID_PF_0 (0x139cU)
284 * c) #define XUSB_PADCTL_HOST_AXI_STREAMID_VF_0 (0x1370U)
285 * d) #define XUSB_PADCTL_HOST_AXI_STREAMID_VF_1 (0x1374U)
286 * e) #define XUSB_PADCTL_HOST_AXI_STREAMID_VF_2 (0x1378U)
287 * f) #define XUSB_PADCTL_HOST_AXI_STREAMID_VF_3 (0x137cU)
288 *
289 * This change disables SID override and programs XUSB SIDs in
290 * above registers to support both virtualization and
291 * non-virtualization platforms
292 */
293 if (tegra_platform_is_silicon() || tegra_platform_is_fpga()) {
294
295 mmio_write_32(TEGRA_XUSB_PADCTL_BASE +
296 XUSB_PADCTL_HOST_AXI_STREAMID_PF_0, TEGRA_SID_XUSB_HOST);
297 assert(mmio_read_32(TEGRA_XUSB_PADCTL_BASE +
298 XUSB_PADCTL_HOST_AXI_STREAMID_PF_0) == TEGRA_SID_XUSB_HOST);
299 mmio_write_32(TEGRA_XUSB_PADCTL_BASE +
300 XUSB_PADCTL_HOST_AXI_STREAMID_VF_0, TEGRA_SID_XUSB_VF0);
301 assert(mmio_read_32(TEGRA_XUSB_PADCTL_BASE +
302 XUSB_PADCTL_HOST_AXI_STREAMID_VF_0) == TEGRA_SID_XUSB_VF0);
303 mmio_write_32(TEGRA_XUSB_PADCTL_BASE +
304 XUSB_PADCTL_HOST_AXI_STREAMID_VF_1, TEGRA_SID_XUSB_VF1);
305 assert(mmio_read_32(TEGRA_XUSB_PADCTL_BASE +
306 XUSB_PADCTL_HOST_AXI_STREAMID_VF_1) == TEGRA_SID_XUSB_VF1);
307 mmio_write_32(TEGRA_XUSB_PADCTL_BASE +
308 XUSB_PADCTL_HOST_AXI_STREAMID_VF_2, TEGRA_SID_XUSB_VF2);
309 assert(mmio_read_32(TEGRA_XUSB_PADCTL_BASE +
310 XUSB_PADCTL_HOST_AXI_STREAMID_VF_2) == TEGRA_SID_XUSB_VF2);
311 mmio_write_32(TEGRA_XUSB_PADCTL_BASE +
312 XUSB_PADCTL_HOST_AXI_STREAMID_VF_3, TEGRA_SID_XUSB_VF3);
313 assert(mmio_read_32(TEGRA_XUSB_PADCTL_BASE +
314 XUSB_PADCTL_HOST_AXI_STREAMID_VF_3) == TEGRA_SID_XUSB_VF3);
315 mmio_write_32(TEGRA_XUSB_PADCTL_BASE +
316 XUSB_PADCTL_DEV_AXI_STREAMID_PF_0, TEGRA_SID_XUSB_DEV);
317 assert(mmio_read_32(TEGRA_XUSB_PADCTL_BASE +
318 XUSB_PADCTL_DEV_AXI_STREAMID_PF_0) == TEGRA_SID_XUSB_DEV);
319 }
320
321 /*
322 * Enable dual execution optimized translations for all ELx.
323 */
324 if (enable_ccplex_lock_step != 0U) {
325 actlr_elx = read_actlr_el3();
326 actlr_elx |= DENVER_CPU_ENABLE_DUAL_EXEC_EL3;
327 write_actlr_el3(actlr_elx);
328 /* check if the bit is actually set */
329 assert((read_actlr_el3() & DENVER_CPU_ENABLE_DUAL_EXEC_EL3) != 0ULL);
330
331 actlr_elx = read_actlr_el2();
332 actlr_elx |= DENVER_CPU_ENABLE_DUAL_EXEC_EL2;
333 write_actlr_el2(actlr_elx);
334 /* check if the bit is actually set */
335 assert((read_actlr_el2() & DENVER_CPU_ENABLE_DUAL_EXEC_EL2) != 0ULL);
336
337 actlr_elx = read_actlr_el1();
338 actlr_elx |= DENVER_CPU_ENABLE_DUAL_EXEC_EL1;
339 write_actlr_el1(actlr_elx);
340 /* check if the bit is actually set */
341 assert((read_actlr_el1() & DENVER_CPU_ENABLE_DUAL_EXEC_EL1) != 0ULL);
342 }
343 }
344
345 /* Secure IRQs for Tegra194 */
346 static const interrupt_prop_t tegra194_interrupt_props[] = {
347 INTR_PROP_DESC(TEGRA_SDEI_SGI_PRIVATE, PLAT_SDEI_CRITICAL_PRI,
348 GICV2_INTR_GROUP0, GIC_INTR_CFG_EDGE),
349 INTR_PROP_DESC(TEGRA194_TOP_WDT_IRQ, PLAT_TEGRA_WDT_PRIO,
350 GICV2_INTR_GROUP0, GIC_INTR_CFG_EDGE)
351 };
352
353 /*******************************************************************************
354 * Initialize the GIC and SGIs
355 ******************************************************************************/
plat_gic_setup(void)356 void plat_gic_setup(void)
357 {
358 tegra_gic_setup(tegra194_interrupt_props, ARRAY_SIZE(tegra194_interrupt_props));
359 tegra_gic_init();
360
361 /*
362 * Initialize the FIQ handler
363 */
364 tegra_fiq_handler_setup();
365 }
366
367 /*******************************************************************************
368 * Return pointer to the BL31 params from previous bootloader
369 ******************************************************************************/
plat_get_bl31_params(void)370 struct tegra_bl31_params *plat_get_bl31_params(void)
371 {
372 uint64_t val;
373
374 val = (mmio_read_32(TEGRA_SCRATCH_BASE + SCRATCH_BL31_PARAMS_HI_ADDR) &
375 SCRATCH_BL31_PARAMS_HI_ADDR_MASK) >> SCRATCH_BL31_PARAMS_HI_ADDR_SHIFT;
376 val <<= 32;
377 val |= mmio_read_32(TEGRA_SCRATCH_BASE + SCRATCH_BL31_PARAMS_LO_ADDR);
378
379 return (struct tegra_bl31_params *)(uintptr_t)val;
380 }
381
382 /*******************************************************************************
383 * Return pointer to the BL31 platform params from previous bootloader
384 ******************************************************************************/
plat_get_bl31_plat_params(void)385 plat_params_from_bl2_t *plat_get_bl31_plat_params(void)
386 {
387 uint64_t val;
388
389 val = (mmio_read_32(TEGRA_SCRATCH_BASE + SCRATCH_BL31_PLAT_PARAMS_HI_ADDR) &
390 SCRATCH_BL31_PLAT_PARAMS_HI_ADDR_MASK) >> SCRATCH_BL31_PLAT_PARAMS_HI_ADDR_SHIFT;
391 val <<= 32;
392 val |= mmio_read_32(TEGRA_SCRATCH_BASE + SCRATCH_BL31_PLAT_PARAMS_LO_ADDR);
393
394 return (plat_params_from_bl2_t *)(uintptr_t)val;
395 }
396
397 /*******************************************************************************
398 * Handler for late platform setup
399 ******************************************************************************/
plat_late_platform_setup(void)400 void plat_late_platform_setup(void)
401 {
402 #if ENABLE_STRICT_CHECKING_MODE
403 /*
404 * Enable strict checking after programming the GSC for
405 * enabling TZSRAM and TZDRAM
406 */
407 mce_enable_strict_checking();
408 mce_verify_strict_checking();
409 #endif
410 }
411
412 /*******************************************************************************
413 * Handler to indicate support for System Suspend
414 ******************************************************************************/
plat_supports_system_suspend(void)415 bool plat_supports_system_suspend(void)
416 {
417 return true;
418 }
419
420 /*******************************************************************************
421 * Platform specific runtime setup.
422 ******************************************************************************/
plat_runtime_setup(void)423 void plat_runtime_setup(void)
424 {
425 /*
426 * During cold boot, it is observed that the arbitration
427 * bit is set in the Memory controller leading to false
428 * error interrupts in the non-secure world. To avoid
429 * this, clean the interrupt status register before
430 * booting into the non-secure world
431 */
432 tegra_memctrl_clear_pending_interrupts();
433
434 /*
435 * During boot, USB3 and flash media (SDMMC/SATA) devices need
436 * access to IRAM. Because these clients connect to the MC and
437 * do not have a direct path to the IRAM, the MC implements AHB
438 * redirection during boot to allow path to IRAM. In this mode
439 * accesses to a programmed memory address aperture are directed
440 * to the AHB bus, allowing access to the IRAM. This mode must be
441 * disabled before we jump to the non-secure world.
442 */
443 tegra_memctrl_disable_ahb_redirection();
444
445 /*
446 * Verify the integrity of the previously configured SMMU(s) settings
447 */
448 tegra_smmu_verify();
449 }
450