1 /* 2 * Copyright (c) 2015-2021, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef PLATFORM_DEF_H 8 #define PLATFORM_DEF_H 9 10 #include <arch.h> 11 #include <drivers/arm/gic_common.h> 12 #include <lib/utils_def.h> 13 #include <plat/common/common_def.h> 14 15 #include "../stm32mp1_def.h" 16 17 /******************************************************************************* 18 * Generic platform constants 19 ******************************************************************************/ 20 21 /* Size of cacheable stacks */ 22 #if defined(IMAGE_BL32) 23 #define PLATFORM_STACK_SIZE 0x600 24 #else 25 #define PLATFORM_STACK_SIZE 0xC00 26 #endif 27 28 #ifdef AARCH32_SP_OPTEE 29 #define OPTEE_HEADER_IMAGE_NAME "teeh" 30 #define OPTEE_PAGED_IMAGE_NAME "teed" 31 #define OPTEE_PAGER_IMAGE_NAME "teex" 32 #define OPTEE_HEADER_BINARY_TYPE U(0x20) 33 #define OPTEE_PAGER_BINARY_TYPE U(0x21) 34 #define OPTEE_PAGED_BINARY_TYPE U(0x22) 35 #endif 36 37 /* SSBL = second stage boot loader */ 38 #define BL33_IMAGE_NAME "ssbl" 39 #define BL33_BINARY_TYPE U(0x0) 40 41 #define STM32MP_PRIMARY_CPU U(0x0) 42 #define STM32MP_SECONDARY_CPU U(0x1) 43 44 #define PLATFORM_CLUSTER_COUNT U(1) 45 #define PLATFORM_CLUSTER0_CORE_COUNT U(2) 46 #define PLATFORM_CLUSTER1_CORE_COUNT U(0) 47 #define PLATFORM_CORE_COUNT (PLATFORM_CLUSTER1_CORE_COUNT + \ 48 PLATFORM_CLUSTER0_CORE_COUNT) 49 #define PLATFORM_MAX_CPUS_PER_CLUSTER 2 50 51 #define MAX_IO_DEVICES U(4) 52 #define MAX_IO_HANDLES U(4) 53 #define MAX_IO_BLOCK_DEVICES U(1) 54 #define MAX_IO_MTD_DEVICES U(1) 55 56 /******************************************************************************* 57 * BL2 specific defines. 58 ******************************************************************************/ 59 /* 60 * Put BL2 just below BL3-1. BL2_BASE is calculated using the current BL2 debug 61 * size plus a little space for growth. 62 */ 63 #define BL2_BASE STM32MP_BL2_BASE 64 #define BL2_LIMIT (STM32MP_BL2_BASE + \ 65 STM32MP_BL2_SIZE) 66 67 /******************************************************************************* 68 * BL32 specific defines. 69 ******************************************************************************/ 70 #ifndef AARCH32_SP_OPTEE 71 #if ENABLE_PIE 72 #define BL32_BASE 0 73 #define BL32_LIMIT STM32MP_BL32_SIZE 74 #else 75 #define BL32_BASE STM32MP_BL32_BASE 76 #define BL32_LIMIT (STM32MP_BL32_BASE + \ 77 STM32MP_BL32_SIZE) 78 #endif 79 #endif 80 81 /******************************************************************************* 82 * BL33 specific defines. 83 ******************************************************************************/ 84 #define BL33_BASE STM32MP_BL33_BASE 85 86 /* 87 * Load address of BL33 for this platform port 88 */ 89 #define PLAT_STM32MP_NS_IMAGE_OFFSET BL33_BASE 90 91 /******************************************************************************* 92 * DTB specific defines. 93 ******************************************************************************/ 94 #define DTB_BASE STM32MP_DTB_BASE 95 #define DTB_LIMIT (STM32MP_DTB_BASE + \ 96 STM32MP_DTB_SIZE) 97 98 /******************************************************************************* 99 * Platform specific page table and MMU setup constants 100 ******************************************************************************/ 101 #define PLAT_PHY_ADDR_SPACE_SIZE (ULL(1) << 32) 102 #define PLAT_VIRT_ADDR_SPACE_SIZE (ULL(1) << 32) 103 104 /******************************************************************************* 105 * Declarations and constants to access the mailboxes safely. Each mailbox is 106 * aligned on the biggest cache line size in the platform. This is known only 107 * to the platform as it might have a combination of integrated and external 108 * caches. Such alignment ensures that two maiboxes do not sit on the same cache 109 * line at any cache level. They could belong to different cpus/clusters & 110 * get written while being protected by different locks causing corruption of 111 * a valid mailbox address. 112 ******************************************************************************/ 113 #define CACHE_WRITEBACK_SHIFT 6 114 #define CACHE_WRITEBACK_GRANULE (U(1) << CACHE_WRITEBACK_SHIFT) 115 116 /* 117 * Secure Interrupt: based on the standard ARM mapping 118 */ 119 #define ARM_IRQ_SEC_PHY_TIMER U(29) 120 121 #define ARM_IRQ_SEC_SGI_0 U(8) 122 #define ARM_IRQ_SEC_SGI_1 U(9) 123 #define ARM_IRQ_SEC_SGI_2 U(10) 124 #define ARM_IRQ_SEC_SGI_3 U(11) 125 #define ARM_IRQ_SEC_SGI_4 U(12) 126 #define ARM_IRQ_SEC_SGI_5 U(13) 127 #define ARM_IRQ_SEC_SGI_6 U(14) 128 #define ARM_IRQ_SEC_SGI_7 U(15) 129 130 #define STM32MP1_IRQ_TZC400 U(36) 131 #define STM32MP1_IRQ_TAMPSERRS U(229) 132 #define STM32MP1_IRQ_AXIERRIRQ U(244) 133 134 /* 135 * Define a list of Group 1 Secure and Group 0 interrupts as per GICv3 136 * terminology. On a GICv2 system or mode, the lists will be merged and treated 137 * as Group 0 interrupts. 138 */ 139 #define PLATFORM_G1S_PROPS(grp) \ 140 INTR_PROP_DESC(ARM_IRQ_SEC_PHY_TIMER, \ 141 GIC_HIGHEST_SEC_PRIORITY, \ 142 grp, GIC_INTR_CFG_LEVEL), \ 143 INTR_PROP_DESC(STM32MP1_IRQ_AXIERRIRQ, \ 144 GIC_HIGHEST_SEC_PRIORITY, \ 145 grp, GIC_INTR_CFG_LEVEL), \ 146 INTR_PROP_DESC(STM32MP1_IRQ_TZC400, \ 147 GIC_HIGHEST_SEC_PRIORITY, \ 148 grp, GIC_INTR_CFG_LEVEL), \ 149 INTR_PROP_DESC(ARM_IRQ_SEC_SGI_1, \ 150 GIC_HIGHEST_SEC_PRIORITY, \ 151 grp, GIC_INTR_CFG_EDGE), \ 152 INTR_PROP_DESC(ARM_IRQ_SEC_SGI_2, \ 153 GIC_HIGHEST_SEC_PRIORITY, \ 154 grp, GIC_INTR_CFG_EDGE), \ 155 INTR_PROP_DESC(ARM_IRQ_SEC_SGI_3, \ 156 GIC_HIGHEST_SEC_PRIORITY, \ 157 grp, GIC_INTR_CFG_EDGE), \ 158 INTR_PROP_DESC(ARM_IRQ_SEC_SGI_4, \ 159 GIC_HIGHEST_SEC_PRIORITY, \ 160 grp, GIC_INTR_CFG_EDGE), \ 161 INTR_PROP_DESC(ARM_IRQ_SEC_SGI_5, \ 162 GIC_HIGHEST_SEC_PRIORITY, \ 163 grp, GIC_INTR_CFG_EDGE), \ 164 INTR_PROP_DESC(ARM_IRQ_SEC_SGI_7, \ 165 GIC_HIGHEST_SEC_PRIORITY, \ 166 grp, GIC_INTR_CFG_EDGE) 167 168 #define PLATFORM_G0_PROPS(grp) \ 169 INTR_PROP_DESC(ARM_IRQ_SEC_SGI_0, \ 170 GIC_HIGHEST_SEC_PRIORITY, \ 171 grp, GIC_INTR_CFG_EDGE), \ 172 INTR_PROP_DESC(ARM_IRQ_SEC_SGI_6, \ 173 GIC_HIGHEST_SEC_PRIORITY, \ 174 grp, GIC_INTR_CFG_EDGE) 175 176 /* 177 * Power 178 */ 179 #define PLAT_MAX_PWR_LVL U(1) 180 181 /* Local power state for power domains in Run state. */ 182 #define ARM_LOCAL_STATE_RUN U(0) 183 /* Local power state for retention. Valid only for CPU power domains */ 184 #define ARM_LOCAL_STATE_RET U(1) 185 /* Local power state for power-down. Valid for CPU and cluster power domains */ 186 #define ARM_LOCAL_STATE_OFF U(2) 187 /* 188 * This macro defines the deepest retention state possible. 189 * A higher state id will represent an invalid or a power down state. 190 */ 191 #define PLAT_MAX_RET_STATE ARM_LOCAL_STATE_RET 192 /* 193 * This macro defines the deepest power down states possible. Any state ID 194 * higher than this is invalid. 195 */ 196 #define PLAT_MAX_OFF_STATE ARM_LOCAL_STATE_OFF 197 198 /******************************************************************************* 199 * Size of the per-cpu data in bytes that should be reserved in the generic 200 * per-cpu data structure for the FVP port. 201 ******************************************************************************/ 202 #define PLAT_PCPU_DATA_SIZE 2 203 204 /******************************************************************************* 205 * Number of parallel entry slots in SMT SCMI server entry context. For this 206 * platform, SCMI server is reached through SMC only, hence the number of 207 * entry slots. 208 ******************************************************************************/ 209 #define PLAT_SMT_ENTRY_COUNT PLATFORM_CORE_COUNT 210 211 #endif /* PLATFORM_DEF_H */ 212