1 /** @file 2 3 Copyright (c) 2015, Intel Corporation. All rights reserved.<BR> 4 SPDX-License-Identifier: BSD-2-Clause-Patent 5 6 **/ 7 8 #ifndef _EMMC_HCI_H_ 9 #define _EMMC_HCI_H_ 10 11 // 12 // EMMC Host Controller MMIO Register Offset 13 // 14 #define EMMC_HC_SDMA_ADDR 0x00 15 #define EMMC_HC_ARG2 0x00 16 #define EMMC_HC_BLK_SIZE 0x04 17 #define EMMC_HC_BLK_COUNT 0x06 18 #define EMMC_HC_ARG1 0x08 19 #define EMMC_HC_TRANS_MOD 0x0C 20 #define EMMC_HC_COMMAND 0x0E 21 #define EMMC_HC_RESPONSE 0x10 22 #define EMMC_HC_BUF_DAT_PORT 0x20 23 #define EMMC_HC_PRESENT_STATE 0x24 24 #define EMMC_HC_HOST_CTRL1 0x28 25 #define EMMC_HC_POWER_CTRL 0x29 26 #define EMMC_HC_BLK_GAP_CTRL 0x2A 27 #define EMMC_HC_WAKEUP_CTRL 0x2B 28 #define EMMC_HC_CLOCK_CTRL 0x2C 29 #define EMMC_HC_TIMEOUT_CTRL 0x2E 30 #define EMMC_HC_SW_RST 0x2F 31 #define EMMC_HC_NOR_INT_STS 0x30 32 #define EMMC_HC_ERR_INT_STS 0x32 33 #define EMMC_HC_NOR_INT_STS_EN 0x34 34 #define EMMC_HC_ERR_INT_STS_EN 0x36 35 #define EMMC_HC_NOR_INT_SIG_EN 0x38 36 #define EMMC_HC_ERR_INT_SIG_EN 0x3A 37 #define EMMC_HC_AUTO_CMD_ERR_STS 0x3C 38 #define EMMC_HC_HOST_CTRL2 0x3E 39 #define EMMC_HC_CAP 0x40 40 #define EMMC_HC_MAX_CURRENT_CAP 0x48 41 #define EMMC_HC_FORCE_EVT_AUTO_CMD 0x50 42 #define EMMC_HC_FORCE_EVT_ERR_INT 0x52 43 #define EMMC_HC_ADMA_ERR_STS 0x54 44 #define EMMC_HC_ADMA_SYS_ADDR 0x58 45 #define EMMC_HC_PRESET_VAL 0x60 46 #define EMMC_HC_SHARED_BUS_CTRL 0xE0 47 #define EMMC_HC_SLOT_INT_STS 0xFC 48 #define EMMC_HC_CTRL_VER 0xFE 49 50 // 51 // The transfer modes supported by SD Host Controller 52 // Simplified Spec 3.0 Table 1-2 53 // 54 typedef enum { 55 EmmcNoData, 56 EmmcPioMode, 57 EmmcSdmaMode, 58 EmmcAdmaMode 59 } EMMC_HC_TRANSFER_MODE; 60 61 // 62 // The maximum data length of each descriptor line 63 // 64 #define ADMA_MAX_DATA_PER_LINE 0x10000 65 #define EMMC_SDMA_BOUNDARY 512 * 1024 66 #define EMMC_SDMA_ROUND_UP(x, n) (((x) + n) & ~(n - 1)) 67 68 typedef enum { 69 EmmcCommandTypeBc, // Broadcast commands, no response 70 EmmcCommandTypeBcr, // Broadcast commands with response 71 EmmcCommandTypeAc, // Addressed(point-to-point) commands 72 EmmcCommandTypeAdtc // Addressed(point-to-point) data transfer commands 73 } EMMC_COMMAND_TYPE; 74 75 typedef enum { 76 EmmcResponceTypeR1, 77 EmmcResponceTypeR1b, 78 EmmcResponceTypeR2, 79 EmmcResponceTypeR3, 80 EmmcResponceTypeR4, 81 EmmcResponceTypeR5, 82 EmmcResponceTypeR5b, 83 EmmcResponceTypeR6, 84 EmmcResponceTypeR7 85 } EMMC_RESPONSE_TYPE; 86 87 typedef struct _EMMC_COMMAND_BLOCK { 88 UINT16 CommandIndex; 89 UINT32 CommandArgument; 90 UINT32 CommandType; // One of the EMMC_COMMAND_TYPE values 91 UINT32 ResponseType; // One of the EMMC_RESPONSE_TYPE values 92 } EMMC_COMMAND_BLOCK; 93 94 typedef struct _EMMC_STATUS_BLOCK { 95 UINT32 Resp0; 96 UINT32 Resp1; 97 UINT32 Resp2; 98 UINT32 Resp3; 99 } EMMC_STATUS_BLOCK; 100 101 typedef struct _EMMC_COMMAND_PACKET { 102 UINT64 Timeout; 103 EMMC_COMMAND_BLOCK *EmmcCmdBlk; 104 EMMC_STATUS_BLOCK *EmmcStatusBlk; 105 VOID *InDataBuffer; 106 VOID *OutDataBuffer; 107 UINT32 InTransferLength; 108 UINT32 OutTransferLength; 109 } EMMC_COMMAND_PACKET; 110 111 #pragma pack(1) 112 113 typedef struct { 114 UINT32 Valid:1; 115 UINT32 End:1; 116 UINT32 Int:1; 117 UINT32 Reserved:1; 118 UINT32 Act:2; 119 UINT32 Reserved1:10; 120 UINT32 Length:16; 121 UINT32 Address; 122 } EMMC_HC_ADMA_DESC_LINE; 123 124 typedef struct { 125 UINT32 TimeoutFreq:6; // bit 0:5 126 UINT32 Reserved:1; // bit 6 127 UINT32 TimeoutUnit:1; // bit 7 128 UINT32 BaseClkFreq:8; // bit 8:15 129 UINT32 MaxBlkLen:2; // bit 16:17 130 UINT32 BusWidth8:1; // bit 18 131 UINT32 Adma2:1; // bit 19 132 UINT32 Reserved2:1; // bit 20 133 UINT32 HighSpeed:1; // bit 21 134 UINT32 Sdma:1; // bit 22 135 UINT32 SuspRes:1; // bit 23 136 UINT32 Voltage33:1; // bit 24 137 UINT32 Voltage30:1; // bit 25 138 UINT32 Voltage18:1; // bit 26 139 UINT32 Reserved3:1; // bit 27 140 UINT32 SysBus64:1; // bit 28 141 UINT32 AsyncInt:1; // bit 29 142 UINT32 SlotType:2; // bit 30:31 143 UINT32 Sdr50:1; // bit 32 144 UINT32 Sdr104:1; // bit 33 145 UINT32 Ddr50:1; // bit 34 146 UINT32 Reserved4:1; // bit 35 147 UINT32 DriverTypeA:1; // bit 36 148 UINT32 DriverTypeC:1; // bit 37 149 UINT32 DriverTypeD:1; // bit 38 150 UINT32 DriverType4:1; // bit 39 151 UINT32 TimerCount:4; // bit 40:43 152 UINT32 Reserved5:1; // bit 44 153 UINT32 TuningSDR50:1; // bit 45 154 UINT32 RetuningMod:2; // bit 46:47 155 UINT32 ClkMultiplier:8; // bit 48:55 156 UINT32 Reserved6:7; // bit 56:62 157 UINT32 Hs400:1; // bit 63 158 } EMMC_HC_SLOT_CAP; 159 160 #pragma pack() 161 162 /** 163 Software reset the specified EMMC host controller and enable all interrupts. 164 165 @param[in] Bar The mmio base address of the slot to be accessed. 166 167 @retval EFI_SUCCESS The software reset executes successfully. 168 @retval Others The software reset fails. 169 170 **/ 171 EFI_STATUS 172 EmmcPeimHcReset ( 173 IN UINTN Bar 174 ); 175 176 /** 177 Set all interrupt status bits in Normal and Error Interrupt Status Enable 178 register. 179 180 @param[in] Bar The mmio base address of the slot to be accessed. 181 182 @retval EFI_SUCCESS The operation executes successfully. 183 @retval Others The operation fails. 184 185 **/ 186 EFI_STATUS 187 EmmcPeimHcEnableInterrupt ( 188 IN UINTN Bar 189 ); 190 191 /** 192 Get the capability data from the specified slot. 193 194 @param[in] Bar The mmio base address of the slot to be accessed. 195 @param[out] Capability The buffer to store the capability data. 196 197 @retval EFI_SUCCESS The operation executes successfully. 198 @retval Others The operation fails. 199 200 **/ 201 EFI_STATUS 202 EmmcPeimHcGetCapability ( 203 IN UINTN Bar, 204 OUT EMMC_HC_SLOT_CAP *Capability 205 ); 206 207 /** 208 Detect whether there is a EMMC card attached at the specified EMMC host controller 209 slot. 210 211 Refer to SD Host Controller Simplified spec 3.0 Section 3.1 for details. 212 213 @param[in] Bar The mmio base address of the slot to be accessed. 214 215 @retval EFI_SUCCESS There is a EMMC card attached. 216 @retval EFI_NO_MEDIA There is not a EMMC card attached. 217 @retval Others The detection fails. 218 219 **/ 220 EFI_STATUS 221 EmmcPeimHcCardDetect ( 222 IN UINTN Bar 223 ); 224 225 /** 226 Initial EMMC host controller with lowest clock frequency, max power and max timeout value 227 at initialization. 228 make_partition_pruneinfo(PlannerInfo * root,RelOptInfo * parentrel,List * subpaths,List * partitioned_rels,List * prunequal)229 @param[in] Bar The mmio base address of the slot to be accessed. 230 231 @retval EFI_SUCCESS The host controller is initialized successfully. 232 @retval Others The host controller isn't initialized successfully. 233 234 **/ 235 EFI_STATUS 236 EmmcPeimHcInitHost ( 237 IN UINTN Bar 238 ); 239 240 /** 241 Send command SWITCH to the EMMC device to switch the mode of operation of the 242 selected Device or modifies the EXT_CSD registers. 243 244 Refer to EMMC Electrical Standard Spec 5.1 Section 6.10.4 for details. 245 246 @param[in] Slot The slot number of the Emmc card to send the command to. 247 @param[in] Access The access mode of SWITCH command. 248 @param[in] Index The offset of the field to be access. 249 @param[in] Value The value to be set to the specified field of EXT_CSD register. 250 @param[in] CmdSet The value of CmdSet field of EXT_CSD register. 251 252 @retval EFI_SUCCESS The operation is done correctly. 253 @retval Others The operation fails. 254 255 **/ 256 EFI_STATUS 257 EmmcPeimSwitch ( 258 IN EMMC_PEIM_HC_SLOT *Slot, 259 IN UINT8 Access, 260 IN UINT8 Index, 261 IN UINT8 Value, 262 IN UINT8 CmdSet 263 ); 264 265 /** 266 Send command SET_BLOCK_COUNT to the addressed EMMC device to set the number of 267 blocks for the following block read/write cmd. 268 269 Refer to EMMC Electrical Standard Spec 5.1 Section 6.10.4 for details. 270 271 @param[in] Slot The slot number of the Emmc card to send the command to. 272 @param[in] BlockCount The number of the logical block to access. 273 274 @retval EFI_SUCCESS The operation is done correctly. 275 @retval Others The operation fails. 276 277 **/ 278 EFI_STATUS 279 EmmcPeimSetBlkCount ( 280 IN EMMC_PEIM_HC_SLOT *Slot, 281 IN UINT16 BlockCount 282 ); 283 284 /** 285 Send command READ_MULTIPLE_BLOCK/WRITE_MULTIPLE_BLOCK to the addressed EMMC device 286 to read/write the specified number of blocks. 287 288 Refer to EMMC Electrical Standard Spec 5.1 Section 6.10.4 for details. 289 290 @param[in] Slot The slot number of the Emmc card to send the command to. 291 @param[in] Lba The logical block address of starting access. 292 @param[in] BlockSize The block size of specified EMMC device partition. 293 @param[in] Buffer The pointer to the transfer buffer. 294 @param[in] BufferSize The size of transfer buffer. 295 @param[in] IsRead Boolean to show the operation direction. 296 297 @retval EFI_SUCCESS The operation is done correctly. 298 @retval Others The operation fails. 299 300 **/ 301 EFI_STATUS 302 EmmcPeimRwMultiBlocks ( 303 IN EMMC_PEIM_HC_SLOT *Slot, 304 IN EFI_LBA Lba, 305 IN UINT32 BlockSize, 306 IN VOID *Buffer, 307 IN UINTN BufferSize, 308 IN BOOLEAN IsRead 309 ); 310 311 /** 312 Execute EMMC device identification procedure. 313 314 Refer to EMMC Electrical Standard Spec 5.1 Section 6.4 for details. 315 316 @param[in] Slot The slot number of the Emmc card to send the command to. 317 318 @retval EFI_SUCCESS There is a EMMC card. 319 @retval Others There is not a EMMC card. 320 321 **/ 322 EFI_STATUS 323 EmmcPeimIdentification ( 324 IN EMMC_PEIM_HC_SLOT *Slot 325 ); 326 327 /** 328 Free the resource used by the TRB. 329 330 @param[in] Trb The pointer to the EMMC_TRB instance. 331 332 **/ 333 VOID 334 EmmcPeimFreeTrb ( 335 IN EMMC_TRB *Trb 336 ); 337 338 #endif 339 340