1 /** @file 2 MSR Definitions for Intel processors based on the Ivy Bridge microarchitecture. 3 4 Provides defines for Machine Specific Registers(MSR) indexes. Data structures 5 are provided for MSRs that contain one or more bit fields. If the MSR value 6 returned is a single 32-bit or 64-bit value, then a data structure is not 7 provided for that MSR. 8 9 Copyright (c) 2016 - 2019, Intel Corporation. All rights reserved.<BR> 10 SPDX-License-Identifier: BSD-2-Clause-Patent 11 12 @par Specification Reference: 13 Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 4, 14 May 2018, Volume 4: Model-Specific-Registers (MSR) 15 16 **/ 17 18 #ifndef __IVY_BRIDGE_MSR_H__ 19 #define __IVY_BRIDGE_MSR_H__ 20 21 #include <Register/Intel/ArchitecturalMsr.h> 22 23 /** 24 Is Intel processors based on the Ivy Bridge microarchitecture? 25 26 @param DisplayFamily Display Family ID 27 @param DisplayModel Display Model ID 28 29 @retval TRUE Yes, it is. 30 @retval FALSE No, it isn't. 31 **/ 32 #define IS_IVY_BRIDGE_PROCESSOR(DisplayFamily, DisplayModel) \ 33 (DisplayFamily == 0x06 && \ 34 ( \ 35 DisplayModel == 0x3A || \ 36 DisplayModel == 0x3E \ 37 ) \ 38 ) 39 40 /** 41 Package. See http://biosbits.org. 42 43 @param ECX MSR_IVY_BRIDGE_PLATFORM_INFO (0x000000CE) 44 @param EAX Lower 32-bits of MSR value. 45 Described by the type MSR_IVY_BRIDGE_PLATFORM_INFO_REGISTER. 46 @param EDX Upper 32-bits of MSR value. 47 Described by the type MSR_IVY_BRIDGE_PLATFORM_INFO_REGISTER. 48 49 <b>Example usage</b> 50 @code 51 MSR_IVY_BRIDGE_PLATFORM_INFO_REGISTER Msr; 52 53 Msr.Uint64 = AsmReadMsr64 (MSR_IVY_BRIDGE_PLATFORM_INFO); 54 AsmWriteMsr64 (MSR_IVY_BRIDGE_PLATFORM_INFO, Msr.Uint64); 55 @endcode 56 @note MSR_IVY_BRIDGE_PLATFORM_INFO is defined as MSR_PLATFORM_INFO in SDM. 57 **/ 58 #define MSR_IVY_BRIDGE_PLATFORM_INFO 0x000000CE 59 60 /** 61 MSR information returned for MSR index #MSR_IVY_BRIDGE_PLATFORM_INFO 62 **/ 63 typedef union { 64 /// 65 /// Individual bit fields 66 /// 67 struct { 68 UINT32 Reserved1:8; 69 /// 70 /// [Bits 15:8] Package. Maximum Non-Turbo Ratio (R/O) The is the ratio 71 /// of the frequency that invariant TSC runs at. Frequency = ratio * 100 72 /// MHz. 73 /// 74 UINT32 MaximumNonTurboRatio:8; 75 UINT32 Reserved2:12; 76 /// 77 /// [Bit 28] Package. Programmable Ratio Limit for Turbo Mode (R/O) When 78 /// set to 1, indicates that Programmable Ratio Limits for Turbo mode is 79 /// enabled, and when set to 0, indicates Programmable Ratio Limits for 80 /// Turbo mode is disabled. 81 /// 82 UINT32 RatioLimit:1; 83 /// 84 /// [Bit 29] Package. Programmable TDP Limit for Turbo Mode (R/O) When 85 /// set to 1, indicates that TDP Limits for Turbo mode are programmable, 86 /// and when set to 0, indicates TDP Limit for Turbo mode is not 87 /// programmable. 88 /// 89 UINT32 TDPLimit:1; 90 UINT32 Reserved3:2; 91 /// 92 /// [Bit 32] Package. Low Power Mode Support (LPM) (R/O) When set to 1, 93 /// indicates that LPM is supported, and when set to 0, indicates LPM is 94 /// not supported. 95 /// 96 UINT32 LowPowerModeSupport:1; 97 /// 98 /// [Bits 34:33] Package. Number of ConfigTDP Levels (R/O) 00: Only Base 99 /// TDP level available. 01: One additional TDP level available. 02: Two 100 /// additional TDP level available. 11: Reserved. 101 /// 102 UINT32 ConfigTDPLevels:2; 103 UINT32 Reserved4:5; 104 /// 105 /// [Bits 47:40] Package. Maximum Efficiency Ratio (R/O) The is the 106 /// minimum ratio (maximum efficiency) that the processor can operates, in 107 /// units of 100MHz. 108 /// 109 UINT32 MaximumEfficiencyRatio:8; 110 /// 111 /// [Bits 55:48] Package. Minimum Operating Ratio (R/O) Contains the 112 /// minimum supported operating ratio in units of 100 MHz. 113 /// 114 UINT32 MinimumOperatingRatio:8; 115 UINT32 Reserved5:8; 116 } Bits; 117 /// 118 /// All bit fields as a 64-bit value 119 /// 120 UINT64 Uint64; 121 } MSR_IVY_BRIDGE_PLATFORM_INFO_REGISTER; 122 123 124 /** 125 Core. C-State Configuration Control (R/W) Note: C-state values are 126 processor specific C-state code names, unrelated to MWAIT extension C-state 127 parameters or ACPI C-States. See http://biosbits.org. 128 129 @param ECX MSR_IVY_BRIDGE_PKG_CST_CONFIG_CONTROL (0x000000E2) 130 @param EAX Lower 32-bits of MSR value. 131 Described by the type MSR_IVY_BRIDGE_PKG_CST_CONFIG_CONTROL_REGISTER. 132 @param EDX Upper 32-bits of MSR value. 133 Described by the type MSR_IVY_BRIDGE_PKG_CST_CONFIG_CONTROL_REGISTER. 134 135 <b>Example usage</b> 136 @code 137 MSR_IVY_BRIDGE_PKG_CST_CONFIG_CONTROL_REGISTER Msr; 138 139 Msr.Uint64 = AsmReadMsr64 (MSR_IVY_BRIDGE_PKG_CST_CONFIG_CONTROL); 140 AsmWriteMsr64 (MSR_IVY_BRIDGE_PKG_CST_CONFIG_CONTROL, Msr.Uint64); 141 @endcode 142 @note MSR_IVY_BRIDGE_PKG_CST_CONFIG_CONTROL is defined as MSR_PKG_CST_CONFIG_CONTROL in SDM. 143 **/ 144 #define MSR_IVY_BRIDGE_PKG_CST_CONFIG_CONTROL 0x000000E2 145 146 /** 147 MSR information returned for MSR index #MSR_IVY_BRIDGE_PKG_CST_CONFIG_CONTROL 148 **/ 149 typedef union { 150 /// 151 /// Individual bit fields 152 /// 153 struct { 154 /// 155 /// [Bits 2:0] Package C-State Limit (R/W) Specifies the lowest 156 /// processor-specific C-state code name (consuming the least power). for 157 /// the package. The default is set as factory-configured package C-state 158 /// limit. The following C-state code name encodings are supported: 000b: 159 /// C0/C1 (no package C-sate support) 001b: C2 010b: C6 no retention 011b: 160 /// C6 retention 100b: C7 101b: C7s 111: No package C-state limit. Note: 161 /// This field cannot be used to limit package C-state to C3. 162 /// 163 UINT32 Limit:3; 164 UINT32 Reserved1:7; 165 /// 166 /// [Bit 10] I/O MWAIT Redirection Enable (R/W) When set, will map 167 /// IO_read instructions sent to IO register specified by 168 /// MSR_PMG_IO_CAPTURE_BASE to MWAIT instructions. 169 /// 170 UINT32 IO_MWAIT:1; 171 UINT32 Reserved2:4; 172 /// 173 /// [Bit 15] CFG Lock (R/WO) When set, lock bits 15:0 of this register 174 /// until next reset. 175 /// 176 UINT32 CFGLock:1; 177 UINT32 Reserved3:9; 178 /// 179 /// [Bit 25] C3 state auto demotion enable (R/W) When set, the processor 180 /// will conditionally demote C6/C7 requests to C3 based on uncore 181 /// auto-demote information. 182 /// 183 UINT32 C3AutoDemotion:1; 184 /// 185 /// [Bit 26] C1 state auto demotion enable (R/W) When set, the processor 186 /// will conditionally demote C3/C6/C7 requests to C1 based on uncore 187 /// auto-demote information. 188 /// 189 UINT32 C1AutoDemotion:1; 190 /// 191 /// [Bit 27] Enable C3 undemotion (R/W) When set, enables undemotion from 192 /// demoted C3. 193 /// 194 UINT32 C3Undemotion:1; 195 /// 196 /// [Bit 28] Enable C1 undemotion (R/W) When set, enables undemotion from 197 /// demoted C1. 198 /// 199 UINT32 C1Undemotion:1; 200 UINT32 Reserved4:3; 201 UINT32 Reserved5:32; 202 } Bits; 203 /// 204 /// All bit fields as a 32-bit value 205 /// 206 UINT32 Uint32; 207 /// 208 /// All bit fields as a 64-bit value 209 /// 210 UINT64 Uint64; 211 } MSR_IVY_BRIDGE_PKG_CST_CONFIG_CONTROL_REGISTER; 212 213 214 /** 215 Package. PP0 Energy Status (R/O) See Section 14.9.4, "PP0/PP1 RAPL 216 Domains.". 217 218 @param ECX MSR_IVY_BRIDGE_PP0_ENERGY_STATUS (0x00000639) 219 @param EAX Lower 32-bits of MSR value. 220 @param EDX Upper 32-bits of MSR value. 221 222 <b>Example usage</b> 223 @code 224 UINT64 Msr; 225 226 Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_PP0_ENERGY_STATUS); 227 @endcode 228 @note MSR_IVY_BRIDGE_PP0_ENERGY_STATUS is defined as MSR_PP0_ENERGY_STATUS in SDM. 229 **/ 230 #define MSR_IVY_BRIDGE_PP0_ENERGY_STATUS 0x00000639 231 232 233 /** 234 Package. Base TDP Ratio (R/O). 235 236 @param ECX MSR_IVY_BRIDGE_CONFIG_TDP_NOMINAL (0x00000648) 237 @param EAX Lower 32-bits of MSR value. 238 Described by the type MSR_IVY_BRIDGE_CONFIG_TDP_NOMINAL_REGISTER. 239 @param EDX Upper 32-bits of MSR value. 240 Described by the type MSR_IVY_BRIDGE_CONFIG_TDP_NOMINAL_REGISTER. 241 242 <b>Example usage</b> 243 @code 244 MSR_IVY_BRIDGE_CONFIG_TDP_NOMINAL_REGISTER Msr; 245 246 Msr.Uint64 = AsmReadMsr64 (MSR_IVY_BRIDGE_CONFIG_TDP_NOMINAL); 247 @endcode 248 @note MSR_IVY_BRIDGE_CONFIG_TDP_NOMINAL is defined as MSR_CONFIG_TDP_NOMINAL in SDM. 249 **/ 250 #define MSR_IVY_BRIDGE_CONFIG_TDP_NOMINAL 0x00000648 251 252 /** 253 MSR information returned for MSR index #MSR_IVY_BRIDGE_CONFIG_TDP_NOMINAL 254 **/ 255 typedef union { 256 /// 257 /// Individual bit fields 258 /// 259 struct { 260 /// 261 /// [Bits 7:0] Config_TDP_Base Base TDP level ratio to be used for this 262 /// specific processor (in units of 100 MHz). 263 /// 264 UINT32 Config_TDP_Base:8; 265 UINT32 Reserved1:24; 266 UINT32 Reserved2:32; 267 } Bits; 268 /// 269 /// All bit fields as a 32-bit value 270 /// 271 UINT32 Uint32; 272 /// 273 /// All bit fields as a 64-bit value 274 /// 275 UINT64 Uint64; 276 } MSR_IVY_BRIDGE_CONFIG_TDP_NOMINAL_REGISTER; 277 278 279 /** 280 Package. ConfigTDP Level 1 ratio and power level (R/O). 281 282 @param ECX MSR_IVY_BRIDGE_CONFIG_TDP_LEVEL1 (0x00000649) 283 @param EAX Lower 32-bits of MSR value. 284 Described by the type MSR_IVY_BRIDGE_CONFIG_TDP_LEVEL1_REGISTER. 285 @param EDX Upper 32-bits of MSR value. 286 Described by the type MSR_IVY_BRIDGE_CONFIG_TDP_LEVEL1_REGISTER. 287 288 <b>Example usage</b> 289 @code 290 MSR_IVY_BRIDGE_CONFIG_TDP_LEVEL1_REGISTER Msr; 291 292 Msr.Uint64 = AsmReadMsr64 (MSR_IVY_BRIDGE_CONFIG_TDP_LEVEL1); 293 @endcode 294 @note MSR_IVY_BRIDGE_CONFIG_TDP_LEVEL1 is defined as MSR_CONFIG_TDP_LEVEL1 in SDM. 295 **/ 296 #define MSR_IVY_BRIDGE_CONFIG_TDP_LEVEL1 0x00000649 297 298 /** 299 MSR information returned for MSR index #MSR_IVY_BRIDGE_CONFIG_TDP_LEVEL1 300 **/ 301 typedef union { 302 /// 303 /// Individual bit fields 304 /// 305 struct { 306 /// 307 /// [Bits 14:0] PKG_TDP_LVL1. Power setting for ConfigTDP Level 1. 308 /// 309 UINT32 PKG_TDP_LVL1:15; 310 UINT32 Reserved1:1; 311 /// 312 /// [Bits 23:16] Config_TDP_LVL1_Ratio. ConfigTDP level 1 ratio to be used 313 /// for this specific processor. 314 /// 315 UINT32 Config_TDP_LVL1_Ratio:8; 316 UINT32 Reserved2:8; 317 /// 318 /// [Bits 46:32] PKG_MAX_PWR_LVL1. Max Power setting allowed for ConfigTDP 319 /// Level 1. 320 /// 321 UINT32 PKG_MAX_PWR_LVL1:15; 322 UINT32 Reserved3:1; 323 /// 324 /// [Bits 62:48] PKG_MIN_PWR_LVL1. MIN Power setting allowed for ConfigTDP 325 /// Level 1. 326 /// 327 UINT32 PKG_MIN_PWR_LVL1:15; 328 UINT32 Reserved4:1; 329 } Bits; 330 /// 331 /// All bit fields as a 64-bit value 332 /// 333 UINT64 Uint64; 334 } MSR_IVY_BRIDGE_CONFIG_TDP_LEVEL1_REGISTER; 335 336 337 /** 338 Package. ConfigTDP Level 2 ratio and power level (R/O). 339 340 @param ECX MSR_IVY_BRIDGE_CONFIG_TDP_LEVEL2 (0x0000064A) 341 @param EAX Lower 32-bits of MSR value. 342 Described by the type MSR_IVY_BRIDGE_CONFIG_TDP_LEVEL2_REGISTER. 343 @param EDX Upper 32-bits of MSR value. 344 Described by the type MSR_IVY_BRIDGE_CONFIG_TDP_LEVEL2_REGISTER. 345 346 <b>Example usage</b> 347 @code 348 MSR_IVY_BRIDGE_CONFIG_TDP_LEVEL2_REGISTER Msr; 349 350 Msr.Uint64 = AsmReadMsr64 (MSR_IVY_BRIDGE_CONFIG_TDP_LEVEL2); 351 @endcode 352 @note MSR_IVY_BRIDGE_CONFIG_TDP_LEVEL2 is defined as MSR_CONFIG_TDP_LEVEL2 in SDM. 353 **/ 354 #define MSR_IVY_BRIDGE_CONFIG_TDP_LEVEL2 0x0000064A 355 356 /** 357 MSR information returned for MSR index #MSR_IVY_BRIDGE_CONFIG_TDP_LEVEL2 358 **/ 359 typedef union { 360 /// 361 /// Individual bit fields 362 /// 363 struct { 364 /// 365 /// [Bits 14:0] PKG_TDP_LVL2. Power setting for ConfigTDP Level 2. 366 /// 367 UINT32 PKG_TDP_LVL2:15; 368 UINT32 Reserved1:1; 369 /// 370 /// [Bits 23:16] Config_TDP_LVL2_Ratio. ConfigTDP level 2 ratio to be used 371 /// for this specific processor. 372 /// 373 UINT32 Config_TDP_LVL2_Ratio:8; 374 UINT32 Reserved2:8; 375 /// 376 /// [Bits 46:32] PKG_MAX_PWR_LVL2. Max Power setting allowed for ConfigTDP 377 /// Level 2. 378 /// 379 UINT32 PKG_MAX_PWR_LVL2:15; 380 UINT32 Reserved3:1; 381 /// 382 /// [Bits 62:48] PKG_MIN_PWR_LVL2. MIN Power setting allowed for ConfigTDP 383 /// Level 2. 384 /// 385 UINT32 PKG_MIN_PWR_LVL2:15; 386 UINT32 Reserved4:1; 387 } Bits; 388 /// 389 /// All bit fields as a 64-bit value 390 /// 391 UINT64 Uint64; 392 } MSR_IVY_BRIDGE_CONFIG_TDP_LEVEL2_REGISTER; 393 394 395 /** 396 Package. ConfigTDP Control (R/W). 397 398 @param ECX MSR_IVY_BRIDGE_CONFIG_TDP_CONTROL (0x0000064B) 399 @param EAX Lower 32-bits of MSR value. 400 Described by the type MSR_IVY_BRIDGE_CONFIG_TDP_CONTROL_REGISTER. 401 @param EDX Upper 32-bits of MSR value. 402 Described by the type MSR_IVY_BRIDGE_CONFIG_TDP_CONTROL_REGISTER. 403 404 <b>Example usage</b> 405 @code 406 MSR_IVY_BRIDGE_CONFIG_TDP_CONTROL_REGISTER Msr; 407 408 Msr.Uint64 = AsmReadMsr64 (MSR_IVY_BRIDGE_CONFIG_TDP_CONTROL); 409 AsmWriteMsr64 (MSR_IVY_BRIDGE_CONFIG_TDP_CONTROL, Msr.Uint64); 410 @endcode 411 @note MSR_IVY_BRIDGE_CONFIG_TDP_CONTROL is defined as MSR_CONFIG_TDP_CONTROL in SDM. 412 **/ 413 #define MSR_IVY_BRIDGE_CONFIG_TDP_CONTROL 0x0000064B 414 415 /** 416 MSR information returned for MSR index #MSR_IVY_BRIDGE_CONFIG_TDP_CONTROL 417 **/ 418 typedef union { 419 /// 420 /// Individual bit fields 421 /// 422 struct { 423 /// 424 /// [Bits 1:0] TDP_LEVEL (RW/L) System BIOS can program this field. 425 /// 426 UINT32 TDP_LEVEL:2; 427 UINT32 Reserved1:29; 428 /// 429 /// [Bit 31] Config_TDP_Lock (RW/L) When this bit is set, the content of 430 /// this register is locked until a reset. 431 /// 432 UINT32 Config_TDP_Lock:1; 433 UINT32 Reserved2:32; 434 } Bits; 435 /// 436 /// All bit fields as a 32-bit value 437 /// 438 UINT32 Uint32; 439 /// 440 /// All bit fields as a 64-bit value 441 /// 442 UINT64 Uint64; 443 } MSR_IVY_BRIDGE_CONFIG_TDP_CONTROL_REGISTER; 444 445 446 /** 447 Package. ConfigTDP Control (R/W). 448 449 @param ECX MSR_IVY_BRIDGE_TURBO_ACTIVATION_RATIO (0x0000064C) 450 @param EAX Lower 32-bits of MSR value. 451 Described by the type MSR_IVY_BRIDGE_TURBO_ACTIVATION_RATIO_REGISTER. 452 @param EDX Upper 32-bits of MSR value. 453 Described by the type MSR_IVY_BRIDGE_TURBO_ACTIVATION_RATIO_REGISTER. 454 455 <b>Example usage</b> 456 @code 457 MSR_IVY_BRIDGE_TURBO_ACTIVATION_RATIO_REGISTER Msr; 458 459 Msr.Uint64 = AsmReadMsr64 (MSR_IVY_BRIDGE_TURBO_ACTIVATION_RATIO); 460 AsmWriteMsr64 (MSR_IVY_BRIDGE_TURBO_ACTIVATION_RATIO, Msr.Uint64); 461 @endcode 462 @note MSR_IVY_BRIDGE_TURBO_ACTIVATION_RATIO is defined as MSR_TURBO_ACTIVATION_RATIO in SDM. 463 **/ 464 #define MSR_IVY_BRIDGE_TURBO_ACTIVATION_RATIO 0x0000064C 465 466 /** 467 MSR information returned for MSR index #MSR_IVY_BRIDGE_TURBO_ACTIVATION_RATIO 468 **/ 469 typedef union { 470 /// 471 /// Individual bit fields 472 /// 473 struct { 474 /// 475 /// [Bits 7:0] MAX_NON_TURBO_RATIO (RW/L) System BIOS can program this 476 /// field. 477 /// 478 UINT32 MAX_NON_TURBO_RATIO:8; 479 UINT32 Reserved1:23; 480 /// 481 /// [Bit 31] TURBO_ACTIVATION_RATIO_Lock (RW/L) When this bit is set, the 482 /// content of this register is locked until a reset. 483 /// 484 UINT32 TURBO_ACTIVATION_RATIO_Lock:1; 485 UINT32 Reserved2:32; 486 } Bits; 487 /// 488 /// All bit fields as a 32-bit value 489 /// 490 UINT32 Uint32; 491 /// 492 /// All bit fields as a 64-bit value 493 /// 494 UINT64 Uint64; 495 } MSR_IVY_BRIDGE_TURBO_ACTIVATION_RATIO_REGISTER; 496 497 498 /** 499 Package. Protected Processor Inventory Number Enable Control (R/W). 500 501 @param ECX MSR_IVY_BRIDGE_PPIN_CTL (0x0000004E) 502 @param EAX Lower 32-bits of MSR value. 503 Described by the type MSR_IVY_BRIDGE_PPIN_CTL_REGISTER. 504 @param EDX Upper 32-bits of MSR value. 505 Described by the type MSR_IVY_BRIDGE_PPIN_CTL_REGISTER. 506 507 <b>Example usage</b> 508 @code 509 MSR_IVY_BRIDGE_PPIN_CTL_REGISTER Msr; 510 511 Msr.Uint64 = AsmReadMsr64 (MSR_IVY_BRIDGE_PPIN_CTL); 512 AsmWriteMsr64 (MSR_IVY_BRIDGE_PPIN_CTL, Msr.Uint64); 513 @endcode 514 @note MSR_IVY_BRIDGE_PPIN_CTL is defined as MSR_PPIN_CTL in SDM. 515 **/ 516 #define MSR_IVY_BRIDGE_PPIN_CTL 0x0000004E 517 518 /** 519 MSR information returned for MSR index #MSR_IVY_BRIDGE_PPIN_CTL 520 **/ 521 typedef union { 522 /// 523 /// Individual bit fields 524 /// 525 struct { 526 /// 527 /// [Bit 0] LockOut (R/WO) Set 1to prevent further writes to MSR_PPIN_CTL. 528 /// Writing 1 to MSR_PPINCTL[bit 0] is permitted only if MSR_PPIN_CTL[bit 529 /// 1] is clear, Default is 0. BIOS should provide an opt-in menu to 530 /// enable the user to turn on MSR_PPIN_CTL[bit 1] for privileged 531 /// inventory initialization agent to access MSR_PPIN. After reading 532 /// MSR_PPIN, the privileged inventory initialization agent should write 533 /// '01b' to MSR_PPIN_CTL to disable further access to MSR_PPIN and 534 /// prevent unauthorized modification to MSR_PPIN_CTL. 535 /// 536 UINT32 LockOut:1; 537 /// 538 /// [Bit 1] Enable_PPIN (R/W) If 1, enables MSR_PPIN to be accessible 539 /// using RDMSR. Once set, attempt to write 1 to MSR_PPIN_CTL[bit 0] will 540 /// cause #GP. If 0, an attempt to read MSR_PPIN will cause #GP. Default 541 /// is 0. 542 /// 543 UINT32 Enable_PPIN:1; 544 UINT32 Reserved1:30; 545 UINT32 Reserved2:32; 546 } Bits; 547 /// 548 /// All bit fields as a 32-bit value 549 /// 550 UINT32 Uint32; 551 /// 552 /// All bit fields as a 64-bit value 553 /// 554 UINT64 Uint64; 555 } MSR_IVY_BRIDGE_PPIN_CTL_REGISTER; 556 557 558 /** 559 Package. Protected Processor Inventory Number (R/O). Protected Processor 560 Inventory Number (R/O) A unique value within a given CPUID 561 family/model/stepping signature that a privileged inventory initialization 562 agent can access to identify each physical processor, when access to 563 MSR_PPIN is enabled. Access to MSR_PPIN is permitted only if 564 MSR_PPIN_CTL[bits 1:0] = '10b'. 565 566 @param ECX MSR_IVY_BRIDGE_PPIN (0x0000004F) 567 @param EAX Lower 32-bits of MSR value. 568 @param EDX Upper 32-bits of MSR value. 569 570 <b>Example usage</b> 571 @code 572 UINT64 Msr; 573 574 Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_PPIN); 575 @endcode 576 @note MSR_IVY_BRIDGE_PPIN is defined as MSR_PPIN in SDM. 577 **/ 578 #define MSR_IVY_BRIDGE_PPIN 0x0000004F 579 580 581 /** 582 Package. See http://biosbits.org. 583 584 @param ECX MSR_IVY_BRIDGE_PLATFORM_INFO_1 (0x000000CE) 585 @param EAX Lower 32-bits of MSR value. 586 Described by the type MSR_IVY_BRIDGE_PLATFORM_INFO_1_REGISTER. 587 @param EDX Upper 32-bits of MSR value. 588 Described by the type MSR_IVY_BRIDGE_PLATFORM_INFO_1_REGISTER. 589 590 <b>Example usage</b> 591 @code 592 MSR_IVY_BRIDGE_PLATFORM_INFO_1_REGISTER Msr; 593 594 Msr.Uint64 = AsmReadMsr64 (MSR_IVY_BRIDGE_PLATFORM_INFO_1); 595 AsmWriteMsr64 (MSR_IVY_BRIDGE_PLATFORM_INFO_1, Msr.Uint64); 596 @endcode 597 @note MSR_IVY_BRIDGE_PLATFORM_INFO_1 is defined as MSR_PLATFORM_INFO_1 in SDM. 598 **/ 599 #define MSR_IVY_BRIDGE_PLATFORM_INFO_1 0x000000CE 600 601 /** 602 MSR information returned for MSR index #MSR_IVY_BRIDGE_PLATFORM_INFO_1 603 **/ 604 typedef union { 605 /// 606 /// Individual bit fields 607 /// 608 struct { 609 UINT32 Reserved1:8; 610 /// 611 /// [Bits 15:8] Package. Maximum Non-Turbo Ratio (R/O) The is the ratio 612 /// of the frequency that invariant TSC runs at. Frequency = ratio * 100 613 /// MHz. 614 /// 615 UINT32 MaximumNonTurboRatio:8; 616 UINT32 Reserved2:7; 617 /// 618 /// [Bit 23] Package. PPIN_CAP (R/O) When set to 1, indicates that 619 /// Protected Processor Inventory Number (PPIN) capability can be enabled 620 /// for privileged system inventory agent to read PPIN from MSR_PPIN. When 621 /// set to 0, PPIN capability is not supported. An attempt to access 622 /// MSR_PPIN_CTL or MSR_PPIN will cause #GP. 623 /// 624 UINT32 PPIN_CAP:1; 625 UINT32 Reserved3:4; 626 /// 627 /// [Bit 28] Package. Programmable Ratio Limit for Turbo Mode (R/O) When 628 /// set to 1, indicates that Programmable Ratio Limits for Turbo mode is 629 /// enabled, and when set to 0, indicates Programmable Ratio Limits for 630 /// Turbo mode is disabled. 631 /// 632 UINT32 RatioLimit:1; 633 /// 634 /// [Bit 29] Package. Programmable TDP Limit for Turbo Mode (R/O) When 635 /// set to 1, indicates that TDP Limits for Turbo mode are programmable, 636 /// and when set to 0, indicates TDP Limit for Turbo mode is not 637 /// programmable. 638 /// 639 UINT32 TDPLimit:1; 640 /// 641 /// [Bit 30] Package. Programmable TJ OFFSET (R/O) When set to 1, 642 /// indicates that MSR_TEMPERATURE_TARGET.[27:24] is valid and writable to 643 /// specify an temperature offset. 644 /// 645 UINT32 TJOFFSET:1; 646 UINT32 Reserved4:1; 647 UINT32 Reserved5:8; 648 /// 649 /// [Bits 47:40] Package. Maximum Efficiency Ratio (R/O) The is the 650 /// minimum ratio (maximum efficiency) that the processor can operates, in 651 /// units of 100MHz. 652 /// 653 UINT32 MaximumEfficiencyRatio:8; 654 UINT32 Reserved6:16; 655 } Bits; 656 /// 657 /// All bit fields as a 64-bit value 658 /// 659 UINT64 Uint64; 660 } MSR_IVY_BRIDGE_PLATFORM_INFO_1_REGISTER; 661 662 663 /** 664 Package. MC Bank Error Configuration (R/W). 665 666 @param ECX MSR_IVY_BRIDGE_ERROR_CONTROL (0x0000017F) 667 @param EAX Lower 32-bits of MSR value. 668 Described by the type MSR_IVY_BRIDGE_ERROR_CONTROL_REGISTER. 669 @param EDX Upper 32-bits of MSR value. 670 Described by the type MSR_IVY_BRIDGE_ERROR_CONTROL_REGISTER. 671 672 <b>Example usage</b> 673 @code 674 MSR_IVY_BRIDGE_ERROR_CONTROL_REGISTER Msr; 675 676 Msr.Uint64 = AsmReadMsr64 (MSR_IVY_BRIDGE_ERROR_CONTROL); 677 AsmWriteMsr64 (MSR_IVY_BRIDGE_ERROR_CONTROL, Msr.Uint64); 678 @endcode 679 @note MSR_IVY_BRIDGE_ERROR_CONTROL is defined as MSR_ERROR_CONTROL in SDM. 680 **/ 681 #define MSR_IVY_BRIDGE_ERROR_CONTROL 0x0000017F 682 683 /** 684 MSR information returned for MSR index #MSR_IVY_BRIDGE_ERROR_CONTROL 685 **/ 686 typedef union { 687 /// 688 /// Individual bit fields 689 /// 690 struct { 691 UINT32 Reserved1:1; 692 /// 693 /// [Bit 1] MemError Log Enable (R/W) When set, enables IMC status bank 694 /// to log additional info in bits 36:32. 695 /// 696 UINT32 MemErrorLogEnable:1; 697 UINT32 Reserved2:30; 698 UINT32 Reserved3:32; 699 } Bits; 700 /// 701 /// All bit fields as a 32-bit value 702 /// 703 UINT32 Uint32; 704 /// 705 /// All bit fields as a 64-bit value 706 /// 707 UINT64 Uint64; 708 } MSR_IVY_BRIDGE_ERROR_CONTROL_REGISTER; 709 710 711 /** 712 Package. 713 714 @param ECX MSR_IVY_BRIDGE_TEMPERATURE_TARGET (0x000001A2) 715 @param EAX Lower 32-bits of MSR value. 716 Described by the type MSR_IVY_BRIDGE_TEMPERATURE_TARGET_REGISTER. 717 @param EDX Upper 32-bits of MSR value. 718 Described by the type MSR_IVY_BRIDGE_TEMPERATURE_TARGET_REGISTER. 719 720 <b>Example usage</b> 721 @code 722 MSR_IVY_BRIDGE_TEMPERATURE_TARGET_REGISTER Msr; 723 724 Msr.Uint64 = AsmReadMsr64 (MSR_IVY_BRIDGE_TEMPERATURE_TARGET); 725 AsmWriteMsr64 (MSR_IVY_BRIDGE_TEMPERATURE_TARGET, Msr.Uint64); 726 @endcode 727 @note MSR_IVY_BRIDGE_TEMPERATURE_TARGET is defined as MSR_TEMPERATURE_TARGET in SDM. 728 **/ 729 #define MSR_IVY_BRIDGE_TEMPERATURE_TARGET 0x000001A2 730 731 /** 732 MSR information returned for MSR index #MSR_IVY_BRIDGE_TEMPERATURE_TARGET 733 **/ 734 typedef union { 735 /// 736 /// Individual bit fields 737 /// 738 struct { 739 UINT32 Reserved1:16; 740 /// 741 /// [Bits 23:16] Temperature Target (RO) The minimum temperature at which 742 /// PROCHOT# will be asserted. The value is degree C. 743 /// 744 UINT32 TemperatureTarget:8; 745 /// 746 /// [Bits 27:24] TCC Activation Offset (R/W) Specifies a temperature 747 /// offset in degrees C from the temperature target (bits 23:16). PROCHOT# 748 /// will assert at the offset target temperature. Write is permitted only 749 /// MSR_PLATFORM_INFO.[30] is set. 750 /// 751 UINT32 TCCActivationOffset:4; 752 UINT32 Reserved2:4; 753 UINT32 Reserved3:32; 754 } Bits; 755 /// 756 /// All bit fields as a 32-bit value 757 /// 758 UINT32 Uint32; 759 /// 760 /// All bit fields as a 64-bit value 761 /// 762 UINT64 Uint64; 763 } MSR_IVY_BRIDGE_TEMPERATURE_TARGET_REGISTER; 764 765 766 /** 767 Package. Maximum Ratio Limit of Turbo Mode RO if MSR_PLATFORM_INFO.[28] = 0, 768 RW if MSR_PLATFORM_INFO.[28] = 1. 769 770 @param ECX MSR_IVY_BRIDGE_TURBO_RATIO_LIMIT1 (0x000001AE) 771 @param EAX Lower 32-bits of MSR value. 772 Described by the type MSR_IVY_BRIDGE_TURBO_RATIO_LIMIT1_REGISTER. 773 @param EDX Upper 32-bits of MSR value. 774 Described by the type MSR_IVY_BRIDGE_TURBO_RATIO_LIMIT1_REGISTER. 775 776 <b>Example usage</b> 777 @code 778 MSR_IVY_BRIDGE_TURBO_RATIO_LIMIT1_REGISTER Msr; 779 780 Msr.Uint64 = AsmReadMsr64 (MSR_IVY_BRIDGE_TURBO_RATIO_LIMIT1); 781 @endcode 782 @note MSR_IVY_BRIDGE_TURBO_RATIO_LIMIT1 is defined as MSR_TURBO_RATIO_LIMIT1 in SDM. 783 **/ 784 #define MSR_IVY_BRIDGE_TURBO_RATIO_LIMIT1 0x000001AE 785 786 /** 787 MSR information returned for MSR index #MSR_IVY_BRIDGE_TURBO_RATIO_LIMIT1 788 **/ 789 typedef union { 790 /// 791 /// Individual bit fields 792 /// 793 struct { 794 /// 795 /// [Bits 7:0] Package. Maximum Ratio Limit for 9C Maximum turbo ratio 796 /// limit of 9 core active. 797 /// 798 UINT32 Maximum9C:8; 799 /// 800 /// [Bits 15:8] Package. Maximum Ratio Limit for 10C Maximum turbo ratio 801 /// limit of 10core active. 802 /// 803 UINT32 Maximum10C:8; 804 /// 805 /// [Bits 23:16] Package. Maximum Ratio Limit for 11C Maximum turbo ratio 806 /// limit of 11 core active. 807 /// 808 UINT32 Maximum11C:8; 809 /// 810 /// [Bits 31:24] Package. Maximum Ratio Limit for 12C Maximum turbo ratio 811 /// limit of 12 core active. 812 /// 813 UINT32 Maximum12C:8; 814 /// 815 /// [Bits 39:32] Package. Maximum Ratio Limit for 13C Maximum turbo ratio 816 /// limit of 13 core active. 817 /// 818 UINT32 Maximum13C:8; 819 /// 820 /// [Bits 47:40] Package. Maximum Ratio Limit for 14C Maximum turbo ratio 821 /// limit of 14 core active. 822 /// 823 UINT32 Maximum14C:8; 824 /// 825 /// [Bits 55:48] Package. Maximum Ratio Limit for 15C Maximum turbo ratio 826 /// limit of 15 core active. 827 /// 828 UINT32 Maximum15C:8; 829 UINT32 Reserved:7; 830 /// 831 /// [Bit 63] Package. Semaphore for Turbo Ratio Limit Configuration If 1, 832 /// the processor uses override configuration specified in 833 /// MSR_TURBO_RATIO_LIMIT and MSR_TURBO_RATIO_LIMIT1. If 0, the processor 834 /// uses factory-set configuration (Default). 835 /// 836 UINT32 TurboRatioLimitConfigurationSemaphore:1; 837 } Bits; 838 /// 839 /// All bit fields as a 64-bit value 840 /// 841 UINT64 Uint64; 842 } MSR_IVY_BRIDGE_TURBO_RATIO_LIMIT1_REGISTER; 843 844 845 /** 846 Package. Misc MAC information of Integrated I/O. (R/O) see Section 15.3.2.4. 847 848 @param ECX MSR_IVY_BRIDGE_IA32_MC6_MISC (0x0000041B) 849 @param EAX Lower 32-bits of MSR value. 850 Described by the type MSR_IVY_BRIDGE_IA32_MC6_MISC_REGISTER. 851 @param EDX Upper 32-bits of MSR value. 852 Described by the type MSR_IVY_BRIDGE_IA32_MC6_MISC_REGISTER. 853 854 <b>Example usage</b> 855 @code 856 MSR_IVY_BRIDGE_IA32_MC6_MISC_REGISTER Msr; 857 858 Msr.Uint64 = AsmReadMsr64 (MSR_IVY_BRIDGE_IA32_MC6_MISC); 859 @endcode 860 @note MSR_IVY_BRIDGE_IA32_MC6_MISC is defined as IA32_MC6_MISC in SDM. 861 **/ 862 #define MSR_IVY_BRIDGE_IA32_MC6_MISC 0x0000041B 863 864 /** 865 MSR information returned for MSR index #MSR_IVY_BRIDGE_IA32_MC6_MISC 866 **/ 867 typedef union { 868 /// 869 /// Individual bit fields 870 /// 871 struct { 872 /// 873 /// [Bits 5:0] Recoverable Address LSB. 874 /// 875 UINT32 RecoverableAddressLSB:6; 876 /// 877 /// [Bits 8:6] Address Mode. 878 /// 879 UINT32 AddressMode:3; 880 UINT32 Reserved1:7; 881 /// 882 /// [Bits 31:16] PCI Express Requestor ID. 883 /// 884 UINT32 PCIExpressRequestorID:16; 885 /// 886 /// [Bits 39:32] PCI Express Segment Number. 887 /// 888 UINT32 PCIExpressSegmentNumber:8; 889 UINT32 Reserved2:24; 890 } Bits; 891 /// 892 /// All bit fields as a 64-bit value 893 /// 894 UINT64 Uint64; 895 } MSR_IVY_BRIDGE_IA32_MC6_MISC_REGISTER; 896 897 898 /** 899 Package. See Section 15.3.2.1, "IA32_MCi_CTL MSRs." through Section 900 15.3.2.4, "IA32_MCi_MISC MSRs.". 901 902 Bank MC29 through MC31 reports MC error from a specific CBo (core broadcast) 903 and its corresponding slice of L3. 904 905 @param ECX MSR_IVY_BRIDGE_IA32_MCi_CTL 906 @param EAX Lower 32-bits of MSR value. 907 @param EDX Upper 32-bits of MSR value. 908 909 <b>Example usage</b> 910 @code 911 UINT64 Msr; 912 913 Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_IA32_MC29_CTL); 914 AsmWriteMsr64 (MSR_IVY_BRIDGE_IA32_MC29_CTL, Msr); 915 @endcode 916 @note MSR_IVY_BRIDGE_IA32_MC29_CTL is defined as IA32_MC29_CTL in SDM. 917 MSR_IVY_BRIDGE_IA32_MC30_CTL is defined as IA32_MC30_CTL in SDM. 918 MSR_IVY_BRIDGE_IA32_MC31_CTL is defined as IA32_MC31_CTL in SDM. 919 @{ 920 **/ 921 #define MSR_IVY_BRIDGE_IA32_MC29_CTL 0x00000474 922 #define MSR_IVY_BRIDGE_IA32_MC30_CTL 0x00000478 923 #define MSR_IVY_BRIDGE_IA32_MC31_CTL 0x0000047C 924 /// @} 925 926 927 /** 928 Package. See Section 15.3.2.1, "IA32_MCi_CTL MSRs." through Section 929 15.3.2.4, "IA32_MCi_MISC MSRs.". 930 931 Bank MC29 through MC31 reports MC error from a specific CBo (core broadcast) 932 and its corresponding slice of L3. 933 934 @param ECX MSR_IVY_BRIDGE_IA32_MCi_STATUS 935 @param EAX Lower 32-bits of MSR value. 936 @param EDX Upper 32-bits of MSR value. 937 938 <b>Example usage</b> 939 @code 940 UINT64 Msr; 941 942 Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_IA32_MC29_STATUS); 943 AsmWriteMsr64 (MSR_IVY_BRIDGE_IA32_MC29_STATUS, Msr); 944 @endcode 945 @note MSR_IVY_BRIDGE_IA32_MC29_STATUS is defined as IA32_MC29_STATUS in SDM. 946 MSR_IVY_BRIDGE_IA32_MC30_STATUS is defined as IA32_MC30_STATUS in SDM. 947 MSR_IVY_BRIDGE_IA32_MC31_STATUS is defined as IA32_MC31_STATUS in SDM. 948 @{ 949 **/ 950 #define MSR_IVY_BRIDGE_IA32_MC29_STATUS 0x00000475 951 #define MSR_IVY_BRIDGE_IA32_MC30_STATUS 0x00000479 952 #define MSR_IVY_BRIDGE_IA32_MC31_STATUS 0x0000047D 953 /// @} 954 955 956 /** 957 Package. See Section 15.3.2.1, "IA32_MCi_CTL MSRs." through Section 958 15.3.2.4, "IA32_MCi_MISC MSRs.". 959 960 Bank MC29 through MC31 reports MC error from a specific CBo (core broadcast) 961 and its corresponding slice of L3. 962 963 @param ECX MSR_IVY_BRIDGE_IA32_MCi_ADDR 964 @param EAX Lower 32-bits of MSR value. 965 @param EDX Upper 32-bits of MSR value. 966 967 <b>Example usage</b> 968 @code 969 UINT64 Msr; 970 971 Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_IA32_MC29_ADDR); 972 AsmWriteMsr64 (MSR_IVY_BRIDGE_IA32_MC29_ADDR, Msr); 973 @endcode 974 @note MSR_IVY_BRIDGE_IA32_MC29_ADDR is defined as IA32_MC29_ADDR in SDM. 975 MSR_IVY_BRIDGE_IA32_MC30_ADDR is defined as IA32_MC30_ADDR in SDM. 976 MSR_IVY_BRIDGE_IA32_MC31_ADDR is defined as IA32_MC31_ADDR in SDM. 977 @{ 978 **/ 979 #define MSR_IVY_BRIDGE_IA32_MC29_ADDR 0x00000476 980 #define MSR_IVY_BRIDGE_IA32_MC30_ADDR 0x0000047A 981 #define MSR_IVY_BRIDGE_IA32_MC31_ADDR 0x0000047E 982 /// @} 983 984 985 /** 986 Package. See Section 15.3.2.1, "IA32_MCi_CTL MSRs." through Section 987 15.3.2.4, "IA32_MCi_MISC MSRs.". 988 989 Bank MC29 through MC31 reports MC error from a specific CBo (core broadcast) 990 and its corresponding slice of L3. 991 992 @param ECX MSR_IVY_BRIDGE_IA32_MCi_MISC 993 @param EAX Lower 32-bits of MSR value. 994 @param EDX Upper 32-bits of MSR value. 995 996 <b>Example usage</b> 997 @code 998 UINT64 Msr; 999 1000 Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_IA32_MC29_MISC); 1001 AsmWriteMsr64 (MSR_IVY_BRIDGE_IA32_MC29_MISC, Msr); 1002 @endcode 1003 @note MSR_IVY_BRIDGE_IA32_MC29_MISC is defined as IA32_MC29_MISC in SDM. 1004 MSR_IVY_BRIDGE_IA32_MC30_MISC is defined as IA32_MC30_MISC in SDM. 1005 MSR_IVY_BRIDGE_IA32_MC31_MISC is defined as IA32_MC31_MISC in SDM. 1006 @{ 1007 **/ 1008 #define MSR_IVY_BRIDGE_IA32_MC29_MISC 0x00000477 1009 #define MSR_IVY_BRIDGE_IA32_MC30_MISC 0x0000047B 1010 #define MSR_IVY_BRIDGE_IA32_MC31_MISC 0x0000047F 1011 /// @} 1012 1013 1014 /** 1015 Package. Package RAPL Perf Status (R/O). 1016 1017 @param ECX MSR_IVY_BRIDGE_PKG_PERF_STATUS (0x00000613) 1018 @param EAX Lower 32-bits of MSR value. 1019 @param EDX Upper 32-bits of MSR value. 1020 1021 <b>Example usage</b> 1022 @code 1023 UINT64 Msr; 1024 1025 Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_PKG_PERF_STATUS); 1026 @endcode 1027 @note MSR_IVY_BRIDGE_PKG_PERF_STATUS is defined as MSR_PKG_PERF_STATUS in SDM. 1028 **/ 1029 #define MSR_IVY_BRIDGE_PKG_PERF_STATUS 0x00000613 1030 1031 1032 /** 1033 Package. DRAM RAPL Power Limit Control (R/W) See Section 14.9.5, "DRAM RAPL 1034 Domain.". 1035 1036 @param ECX MSR_IVY_BRIDGE_DRAM_POWER_LIMIT (0x00000618) 1037 @param EAX Lower 32-bits of MSR value. 1038 @param EDX Upper 32-bits of MSR value. 1039 1040 <b>Example usage</b> 1041 @code 1042 UINT64 Msr; 1043 1044 Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_DRAM_POWER_LIMIT); 1045 AsmWriteMsr64 (MSR_IVY_BRIDGE_DRAM_POWER_LIMIT, Msr); 1046 @endcode 1047 @note MSR_IVY_BRIDGE_DRAM_POWER_LIMIT is defined as MSR_DRAM_POWER_LIMIT in SDM. 1048 **/ 1049 #define MSR_IVY_BRIDGE_DRAM_POWER_LIMIT 0x00000618 1050 1051 1052 /** 1053 Package. DRAM Energy Status (R/O) See Section 14.9.5, "DRAM RAPL Domain.". 1054 1055 @param ECX MSR_IVY_BRIDGE_DRAM_ENERGY_STATUS (0x00000619) 1056 @param EAX Lower 32-bits of MSR value. 1057 @param EDX Upper 32-bits of MSR value. 1058 1059 <b>Example usage</b> 1060 @code 1061 UINT64 Msr; 1062 1063 Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_DRAM_ENERGY_STATUS); 1064 @endcode 1065 @note MSR_IVY_BRIDGE_DRAM_ENERGY_STATUS is defined as MSR_DRAM_ENERGY_STATUS in SDM. 1066 **/ 1067 #define MSR_IVY_BRIDGE_DRAM_ENERGY_STATUS 0x00000619 1068 1069 1070 /** 1071 Package. DRAM Performance Throttling Status (R/O) See Section 14.9.5, "DRAM 1072 RAPL Domain.". 1073 1074 @param ECX MSR_IVY_BRIDGE_DRAM_PERF_STATUS (0x0000061B) 1075 @param EAX Lower 32-bits of MSR value. 1076 @param EDX Upper 32-bits of MSR value. 1077 1078 <b>Example usage</b> 1079 @code 1080 UINT64 Msr; 1081 1082 Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_DRAM_PERF_STATUS); 1083 @endcode 1084 @note MSR_IVY_BRIDGE_DRAM_PERF_STATUS is defined as MSR_DRAM_PERF_STATUS in SDM. 1085 **/ 1086 #define MSR_IVY_BRIDGE_DRAM_PERF_STATUS 0x0000061B 1087 1088 1089 /** 1090 Package. DRAM RAPL Parameters (R/W) See Section 14.9.5, "DRAM RAPL Domain.". 1091 1092 @param ECX MSR_IVY_BRIDGE_DRAM_POWER_INFO (0x0000061C) 1093 @param EAX Lower 32-bits of MSR value. 1094 @param EDX Upper 32-bits of MSR value. 1095 1096 <b>Example usage</b> 1097 @code 1098 UINT64 Msr; 1099 1100 Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_DRAM_POWER_INFO); 1101 AsmWriteMsr64 (MSR_IVY_BRIDGE_DRAM_POWER_INFO, Msr); 1102 @endcode 1103 @note MSR_IVY_BRIDGE_DRAM_POWER_INFO is defined as MSR_DRAM_POWER_INFO in SDM. 1104 **/ 1105 #define MSR_IVY_BRIDGE_DRAM_POWER_INFO 0x0000061C 1106 1107 1108 /** 1109 Thread. See Section 18.3.1.1.1, "Processor Event Based Sampling (PEBS).". 1110 1111 @param ECX MSR_IVY_BRIDGE_PEBS_ENABLE (0x000003F1) 1112 @param EAX Lower 32-bits of MSR value. 1113 Described by the type MSR_IVY_BRIDGE_PEBS_ENABLE_REGISTER. 1114 @param EDX Upper 32-bits of MSR value. 1115 Described by the type MSR_IVY_BRIDGE_PEBS_ENABLE_REGISTER. 1116 1117 <b>Example usage</b> 1118 @code 1119 MSR_IVY_BRIDGE_PEBS_ENABLE_REGISTER Msr; 1120 1121 Msr.Uint64 = AsmReadMsr64 (MSR_IVY_BRIDGE_PEBS_ENABLE); 1122 AsmWriteMsr64 (MSR_IVY_BRIDGE_PEBS_ENABLE, Msr.Uint64); 1123 @endcode 1124 @note MSR_IVY_BRIDGE_PEBS_ENABLE is defined as MSR_PEBS_ENABLE in SDM. 1125 **/ 1126 #define MSR_IVY_BRIDGE_PEBS_ENABLE 0x000003F1 1127 1128 /** 1129 MSR information returned for MSR index #MSR_IVY_BRIDGE_PEBS_ENABLE 1130 **/ 1131 typedef union { 1132 /// 1133 /// Individual bit fields 1134 /// 1135 struct { 1136 /// 1137 /// [Bit 0] Enable PEBS on IA32_PMC0. (R/W). 1138 /// 1139 UINT32 PEBS_EN_PMC0:1; 1140 /// 1141 /// [Bit 1] Enable PEBS on IA32_PMC1. (R/W). 1142 /// 1143 UINT32 PEBS_EN_PMC1:1; 1144 /// 1145 /// [Bit 2] Enable PEBS on IA32_PMC2. (R/W). 1146 /// 1147 UINT32 PEBS_EN_PMC2:1; 1148 /// 1149 /// [Bit 3] Enable PEBS on IA32_PMC3. (R/W). 1150 /// 1151 UINT32 PEBS_EN_PMC3:1; 1152 UINT32 Reserved1:28; 1153 /// 1154 /// [Bit 32] Enable Load Latency on IA32_PMC0. (R/W). 1155 /// 1156 UINT32 LL_EN_PMC0:1; 1157 /// 1158 /// [Bit 33] Enable Load Latency on IA32_PMC1. (R/W). 1159 /// 1160 UINT32 LL_EN_PMC1:1; 1161 /// 1162 /// [Bit 34] Enable Load Latency on IA32_PMC2. (R/W). 1163 /// 1164 UINT32 LL_EN_PMC2:1; 1165 /// 1166 /// [Bit 35] Enable Load Latency on IA32_PMC3. (R/W). 1167 /// 1168 UINT32 LL_EN_PMC3:1; 1169 UINT32 Reserved2:28; 1170 } Bits; 1171 /// 1172 /// All bit fields as a 64-bit value 1173 /// 1174 UINT64 Uint64; 1175 } MSR_IVY_BRIDGE_PEBS_ENABLE_REGISTER; 1176 1177 1178 /** 1179 Package. Uncore perfmon per-socket global control. 1180 1181 @param ECX MSR_IVY_BRIDGE_PMON_GLOBAL_CTL (0x00000C00) 1182 @param EAX Lower 32-bits of MSR value. 1183 @param EDX Upper 32-bits of MSR value. 1184 1185 <b>Example usage</b> 1186 @code 1187 UINT64 Msr; 1188 1189 Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_PMON_GLOBAL_CTL); 1190 AsmWriteMsr64 (MSR_IVY_BRIDGE_PMON_GLOBAL_CTL, Msr); 1191 @endcode 1192 @note MSR_IVY_BRIDGE_PMON_GLOBAL_CTL is defined as MSR_PMON_GLOBAL_CTL in SDM. 1193 **/ 1194 #define MSR_IVY_BRIDGE_PMON_GLOBAL_CTL 0x00000C00 1195 1196 1197 /** 1198 Package. Uncore perfmon per-socket global status. 1199 1200 @param ECX MSR_IVY_BRIDGE_PMON_GLOBAL_STATUS (0x00000C01) 1201 @param EAX Lower 32-bits of MSR value. 1202 @param EDX Upper 32-bits of MSR value. 1203 1204 <b>Example usage</b> 1205 @code 1206 UINT64 Msr; 1207 1208 Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_PMON_GLOBAL_STATUS); 1209 AsmWriteMsr64 (MSR_IVY_BRIDGE_PMON_GLOBAL_STATUS, Msr); 1210 @endcode 1211 @note MSR_IVY_BRIDGE_PMON_GLOBAL_STATUS is defined as MSR_PMON_GLOBAL_STATUS in SDM. 1212 **/ 1213 #define MSR_IVY_BRIDGE_PMON_GLOBAL_STATUS 0x00000C01 1214 1215 1216 /** 1217 Package. Uncore perfmon per-socket global configuration. 1218 1219 @param ECX MSR_IVY_BRIDGE_PMON_GLOBAL_CONFIG (0x00000C06) 1220 @param EAX Lower 32-bits of MSR value. 1221 @param EDX Upper 32-bits of MSR value. 1222 1223 <b>Example usage</b> 1224 @code 1225 UINT64 Msr; 1226 1227 Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_PMON_GLOBAL_CONFIG); 1228 AsmWriteMsr64 (MSR_IVY_BRIDGE_PMON_GLOBAL_CONFIG, Msr); 1229 @endcode 1230 @note MSR_IVY_BRIDGE_PMON_GLOBAL_CONFIG is defined as MSR_PMON_GLOBAL_CONFIG in SDM. 1231 **/ 1232 #define MSR_IVY_BRIDGE_PMON_GLOBAL_CONFIG 0x00000C06 1233 1234 1235 /** 1236 Package. Uncore U-box perfmon U-box wide status. 1237 1238 @param ECX MSR_IVY_BRIDGE_U_PMON_BOX_STATUS (0x00000C15) 1239 @param EAX Lower 32-bits of MSR value. 1240 @param EDX Upper 32-bits of MSR value. 1241 1242 <b>Example usage</b> 1243 @code 1244 UINT64 Msr; 1245 1246 Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_U_PMON_BOX_STATUS); 1247 AsmWriteMsr64 (MSR_IVY_BRIDGE_U_PMON_BOX_STATUS, Msr); 1248 @endcode 1249 @note MSR_IVY_BRIDGE_U_PMON_BOX_STATUS is defined as MSR_U_PMON_BOX_STATUS in SDM. 1250 **/ 1251 #define MSR_IVY_BRIDGE_U_PMON_BOX_STATUS 0x00000C15 1252 1253 1254 /** 1255 Package. Uncore PCU perfmon box wide status. 1256 1257 @param ECX MSR_IVY_BRIDGE_PCU_PMON_BOX_STATUS (0x00000C35) 1258 @param EAX Lower 32-bits of MSR value. 1259 @param EDX Upper 32-bits of MSR value. 1260 1261 <b>Example usage</b> 1262 @code 1263 UINT64 Msr; 1264 1265 Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_PCU_PMON_BOX_STATUS); 1266 AsmWriteMsr64 (MSR_IVY_BRIDGE_PCU_PMON_BOX_STATUS, Msr); 1267 @endcode 1268 @note MSR_IVY_BRIDGE_PCU_PMON_BOX_STATUS is defined as MSR_PCU_PMON_BOX_STATUS in SDM. 1269 **/ 1270 #define MSR_IVY_BRIDGE_PCU_PMON_BOX_STATUS 0x00000C35 1271 1272 1273 /** 1274 Package. Uncore C-box 0 perfmon box wide filter1. 1275 1276 @param ECX MSR_IVY_BRIDGE_C0_PMON_BOX_FILTER1 (0x00000D1A) 1277 @param EAX Lower 32-bits of MSR value. 1278 @param EDX Upper 32-bits of MSR value. 1279 1280 <b>Example usage</b> 1281 @code 1282 UINT64 Msr; 1283 1284 Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C0_PMON_BOX_FILTER1); 1285 AsmWriteMsr64 (MSR_IVY_BRIDGE_C0_PMON_BOX_FILTER1, Msr); 1286 @endcode 1287 @note MSR_IVY_BRIDGE_C0_PMON_BOX_FILTER1 is defined as MSR_C0_PMON_BOX_FILTER1 in SDM. 1288 **/ 1289 #define MSR_IVY_BRIDGE_C0_PMON_BOX_FILTER1 0x00000D1A 1290 1291 1292 /** 1293 Package. Uncore C-box 1 perfmon box wide filter1. 1294 1295 @param ECX MSR_IVY_BRIDGE_C1_PMON_BOX_FILTER1 (0x00000D3A) 1296 @param EAX Lower 32-bits of MSR value. 1297 @param EDX Upper 32-bits of MSR value. 1298 1299 <b>Example usage</b> 1300 @code 1301 UINT64 Msr; 1302 1303 Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C1_PMON_BOX_FILTER1); 1304 AsmWriteMsr64 (MSR_IVY_BRIDGE_C1_PMON_BOX_FILTER1, Msr); 1305 @endcode 1306 @note MSR_IVY_BRIDGE_C1_PMON_BOX_FILTER1 is defined as MSR_C1_PMON_BOX_FILTER1 in SDM. 1307 **/ 1308 #define MSR_IVY_BRIDGE_C1_PMON_BOX_FILTER1 0x00000D3A 1309 1310 1311 /** 1312 Package. Uncore C-box 2 perfmon box wide filter1. 1313 1314 @param ECX MSR_IVY_BRIDGE_C2_PMON_BOX_FILTER1 (0x00000D5A) 1315 @param EAX Lower 32-bits of MSR value. 1316 @param EDX Upper 32-bits of MSR value. 1317 1318 <b>Example usage</b> 1319 @code 1320 UINT64 Msr; 1321 1322 Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C2_PMON_BOX_FILTER1); 1323 AsmWriteMsr64 (MSR_IVY_BRIDGE_C2_PMON_BOX_FILTER1, Msr); 1324 @endcode 1325 @note MSR_IVY_BRIDGE_C2_PMON_BOX_FILTER1 is defined as MSR_C2_PMON_BOX_FILTER1 in SDM. 1326 **/ 1327 #define MSR_IVY_BRIDGE_C2_PMON_BOX_FILTER1 0x00000D5A 1328 1329 1330 /** 1331 Package. Uncore C-box 3 perfmon box wide filter1. 1332 1333 @param ECX MSR_IVY_BRIDGE_C3_PMON_BOX_FILTER1 (0x00000D7A) 1334 @param EAX Lower 32-bits of MSR value. 1335 @param EDX Upper 32-bits of MSR value. 1336 1337 <b>Example usage</b> 1338 @code 1339 UINT64 Msr; 1340 1341 Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C3_PMON_BOX_FILTER1); 1342 AsmWriteMsr64 (MSR_IVY_BRIDGE_C3_PMON_BOX_FILTER1, Msr); 1343 @endcode 1344 @note MSR_IVY_BRIDGE_C3_PMON_BOX_FILTER1 is defined as MSR_C3_PMON_BOX_FILTER1 in SDM. 1345 **/ 1346 #define MSR_IVY_BRIDGE_C3_PMON_BOX_FILTER1 0x00000D7A 1347 1348 1349 /** 1350 Package. Uncore C-box 4 perfmon box wide filter1. 1351 1352 @param ECX MSR_IVY_BRIDGE_C4_PMON_BOX_FILTER1 (0x00000D9A) 1353 @param EAX Lower 32-bits of MSR value. 1354 @param EDX Upper 32-bits of MSR value. 1355 1356 <b>Example usage</b> 1357 @code 1358 UINT64 Msr; 1359 1360 Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C4_PMON_BOX_FILTER1); 1361 AsmWriteMsr64 (MSR_IVY_BRIDGE_C4_PMON_BOX_FILTER1, Msr); 1362 @endcode 1363 @note MSR_IVY_BRIDGE_C4_PMON_BOX_FILTER1 is defined as MSR_C4_PMON_BOX_FILTER1 in SDM. 1364 **/ 1365 #define MSR_IVY_BRIDGE_C4_PMON_BOX_FILTER1 0x00000D9A 1366 1367 1368 /** 1369 Package. Uncore C-box 5 perfmon box wide filter1. 1370 1371 @param ECX MSR_IVY_BRIDGE_C5_PMON_BOX_FILTER1 (0x00000DBA) 1372 @param EAX Lower 32-bits of MSR value. 1373 @param EDX Upper 32-bits of MSR value. 1374 1375 <b>Example usage</b> 1376 @code 1377 UINT64 Msr; 1378 1379 Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C5_PMON_BOX_FILTER1); 1380 AsmWriteMsr64 (MSR_IVY_BRIDGE_C5_PMON_BOX_FILTER1, Msr); 1381 @endcode 1382 @note MSR_IVY_BRIDGE_C5_PMON_BOX_FILTER1 is defined as MSR_C5_PMON_BOX_FILTER1 in SDM. 1383 **/ 1384 #define MSR_IVY_BRIDGE_C5_PMON_BOX_FILTER1 0x00000DBA 1385 1386 1387 /** 1388 Package. Uncore C-box 6 perfmon box wide filter1. 1389 1390 @param ECX MSR_IVY_BRIDGE_C6_PMON_BOX_FILTER1 (0x00000DDA) 1391 @param EAX Lower 32-bits of MSR value. 1392 @param EDX Upper 32-bits of MSR value. 1393 1394 <b>Example usage</b> 1395 @code 1396 UINT64 Msr; 1397 1398 Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C6_PMON_BOX_FILTER1); 1399 AsmWriteMsr64 (MSR_IVY_BRIDGE_C6_PMON_BOX_FILTER1, Msr); 1400 @endcode 1401 @note MSR_IVY_BRIDGE_C6_PMON_BOX_FILTER1 is defined as MSR_C6_PMON_BOX_FILTER1 in SDM. 1402 **/ 1403 #define MSR_IVY_BRIDGE_C6_PMON_BOX_FILTER1 0x00000DDA 1404 1405 1406 /** 1407 Package. Uncore C-box 7 perfmon box wide filter1. 1408 1409 @param ECX MSR_IVY_BRIDGE_C7_PMON_BOX_FILTER1 (0x00000DFA) 1410 @param EAX Lower 32-bits of MSR value. 1411 @param EDX Upper 32-bits of MSR value. 1412 1413 <b>Example usage</b> 1414 @code 1415 UINT64 Msr; 1416 1417 Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C7_PMON_BOX_FILTER1); 1418 AsmWriteMsr64 (MSR_IVY_BRIDGE_C7_PMON_BOX_FILTER1, Msr); 1419 @endcode 1420 @note MSR_IVY_BRIDGE_C7_PMON_BOX_FILTER1 is defined as MSR_C7_PMON_BOX_FILTER1 in SDM. 1421 **/ 1422 #define MSR_IVY_BRIDGE_C7_PMON_BOX_FILTER1 0x00000DFA 1423 1424 1425 /** 1426 Package. Uncore C-box 8 perfmon local box wide control. 1427 1428 @param ECX MSR_IVY_BRIDGE_C8_PMON_BOX_CTL (0x00000E04) 1429 @param EAX Lower 32-bits of MSR value. 1430 @param EDX Upper 32-bits of MSR value. 1431 1432 <b>Example usage</b> 1433 @code 1434 UINT64 Msr; 1435 1436 Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C8_PMON_BOX_CTL); 1437 AsmWriteMsr64 (MSR_IVY_BRIDGE_C8_PMON_BOX_CTL, Msr); 1438 @endcode 1439 @note MSR_IVY_BRIDGE_C8_PMON_BOX_CTL is defined as MSR_C8_PMON_BOX_CTL in SDM. 1440 **/ 1441 #define MSR_IVY_BRIDGE_C8_PMON_BOX_CTL 0x00000E04 1442 1443 1444 /** 1445 Package. Uncore C-box 8 perfmon event select for C-box 8 counter 0. 1446 1447 @param ECX MSR_IVY_BRIDGE_C8_PMON_EVNTSEL0 (0x00000E10) 1448 @param EAX Lower 32-bits of MSR value. 1449 @param EDX Upper 32-bits of MSR value. 1450 1451 <b>Example usage</b> 1452 @code 1453 UINT64 Msr; 1454 1455 Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C8_PMON_EVNTSEL0); 1456 AsmWriteMsr64 (MSR_IVY_BRIDGE_C8_PMON_EVNTSEL0, Msr); 1457 @endcode 1458 @note MSR_IVY_BRIDGE_C8_PMON_EVNTSEL0 is defined as MSR_C8_PMON_EVNTSEL0 in SDM. 1459 **/ 1460 #define MSR_IVY_BRIDGE_C8_PMON_EVNTSEL0 0x00000E10 1461 1462 1463 /** 1464 Package. Uncore C-box 8 perfmon event select for C-box 8 counter 1. 1465 1466 @param ECX MSR_IVY_BRIDGE_C8_PMON_EVNTSEL1 (0x00000E11) 1467 @param EAX Lower 32-bits of MSR value. 1468 @param EDX Upper 32-bits of MSR value. 1469 1470 <b>Example usage</b> 1471 @code 1472 UINT64 Msr; 1473 1474 Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C8_PMON_EVNTSEL1); 1475 AsmWriteMsr64 (MSR_IVY_BRIDGE_C8_PMON_EVNTSEL1, Msr); 1476 @endcode 1477 @note MSR_IVY_BRIDGE_C8_PMON_EVNTSEL1 is defined as MSR_C8_PMON_EVNTSEL1 in SDM. 1478 **/ 1479 #define MSR_IVY_BRIDGE_C8_PMON_EVNTSEL1 0x00000E11 1480 1481 1482 /** 1483 Package. Uncore C-box 8 perfmon event select for C-box 8 counter 2. 1484 1485 @param ECX MSR_IVY_BRIDGE_C8_PMON_EVNTSEL2 (0x00000E12) 1486 @param EAX Lower 32-bits of MSR value. 1487 @param EDX Upper 32-bits of MSR value. 1488 1489 <b>Example usage</b> 1490 @code 1491 UINT64 Msr; 1492 1493 Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C8_PMON_EVNTSEL2); 1494 AsmWriteMsr64 (MSR_IVY_BRIDGE_C8_PMON_EVNTSEL2, Msr); 1495 @endcode 1496 @note MSR_IVY_BRIDGE_C8_PMON_EVNTSEL2 is defined as MSR_C8_PMON_EVNTSEL2 in SDM. 1497 **/ 1498 #define MSR_IVY_BRIDGE_C8_PMON_EVNTSEL2 0x00000E12 1499 1500 1501 /** 1502 Package. Uncore C-box 8 perfmon event select for C-box 8 counter 3. 1503 1504 @param ECX MSR_IVY_BRIDGE_C8_PMON_EVNTSEL3 (0x00000E13) 1505 @param EAX Lower 32-bits of MSR value. 1506 @param EDX Upper 32-bits of MSR value. 1507 1508 <b>Example usage</b> 1509 @code 1510 UINT64 Msr; 1511 1512 Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C8_PMON_EVNTSEL3); 1513 AsmWriteMsr64 (MSR_IVY_BRIDGE_C8_PMON_EVNTSEL3, Msr); 1514 @endcode 1515 @note MSR_IVY_BRIDGE_C8_PMON_EVNTSEL3 is defined as MSR_C8_PMON_EVNTSEL3 in SDM. 1516 **/ 1517 #define MSR_IVY_BRIDGE_C8_PMON_EVNTSEL3 0x00000E13 1518 1519 1520 /** 1521 Package. Uncore C-box 8 perfmon box wide filter. 1522 1523 @param ECX MSR_IVY_BRIDGE_C8_PMON_BOX_FILTER (0x00000E14) 1524 @param EAX Lower 32-bits of MSR value. 1525 @param EDX Upper 32-bits of MSR value. 1526 1527 <b>Example usage</b> 1528 @code 1529 UINT64 Msr; 1530 1531 Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C8_PMON_BOX_FILTER); 1532 AsmWriteMsr64 (MSR_IVY_BRIDGE_C8_PMON_BOX_FILTER, Msr); 1533 @endcode 1534 @note MSR_IVY_BRIDGE_C8_PMON_BOX_FILTER is defined as MSR_C8_PMON_BOX_FILTER in SDM. 1535 **/ 1536 #define MSR_IVY_BRIDGE_C8_PMON_BOX_FILTER 0x00000E14 1537 1538 1539 /** 1540 Package. Uncore C-box 8 perfmon counter 0. 1541 1542 @param ECX MSR_IVY_BRIDGE_C8_PMON_CTR0 (0x00000E16) 1543 @param EAX Lower 32-bits of MSR value. 1544 @param EDX Upper 32-bits of MSR value. 1545 1546 <b>Example usage</b> 1547 @code 1548 UINT64 Msr; 1549 1550 Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C8_PMON_CTR0); 1551 AsmWriteMsr64 (MSR_IVY_BRIDGE_C8_PMON_CTR0, Msr); 1552 @endcode 1553 @note MSR_IVY_BRIDGE_C8_PMON_CTR0 is defined as MSR_C8_PMON_CTR0 in SDM. 1554 **/ 1555 #define MSR_IVY_BRIDGE_C8_PMON_CTR0 0x00000E16 1556 1557 1558 /** 1559 Package. Uncore C-box 8 perfmon counter 1. 1560 1561 @param ECX MSR_IVY_BRIDGE_C8_PMON_CTR1 (0x00000E17) 1562 @param EAX Lower 32-bits of MSR value. 1563 @param EDX Upper 32-bits of MSR value. 1564 1565 <b>Example usage</b> 1566 @code 1567 UINT64 Msr; 1568 1569 Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C8_PMON_CTR1); 1570 AsmWriteMsr64 (MSR_IVY_BRIDGE_C8_PMON_CTR1, Msr); 1571 @endcode 1572 @note MSR_IVY_BRIDGE_C8_PMON_CTR1 is defined as MSR_C8_PMON_CTR1 in SDM. 1573 **/ 1574 #define MSR_IVY_BRIDGE_C8_PMON_CTR1 0x00000E17 1575 1576 1577 /** 1578 Package. Uncore C-box 8 perfmon counter 2. 1579 1580 @param ECX MSR_IVY_BRIDGE_C8_PMON_CTR2 (0x00000E18) 1581 @param EAX Lower 32-bits of MSR value. 1582 @param EDX Upper 32-bits of MSR value. 1583 1584 <b>Example usage</b> 1585 @code 1586 UINT64 Msr; 1587 1588 Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C8_PMON_CTR2); 1589 AsmWriteMsr64 (MSR_IVY_BRIDGE_C8_PMON_CTR2, Msr); 1590 @endcode 1591 @note MSR_IVY_BRIDGE_C8_PMON_CTR2 is defined as MSR_C8_PMON_CTR2 in SDM. 1592 **/ 1593 #define MSR_IVY_BRIDGE_C8_PMON_CTR2 0x00000E18 1594 1595 1596 /** 1597 Package. Uncore C-box 8 perfmon counter 3. 1598 1599 @param ECX MSR_IVY_BRIDGE_C8_PMON_CTR3 (0x00000E19) 1600 @param EAX Lower 32-bits of MSR value. 1601 @param EDX Upper 32-bits of MSR value. 1602 1603 <b>Example usage</b> 1604 @code 1605 UINT64 Msr; 1606 1607 Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C8_PMON_CTR3); 1608 AsmWriteMsr64 (MSR_IVY_BRIDGE_C8_PMON_CTR3, Msr); 1609 @endcode 1610 @note MSR_IVY_BRIDGE_C8_PMON_CTR3 is defined as MSR_C8_PMON_CTR3 in SDM. 1611 **/ 1612 #define MSR_IVY_BRIDGE_C8_PMON_CTR3 0x00000E19 1613 1614 1615 /** 1616 Package. Uncore C-box 8 perfmon box wide filter1. 1617 1618 @param ECX MSR_IVY_BRIDGE_C8_PMON_BOX_FILTER1 (0x00000E1A) 1619 @param EAX Lower 32-bits of MSR value. 1620 @param EDX Upper 32-bits of MSR value. 1621 1622 <b>Example usage</b> 1623 @code 1624 UINT64 Msr; 1625 1626 Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C8_PMON_BOX_FILTER1); 1627 AsmWriteMsr64 (MSR_IVY_BRIDGE_C8_PMON_BOX_FILTER1, Msr); 1628 @endcode 1629 @note MSR_IVY_BRIDGE_C8_PMON_BOX_FILTER1 is defined as MSR_C8_PMON_BOX_FILTER1 in SDM. 1630 **/ 1631 #define MSR_IVY_BRIDGE_C8_PMON_BOX_FILTER1 0x00000E1A 1632 1633 1634 /** 1635 Package. Uncore C-box 9 perfmon local box wide control. 1636 1637 @param ECX MSR_IVY_BRIDGE_C9_PMON_BOX_CTL (0x00000E24) 1638 @param EAX Lower 32-bits of MSR value. 1639 @param EDX Upper 32-bits of MSR value. 1640 1641 <b>Example usage</b> 1642 @code 1643 UINT64 Msr; 1644 1645 Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C9_PMON_BOX_CTL); 1646 AsmWriteMsr64 (MSR_IVY_BRIDGE_C9_PMON_BOX_CTL, Msr); 1647 @endcode 1648 @note MSR_IVY_BRIDGE_C9_PMON_BOX_CTL is defined as MSR_C9_PMON_BOX_CTL in SDM. 1649 **/ 1650 #define MSR_IVY_BRIDGE_C9_PMON_BOX_CTL 0x00000E24 1651 1652 1653 /** 1654 Package. Uncore C-box 9 perfmon event select for C-box 9 counter 0. 1655 1656 @param ECX MSR_IVY_BRIDGE_C9_PMON_EVNTSEL0 (0x00000E30) 1657 @param EAX Lower 32-bits of MSR value. 1658 @param EDX Upper 32-bits of MSR value. 1659 1660 <b>Example usage</b> 1661 @code 1662 UINT64 Msr; 1663 1664 Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C9_PMON_EVNTSEL0); 1665 AsmWriteMsr64 (MSR_IVY_BRIDGE_C9_PMON_EVNTSEL0, Msr); 1666 @endcode 1667 @note MSR_IVY_BRIDGE_C9_PMON_EVNTSEL0 is defined as MSR_C9_PMON_EVNTSEL0 in SDM. 1668 **/ 1669 #define MSR_IVY_BRIDGE_C9_PMON_EVNTSEL0 0x00000E30 1670 1671 1672 /** 1673 Package. Uncore C-box 9 perfmon event select for C-box 9 counter 1. 1674 1675 @param ECX MSR_IVY_BRIDGE_C9_PMON_EVNTSEL1 (0x00000E31) 1676 @param EAX Lower 32-bits of MSR value. 1677 @param EDX Upper 32-bits of MSR value. 1678 1679 <b>Example usage</b> 1680 @code 1681 UINT64 Msr; 1682 1683 Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C9_PMON_EVNTSEL1); 1684 AsmWriteMsr64 (MSR_IVY_BRIDGE_C9_PMON_EVNTSEL1, Msr); 1685 @endcode 1686 @note MSR_IVY_BRIDGE_C9_PMON_EVNTSEL1 is defined as MSR_C9_PMON_EVNTSEL1 in SDM. 1687 **/ 1688 #define MSR_IVY_BRIDGE_C9_PMON_EVNTSEL1 0x00000E31 1689 1690 1691 /** 1692 Package. Uncore C-box 9 perfmon event select for C-box 9 counter 2. 1693 1694 @param ECX MSR_IVY_BRIDGE_C9_PMON_EVNTSEL2 (0x00000E32) 1695 @param EAX Lower 32-bits of MSR value. 1696 @param EDX Upper 32-bits of MSR value. 1697 1698 <b>Example usage</b> 1699 @code 1700 UINT64 Msr; 1701 1702 Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C9_PMON_EVNTSEL2); 1703 AsmWriteMsr64 (MSR_IVY_BRIDGE_C9_PMON_EVNTSEL2, Msr); 1704 @endcode 1705 @note MSR_IVY_BRIDGE_C9_PMON_EVNTSEL2 is defined as MSR_C9_PMON_EVNTSEL2 in SDM. 1706 **/ 1707 #define MSR_IVY_BRIDGE_C9_PMON_EVNTSEL2 0x00000E32 1708 1709 1710 /** 1711 Package. Uncore C-box 9 perfmon event select for C-box 9 counter 3. 1712 1713 @param ECX MSR_IVY_BRIDGE_C9_PMON_EVNTSEL3 (0x00000E33) 1714 @param EAX Lower 32-bits of MSR value. 1715 @param EDX Upper 32-bits of MSR value. 1716 1717 <b>Example usage</b> 1718 @code 1719 UINT64 Msr; 1720 1721 Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C9_PMON_EVNTSEL3); 1722 AsmWriteMsr64 (MSR_IVY_BRIDGE_C9_PMON_EVNTSEL3, Msr); 1723 @endcode 1724 @note MSR_IVY_BRIDGE_C9_PMON_EVNTSEL3 is defined as MSR_C9_PMON_EVNTSEL3 in SDM. 1725 **/ 1726 #define MSR_IVY_BRIDGE_C9_PMON_EVNTSEL3 0x00000E33 1727 1728 1729 /** 1730 Package. Uncore C-box 9 perfmon box wide filter. 1731 1732 @param ECX MSR_IVY_BRIDGE_C9_PMON_BOX_FILTER (0x00000E34) 1733 @param EAX Lower 32-bits of MSR value. 1734 @param EDX Upper 32-bits of MSR value. 1735 1736 <b>Example usage</b> 1737 @code 1738 UINT64 Msr; 1739 1740 Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C9_PMON_BOX_FILTER); 1741 AsmWriteMsr64 (MSR_IVY_BRIDGE_C9_PMON_BOX_FILTER, Msr); 1742 @endcode 1743 @note MSR_IVY_BRIDGE_C9_PMON_BOX_FILTER is defined as MSR_C9_PMON_BOX_FILTER in SDM. 1744 **/ 1745 #define MSR_IVY_BRIDGE_C9_PMON_BOX_FILTER 0x00000E34 1746 1747 1748 /** 1749 Package. Uncore C-box 9 perfmon counter 0. 1750 1751 @param ECX MSR_IVY_BRIDGE_C9_PMON_CTR0 (0x00000E36) 1752 @param EAX Lower 32-bits of MSR value. 1753 @param EDX Upper 32-bits of MSR value. 1754 1755 <b>Example usage</b> 1756 @code 1757 UINT64 Msr; 1758 1759 Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C9_PMON_CTR0); 1760 AsmWriteMsr64 (MSR_IVY_BRIDGE_C9_PMON_CTR0, Msr); 1761 @endcode 1762 @note MSR_IVY_BRIDGE_C9_PMON_CTR0 is defined as MSR_C9_PMON_CTR0 in SDM. 1763 **/ 1764 #define MSR_IVY_BRIDGE_C9_PMON_CTR0 0x00000E36 1765 1766 1767 /** 1768 Package. Uncore C-box 9 perfmon counter 1. 1769 1770 @param ECX MSR_IVY_BRIDGE_C9_PMON_CTR1 (0x00000E37) 1771 @param EAX Lower 32-bits of MSR value. 1772 @param EDX Upper 32-bits of MSR value. 1773 1774 <b>Example usage</b> 1775 @code 1776 UINT64 Msr; 1777 1778 Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C9_PMON_CTR1); 1779 AsmWriteMsr64 (MSR_IVY_BRIDGE_C9_PMON_CTR1, Msr); 1780 @endcode 1781 @note MSR_IVY_BRIDGE_C9_PMON_CTR1 is defined as MSR_C9_PMON_CTR1 in SDM. 1782 **/ 1783 #define MSR_IVY_BRIDGE_C9_PMON_CTR1 0x00000E37 1784 1785 1786 /** 1787 Package. Uncore C-box 9 perfmon counter 2. 1788 1789 @param ECX MSR_IVY_BRIDGE_C9_PMON_CTR2 (0x00000E38) 1790 @param EAX Lower 32-bits of MSR value. 1791 @param EDX Upper 32-bits of MSR value. 1792 1793 <b>Example usage</b> 1794 @code 1795 UINT64 Msr; 1796 1797 Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C9_PMON_CTR2); 1798 AsmWriteMsr64 (MSR_IVY_BRIDGE_C9_PMON_CTR2, Msr); 1799 @endcode 1800 @note MSR_IVY_BRIDGE_C9_PMON_CTR2 is defined as MSR_C9_PMON_CTR2 in SDM. 1801 **/ 1802 #define MSR_IVY_BRIDGE_C9_PMON_CTR2 0x00000E38 1803 1804 1805 /** 1806 Package. Uncore C-box 9 perfmon counter 3. 1807 1808 @param ECX MSR_IVY_BRIDGE_C9_PMON_CTR3 (0x00000E39) 1809 @param EAX Lower 32-bits of MSR value. 1810 @param EDX Upper 32-bits of MSR value. 1811 1812 <b>Example usage</b> 1813 @code 1814 UINT64 Msr; 1815 1816 Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C9_PMON_CTR3); 1817 AsmWriteMsr64 (MSR_IVY_BRIDGE_C9_PMON_CTR3, Msr); 1818 @endcode 1819 @note MSR_IVY_BRIDGE_C9_PMON_CTR3 is defined as MSR_C9_PMON_CTR3 in SDM. 1820 **/ 1821 #define MSR_IVY_BRIDGE_C9_PMON_CTR3 0x00000E39 1822 1823 1824 /** 1825 Package. Uncore C-box 9 perfmon box wide filter1. 1826 1827 @param ECX MSR_IVY_BRIDGE_C9_PMON_BOX_FILTER1 (0x00000E3A) 1828 @param EAX Lower 32-bits of MSR value. 1829 @param EDX Upper 32-bits of MSR value. 1830 1831 <b>Example usage</b> 1832 @code 1833 UINT64 Msr; 1834 1835 Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C9_PMON_BOX_FILTER1); 1836 AsmWriteMsr64 (MSR_IVY_BRIDGE_C9_PMON_BOX_FILTER1, Msr); 1837 @endcode 1838 @note MSR_IVY_BRIDGE_C9_PMON_BOX_FILTER1 is defined as MSR_C9_PMON_BOX_FILTER1 in SDM. 1839 **/ 1840 #define MSR_IVY_BRIDGE_C9_PMON_BOX_FILTER1 0x00000E3A 1841 1842 1843 /** 1844 Package. Uncore C-box 10 perfmon local box wide control. 1845 1846 @param ECX MSR_IVY_BRIDGE_C10_PMON_BOX_CTL (0x00000E44) 1847 @param EAX Lower 32-bits of MSR value. 1848 @param EDX Upper 32-bits of MSR value. 1849 1850 <b>Example usage</b> 1851 @code 1852 UINT64 Msr; 1853 1854 Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C10_PMON_BOX_CTL); 1855 AsmWriteMsr64 (MSR_IVY_BRIDGE_C10_PMON_BOX_CTL, Msr); 1856 @endcode 1857 @note MSR_IVY_BRIDGE_C10_PMON_BOX_CTL is defined as MSR_C10_PMON_BOX_CTL in SDM. 1858 **/ 1859 #define MSR_IVY_BRIDGE_C10_PMON_BOX_CTL 0x00000E44 1860 1861 1862 /** 1863 Package. Uncore C-box 10 perfmon event select for C-box 10 counter 0. 1864 1865 @param ECX MSR_IVY_BRIDGE_C10_PMON_EVNTSEL0 (0x00000E50) 1866 @param EAX Lower 32-bits of MSR value. 1867 @param EDX Upper 32-bits of MSR value. 1868 1869 <b>Example usage</b> 1870 @code 1871 UINT64 Msr; 1872 1873 Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C10_PMON_EVNTSEL0); 1874 AsmWriteMsr64 (MSR_IVY_BRIDGE_C10_PMON_EVNTSEL0, Msr); 1875 @endcode 1876 @note MSR_IVY_BRIDGE_C10_PMON_EVNTSEL0 is defined as MSR_C10_PMON_EVNTSEL0 in SDM. 1877 **/ 1878 #define MSR_IVY_BRIDGE_C10_PMON_EVNTSEL0 0x00000E50 1879 1880 1881 /** 1882 Package. Uncore C-box 10 perfmon event select for C-box 10 counter 1. 1883 1884 @param ECX MSR_IVY_BRIDGE_C10_PMON_EVNTSEL1 (0x00000E51) 1885 @param EAX Lower 32-bits of MSR value. 1886 @param EDX Upper 32-bits of MSR value. 1887 1888 <b>Example usage</b> 1889 @code 1890 UINT64 Msr; 1891 1892 Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C10_PMON_EVNTSEL1); 1893 AsmWriteMsr64 (MSR_IVY_BRIDGE_C10_PMON_EVNTSEL1, Msr); 1894 @endcode 1895 @note MSR_IVY_BRIDGE_C10_PMON_EVNTSEL1 is defined as MSR_C10_PMON_EVNTSEL1 in SDM. 1896 **/ 1897 #define MSR_IVY_BRIDGE_C10_PMON_EVNTSEL1 0x00000E51 1898 1899 1900 /** 1901 Package. Uncore C-box 10 perfmon event select for C-box 10 counter 2. 1902 1903 @param ECX MSR_IVY_BRIDGE_C10_PMON_EVNTSEL2 (0x00000E52) 1904 @param EAX Lower 32-bits of MSR value. 1905 @param EDX Upper 32-bits of MSR value. 1906 1907 <b>Example usage</b> 1908 @code 1909 UINT64 Msr; 1910 1911 Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C10_PMON_EVNTSEL2); 1912 AsmWriteMsr64 (MSR_IVY_BRIDGE_C10_PMON_EVNTSEL2, Msr); 1913 @endcode 1914 @note MSR_IVY_BRIDGE_C10_PMON_EVNTSEL2 is defined as MSR_C10_PMON_EVNTSEL2 in SDM. 1915 **/ 1916 #define MSR_IVY_BRIDGE_C10_PMON_EVNTSEL2 0x00000E52 1917 1918 1919 /** 1920 Package. Uncore C-box 10 perfmon event select for C-box 10 counter 3. 1921 1922 @param ECX MSR_IVY_BRIDGE_C10_PMON_EVNTSEL3 (0x00000E53) 1923 @param EAX Lower 32-bits of MSR value. 1924 @param EDX Upper 32-bits of MSR value. 1925 1926 <b>Example usage</b> 1927 @code 1928 UINT64 Msr; 1929 1930 Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C10_PMON_EVNTSEL3); 1931 AsmWriteMsr64 (MSR_IVY_BRIDGE_C10_PMON_EVNTSEL3, Msr); 1932 @endcode 1933 @note MSR_IVY_BRIDGE_C10_PMON_EVNTSEL3 is defined as MSR_C10_PMON_EVNTSEL3 in SDM. 1934 **/ 1935 #define MSR_IVY_BRIDGE_C10_PMON_EVNTSEL3 0x00000E53 1936 1937 1938 /** 1939 Package. Uncore C-box 10 perfmon box wide filter. 1940 1941 @param ECX MSR_IVY_BRIDGE_C10_PMON_BOX_FILTER (0x00000E54) 1942 @param EAX Lower 32-bits of MSR value. 1943 @param EDX Upper 32-bits of MSR value. 1944 1945 <b>Example usage</b> 1946 @code 1947 UINT64 Msr; 1948 1949 Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C10_PMON_BOX_FILTER); 1950 AsmWriteMsr64 (MSR_IVY_BRIDGE_C10_PMON_BOX_FILTER, Msr); 1951 @endcode 1952 @note MSR_IVY_BRIDGE_C10_PMON_BOX_FILTER is defined as MSR_C10_PMON_BOX_FILTER in SDM. 1953 **/ 1954 #define MSR_IVY_BRIDGE_C10_PMON_BOX_FILTER 0x00000E54 1955 1956 1957 /** 1958 Package. Uncore C-box 10 perfmon counter 0. 1959 1960 @param ECX MSR_IVY_BRIDGE_C10_PMON_CTR0 (0x00000E56) 1961 @param EAX Lower 32-bits of MSR value. 1962 @param EDX Upper 32-bits of MSR value. 1963 1964 <b>Example usage</b> 1965 @code 1966 UINT64 Msr; 1967 1968 Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C10_PMON_CTR0); 1969 AsmWriteMsr64 (MSR_IVY_BRIDGE_C10_PMON_CTR0, Msr); 1970 @endcode 1971 @note MSR_IVY_BRIDGE_C10_PMON_CTR0 is defined as MSR_C10_PMON_CTR0 in SDM. 1972 **/ 1973 #define MSR_IVY_BRIDGE_C10_PMON_CTR0 0x00000E56 1974 1975 1976 /** 1977 Package. Uncore C-box 10 perfmon counter 1. 1978 1979 @param ECX MSR_IVY_BRIDGE_C10_PMON_CTR1 (0x00000E57) 1980 @param EAX Lower 32-bits of MSR value. 1981 @param EDX Upper 32-bits of MSR value. 1982 1983 <b>Example usage</b> 1984 @code 1985 UINT64 Msr; 1986 1987 Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C10_PMON_CTR1); 1988 AsmWriteMsr64 (MSR_IVY_BRIDGE_C10_PMON_CTR1, Msr); 1989 @endcode 1990 @note MSR_IVY_BRIDGE_C10_PMON_CTR1 is defined as MSR_C10_PMON_CTR1 in SDM. 1991 **/ 1992 #define MSR_IVY_BRIDGE_C10_PMON_CTR1 0x00000E57 1993 1994 1995 /** 1996 Package. Uncore C-box 10 perfmon counter 2. 1997 1998 @param ECX MSR_IVY_BRIDGE_C10_PMON_CTR2 (0x00000E58) 1999 @param EAX Lower 32-bits of MSR value. 2000 @param EDX Upper 32-bits of MSR value. 2001 2002 <b>Example usage</b> 2003 @code 2004 UINT64 Msr; 2005 2006 Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C10_PMON_CTR2); 2007 AsmWriteMsr64 (MSR_IVY_BRIDGE_C10_PMON_CTR2, Msr); 2008 @endcode 2009 @note MSR_IVY_BRIDGE_C10_PMON_CTR2 is defined as MSR_C10_PMON_CTR2 in SDM. 2010 **/ 2011 #define MSR_IVY_BRIDGE_C10_PMON_CTR2 0x00000E58 2012 2013 2014 /** 2015 Package. Uncore C-box 10 perfmon counter 3. 2016 2017 @param ECX MSR_IVY_BRIDGE_C10_PMON_CTR3 (0x00000E59) 2018 @param EAX Lower 32-bits of MSR value. 2019 @param EDX Upper 32-bits of MSR value. 2020 2021 <b>Example usage</b> 2022 @code 2023 UINT64 Msr; 2024 2025 Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C10_PMON_CTR3); 2026 AsmWriteMsr64 (MSR_IVY_BRIDGE_C10_PMON_CTR3, Msr); 2027 @endcode 2028 @note MSR_IVY_BRIDGE_C10_PMON_CTR3 is defined as MSR_C10_PMON_CTR3 in SDM. 2029 **/ 2030 #define MSR_IVY_BRIDGE_C10_PMON_CTR3 0x00000E59 2031 2032 2033 /** 2034 Package. Uncore C-box 10 perfmon box wide filter1. 2035 2036 @param ECX MSR_IVY_BRIDGE_C10_PMON_BOX_FILTER1 (0x00000E5A) 2037 @param EAX Lower 32-bits of MSR value. 2038 @param EDX Upper 32-bits of MSR value. 2039 2040 <b>Example usage</b> 2041 @code 2042 UINT64 Msr; 2043 2044 Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C10_PMON_BOX_FILTER1); 2045 AsmWriteMsr64 (MSR_IVY_BRIDGE_C10_PMON_BOX_FILTER1, Msr); 2046 @endcode 2047 @note MSR_IVY_BRIDGE_C10_PMON_BOX_FILTER1 is defined as MSR_C10_PMON_BOX_FILTER1 in SDM. 2048 **/ 2049 #define MSR_IVY_BRIDGE_C10_PMON_BOX_FILTER1 0x00000E5A 2050 2051 2052 /** 2053 Package. Uncore C-box 11 perfmon local box wide control. 2054 2055 @param ECX MSR_IVY_BRIDGE_C11_PMON_BOX_CTL (0x00000E64) 2056 @param EAX Lower 32-bits of MSR value. 2057 @param EDX Upper 32-bits of MSR value. 2058 2059 <b>Example usage</b> 2060 @code 2061 UINT64 Msr; 2062 2063 Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C11_PMON_BOX_CTL); 2064 AsmWriteMsr64 (MSR_IVY_BRIDGE_C11_PMON_BOX_CTL, Msr); 2065 @endcode 2066 @note MSR_IVY_BRIDGE_C11_PMON_BOX_CTL is defined as MSR_C11_PMON_BOX_CTL in SDM. 2067 **/ 2068 #define MSR_IVY_BRIDGE_C11_PMON_BOX_CTL 0x00000E64 2069 2070 2071 /** 2072 Package. Uncore C-box 11 perfmon event select for C-box 11 counter 0. 2073 2074 @param ECX MSR_IVY_BRIDGE_C11_PMON_EVNTSEL0 (0x00000E70) 2075 @param EAX Lower 32-bits of MSR value. 2076 @param EDX Upper 32-bits of MSR value. 2077 2078 <b>Example usage</b> 2079 @code 2080 UINT64 Msr; 2081 2082 Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C11_PMON_EVNTSEL0); 2083 AsmWriteMsr64 (MSR_IVY_BRIDGE_C11_PMON_EVNTSEL0, Msr); 2084 @endcode 2085 @note MSR_IVY_BRIDGE_C11_PMON_EVNTSEL0 is defined as MSR_C11_PMON_EVNTSEL0 in SDM. 2086 **/ 2087 #define MSR_IVY_BRIDGE_C11_PMON_EVNTSEL0 0x00000E70 2088 2089 2090 /** 2091 Package. Uncore C-box 11 perfmon event select for C-box 11 counter 1. 2092 2093 @param ECX MSR_IVY_BRIDGE_C11_PMON_EVNTSEL1 (0x00000E71) 2094 @param EAX Lower 32-bits of MSR value. 2095 @param EDX Upper 32-bits of MSR value. 2096 2097 <b>Example usage</b> 2098 @code 2099 UINT64 Msr; 2100 2101 Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C11_PMON_EVNTSEL1); 2102 AsmWriteMsr64 (MSR_IVY_BRIDGE_C11_PMON_EVNTSEL1, Msr); 2103 @endcode 2104 @note MSR_IVY_BRIDGE_C11_PMON_EVNTSEL1 is defined as MSR_C11_PMON_EVNTSEL1 in SDM. 2105 **/ 2106 #define MSR_IVY_BRIDGE_C11_PMON_EVNTSEL1 0x00000E71 2107 2108 2109 /** 2110 Package. Uncore C-box 11 perfmon event select for C-box 11 counter 2. 2111 2112 @param ECX MSR_IVY_BRIDGE_C11_PMON_EVNTSEL2 (0x00000E72) 2113 @param EAX Lower 32-bits of MSR value. 2114 @param EDX Upper 32-bits of MSR value. 2115 2116 <b>Example usage</b> 2117 @code 2118 UINT64 Msr; 2119 2120 Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C11_PMON_EVNTSEL2); 2121 AsmWriteMsr64 (MSR_IVY_BRIDGE_C11_PMON_EVNTSEL2, Msr); 2122 @endcode 2123 @note MSR_IVY_BRIDGE_C11_PMON_EVNTSEL2 is defined as MSR_C11_PMON_EVNTSEL2 in SDM. 2124 **/ 2125 #define MSR_IVY_BRIDGE_C11_PMON_EVNTSEL2 0x00000E72 2126 2127 2128 /** 2129 Package. Uncore C-box 11 perfmon event select for C-box 11 counter 3. 2130 2131 @param ECX MSR_IVY_BRIDGE_C11_PMON_EVNTSEL3 (0x00000E73) 2132 @param EAX Lower 32-bits of MSR value. 2133 @param EDX Upper 32-bits of MSR value. 2134 2135 <b>Example usage</b> 2136 @code 2137 UINT64 Msr; 2138 2139 Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C11_PMON_EVNTSEL3); 2140 AsmWriteMsr64 (MSR_IVY_BRIDGE_C11_PMON_EVNTSEL3, Msr); 2141 @endcode 2142 @note MSR_IVY_BRIDGE_C11_PMON_EVNTSEL3 is defined as MSR_C11_PMON_EVNTSEL3 in SDM. 2143 **/ 2144 #define MSR_IVY_BRIDGE_C11_PMON_EVNTSEL3 0x00000E73 2145 2146 2147 /** 2148 Package. Uncore C-box 11 perfmon box wide filter. 2149 2150 @param ECX MSR_IVY_BRIDGE_C11_PMON_BOX_FILTER (0x00000E74) 2151 @param EAX Lower 32-bits of MSR value. 2152 @param EDX Upper 32-bits of MSR value. 2153 2154 <b>Example usage</b> 2155 @code 2156 UINT64 Msr; 2157 2158 Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C11_PMON_BOX_FILTER); 2159 AsmWriteMsr64 (MSR_IVY_BRIDGE_C11_PMON_BOX_FILTER, Msr); 2160 @endcode 2161 @note MSR_IVY_BRIDGE_C11_PMON_BOX_FILTER is defined as MSR_C11_PMON_BOX_FILTER in SDM. 2162 **/ 2163 #define MSR_IVY_BRIDGE_C11_PMON_BOX_FILTER 0x00000E74 2164 2165 2166 /** 2167 Package. Uncore C-box 11 perfmon counter 0. 2168 2169 @param ECX MSR_IVY_BRIDGE_C11_PMON_CTR0 (0x00000E76) 2170 @param EAX Lower 32-bits of MSR value. 2171 @param EDX Upper 32-bits of MSR value. 2172 2173 <b>Example usage</b> 2174 @code 2175 UINT64 Msr; 2176 2177 Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C11_PMON_CTR0); 2178 AsmWriteMsr64 (MSR_IVY_BRIDGE_C11_PMON_CTR0, Msr); 2179 @endcode 2180 @note MSR_IVY_BRIDGE_C11_PMON_CTR0 is defined as MSR_C11_PMON_CTR0 in SDM. 2181 **/ 2182 #define MSR_IVY_BRIDGE_C11_PMON_CTR0 0x00000E76 2183 2184 2185 /** 2186 Package. Uncore C-box 11 perfmon counter 1. 2187 2188 @param ECX MSR_IVY_BRIDGE_C11_PMON_CTR1 (0x00000E77) 2189 @param EAX Lower 32-bits of MSR value. 2190 @param EDX Upper 32-bits of MSR value. 2191 2192 <b>Example usage</b> 2193 @code 2194 UINT64 Msr; 2195 2196 Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C11_PMON_CTR1); 2197 AsmWriteMsr64 (MSR_IVY_BRIDGE_C11_PMON_CTR1, Msr); 2198 @endcode 2199 @note MSR_IVY_BRIDGE_C11_PMON_CTR1 is defined as MSR_C11_PMON_CTR1 in SDM. 2200 **/ 2201 #define MSR_IVY_BRIDGE_C11_PMON_CTR1 0x00000E77 2202 2203 2204 /** 2205 Package. Uncore C-box 11 perfmon counter 2. 2206 2207 @param ECX MSR_IVY_BRIDGE_C11_PMON_CTR2 (0x00000E78) 2208 @param EAX Lower 32-bits of MSR value. 2209 @param EDX Upper 32-bits of MSR value. 2210 2211 <b>Example usage</b> 2212 @code 2213 UINT64 Msr; 2214 2215 Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C11_PMON_CTR2); 2216 AsmWriteMsr64 (MSR_IVY_BRIDGE_C11_PMON_CTR2, Msr); 2217 @endcode 2218 @note MSR_IVY_BRIDGE_C11_PMON_CTR2 is defined as MSR_C11_PMON_CTR2 in SDM. 2219 **/ 2220 #define MSR_IVY_BRIDGE_C11_PMON_CTR2 0x00000E78 2221 2222 2223 /** 2224 Package. Uncore C-box 11 perfmon counter 3. 2225 2226 @param ECX MSR_IVY_BRIDGE_C11_PMON_CTR3 (0x00000E79) 2227 @param EAX Lower 32-bits of MSR value. 2228 @param EDX Upper 32-bits of MSR value. 2229 2230 <b>Example usage</b> 2231 @code 2232 UINT64 Msr; 2233 2234 Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C11_PMON_CTR3); 2235 AsmWriteMsr64 (MSR_IVY_BRIDGE_C11_PMON_CTR3, Msr); 2236 @endcode 2237 @note MSR_IVY_BRIDGE_C11_PMON_CTR3 is defined as MSR_C11_PMON_CTR3 in SDM. 2238 **/ 2239 #define MSR_IVY_BRIDGE_C11_PMON_CTR3 0x00000E79 2240 2241 2242 /** 2243 Package. Uncore C-box 11 perfmon box wide filter1. 2244 2245 @param ECX MSR_IVY_BRIDGE_C11_PMON_BOX_FILTER1 (0x00000E7A) 2246 @param EAX Lower 32-bits of MSR value. 2247 @param EDX Upper 32-bits of MSR value. 2248 2249 <b>Example usage</b> 2250 @code 2251 UINT64 Msr; 2252 2253 Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C11_PMON_BOX_FILTER1); 2254 AsmWriteMsr64 (MSR_IVY_BRIDGE_C11_PMON_BOX_FILTER1, Msr); 2255 @endcode 2256 @note MSR_IVY_BRIDGE_C11_PMON_BOX_FILTER1 is defined as MSR_C11_PMON_BOX_FILTER1 in SDM. 2257 **/ 2258 #define MSR_IVY_BRIDGE_C11_PMON_BOX_FILTER1 0x00000E7A 2259 2260 2261 /** 2262 Package. Uncore C-box 12 perfmon local box wide control. 2263 2264 @param ECX MSR_IVY_BRIDGE_C12_PMON_BOX_CTL (0x00000E84) 2265 @param EAX Lower 32-bits of MSR value. 2266 @param EDX Upper 32-bits of MSR value. 2267 2268 <b>Example usage</b> 2269 @code 2270 UINT64 Msr; 2271 2272 Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C12_PMON_BOX_CTL); 2273 AsmWriteMsr64 (MSR_IVY_BRIDGE_C12_PMON_BOX_CTL, Msr); 2274 @endcode 2275 @note MSR_IVY_BRIDGE_C12_PMON_BOX_CTL is defined as MSR_C12_PMON_BOX_CTL in SDM. 2276 **/ 2277 #define MSR_IVY_BRIDGE_C12_PMON_BOX_CTL 0x00000E84 2278 2279 2280 /** 2281 Package. Uncore C-box 12 perfmon event select for C-box 12 counter 0. 2282 2283 @param ECX MSR_IVY_BRIDGE_C12_PMON_EVNTSEL0 (0x00000E90) 2284 @param EAX Lower 32-bits of MSR value. 2285 @param EDX Upper 32-bits of MSR value. 2286 2287 <b>Example usage</b> 2288 @code 2289 UINT64 Msr; 2290 2291 Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C12_PMON_EVNTSEL0); 2292 AsmWriteMsr64 (MSR_IVY_BRIDGE_C12_PMON_EVNTSEL0, Msr); 2293 @endcode 2294 @note MSR_IVY_BRIDGE_C12_PMON_EVNTSEL0 is defined as MSR_C12_PMON_EVNTSEL0 in SDM. 2295 **/ 2296 #define MSR_IVY_BRIDGE_C12_PMON_EVNTSEL0 0x00000E90 2297 2298 2299 /** 2300 Package. Uncore C-box 12 perfmon event select for C-box 12 counter 1. 2301 2302 @param ECX MSR_IVY_BRIDGE_C12_PMON_EVNTSEL1 (0x00000E91) 2303 @param EAX Lower 32-bits of MSR value. 2304 @param EDX Upper 32-bits of MSR value. 2305 2306 <b>Example usage</b> 2307 @code 2308 UINT64 Msr; 2309 2310 Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C12_PMON_EVNTSEL1); 2311 AsmWriteMsr64 (MSR_IVY_BRIDGE_C12_PMON_EVNTSEL1, Msr); 2312 @endcode 2313 @note MSR_IVY_BRIDGE_C12_PMON_EVNTSEL1 is defined as MSR_C12_PMON_EVNTSEL1 in SDM. 2314 **/ 2315 #define MSR_IVY_BRIDGE_C12_PMON_EVNTSEL1 0x00000E91 2316 2317 2318 /** 2319 Package. Uncore C-box 12 perfmon event select for C-box 12 counter 2. 2320 2321 @param ECX MSR_IVY_BRIDGE_C12_PMON_EVNTSEL2 (0x00000E92) 2322 @param EAX Lower 32-bits of MSR value. 2323 @param EDX Upper 32-bits of MSR value. 2324 2325 <b>Example usage</b> 2326 @code 2327 UINT64 Msr; 2328 2329 Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C12_PMON_EVNTSEL2); 2330 AsmWriteMsr64 (MSR_IVY_BRIDGE_C12_PMON_EVNTSEL2, Msr); 2331 @endcode 2332 @note MSR_IVY_BRIDGE_C12_PMON_EVNTSEL2 is defined as MSR_C12_PMON_EVNTSEL2 in SDM. 2333 **/ 2334 #define MSR_IVY_BRIDGE_C12_PMON_EVNTSEL2 0x00000E92 2335 2336 2337 /** 2338 Package. Uncore C-box 12 perfmon event select for C-box 12 counter 3. 2339 2340 @param ECX MSR_IVY_BRIDGE_C12_PMON_EVNTSEL3 (0x00000E93) 2341 @param EAX Lower 32-bits of MSR value. 2342 @param EDX Upper 32-bits of MSR value. 2343 2344 <b>Example usage</b> 2345 @code 2346 UINT64 Msr; 2347 2348 Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C12_PMON_EVNTSEL3); 2349 AsmWriteMsr64 (MSR_IVY_BRIDGE_C12_PMON_EVNTSEL3, Msr); 2350 @endcode 2351 @note MSR_IVY_BRIDGE_C12_PMON_EVNTSEL3 is defined as MSR_C12_PMON_EVNTSEL3 in SDM. 2352 **/ 2353 #define MSR_IVY_BRIDGE_C12_PMON_EVNTSEL3 0x00000E93 2354 2355 2356 /** 2357 Package. Uncore C-box 12 perfmon box wide filter. 2358 2359 @param ECX MSR_IVY_BRIDGE_C12_PMON_BOX_FILTER (0x00000E94) 2360 @param EAX Lower 32-bits of MSR value. 2361 @param EDX Upper 32-bits of MSR value. 2362 2363 <b>Example usage</b> 2364 @code 2365 UINT64 Msr; 2366 2367 Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C12_PMON_BOX_FILTER); 2368 AsmWriteMsr64 (MSR_IVY_BRIDGE_C12_PMON_BOX_FILTER, Msr); 2369 @endcode 2370 @note MSR_IVY_BRIDGE_C12_PMON_BOX_FILTER is defined as MSR_C12_PMON_BOX_FILTER in SDM. 2371 **/ 2372 #define MSR_IVY_BRIDGE_C12_PMON_BOX_FILTER 0x00000E94 2373 2374 2375 /** 2376 Package. Uncore C-box 12 perfmon counter 0. 2377 2378 @param ECX MSR_IVY_BRIDGE_C12_PMON_CTR0 (0x00000E96) 2379 @param EAX Lower 32-bits of MSR value. 2380 @param EDX Upper 32-bits of MSR value. 2381 2382 <b>Example usage</b> 2383 @code 2384 UINT64 Msr; 2385 2386 Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C12_PMON_CTR0); 2387 AsmWriteMsr64 (MSR_IVY_BRIDGE_C12_PMON_CTR0, Msr); 2388 @endcode 2389 @note MSR_IVY_BRIDGE_C12_PMON_CTR0 is defined as MSR_C12_PMON_CTR0 in SDM. 2390 **/ 2391 #define MSR_IVY_BRIDGE_C12_PMON_CTR0 0x00000E96 2392 2393 2394 /** 2395 Package. Uncore C-box 12 perfmon counter 1. 2396 2397 @param ECX MSR_IVY_BRIDGE_C12_PMON_CTR1 (0x00000E97) 2398 @param EAX Lower 32-bits of MSR value. 2399 @param EDX Upper 32-bits of MSR value. 2400 2401 <b>Example usage</b> 2402 @code 2403 UINT64 Msr; 2404 2405 Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C12_PMON_CTR1); 2406 AsmWriteMsr64 (MSR_IVY_BRIDGE_C12_PMON_CTR1, Msr); 2407 @endcode 2408 @note MSR_IVY_BRIDGE_C12_PMON_CTR1 is defined as MSR_C12_PMON_CTR1 in SDM. 2409 **/ 2410 #define MSR_IVY_BRIDGE_C12_PMON_CTR1 0x00000E97 2411 2412 2413 /** 2414 Package. Uncore C-box 12 perfmon counter 2. 2415 2416 @param ECX MSR_IVY_BRIDGE_C12_PMON_CTR2 (0x00000E98) 2417 @param EAX Lower 32-bits of MSR value. 2418 @param EDX Upper 32-bits of MSR value. 2419 2420 <b>Example usage</b> 2421 @code 2422 UINT64 Msr; 2423 2424 Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C12_PMON_CTR2); 2425 AsmWriteMsr64 (MSR_IVY_BRIDGE_C12_PMON_CTR2, Msr); 2426 @endcode 2427 @note MSR_IVY_BRIDGE_C12_PMON_CTR2 is defined as MSR_C12_PMON_CTR2 in SDM. 2428 **/ 2429 #define MSR_IVY_BRIDGE_C12_PMON_CTR2 0x00000E98 2430 2431 2432 /** 2433 Package. Uncore C-box 12 perfmon counter 3. 2434 2435 @param ECX MSR_IVY_BRIDGE_C12_PMON_CTR3 (0x00000E99) 2436 @param EAX Lower 32-bits of MSR value. 2437 @param EDX Upper 32-bits of MSR value. 2438 2439 <b>Example usage</b> 2440 @code 2441 UINT64 Msr; 2442 2443 Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C12_PMON_CTR3); 2444 AsmWriteMsr64 (MSR_IVY_BRIDGE_C12_PMON_CTR3, Msr); 2445 @endcode 2446 @note MSR_IVY_BRIDGE_C12_PMON_CTR3 is defined as MSR_C12_PMON_CTR3 in SDM. 2447 **/ 2448 #define MSR_IVY_BRIDGE_C12_PMON_CTR3 0x00000E99 2449 2450 2451 /** 2452 Package. Uncore C-box 12 perfmon box wide filter1. 2453 2454 @param ECX MSR_IVY_BRIDGE_C12_PMON_BOX_FILTER1 (0x00000E9A) 2455 @param EAX Lower 32-bits of MSR value. 2456 @param EDX Upper 32-bits of MSR value. 2457 2458 <b>Example usage</b> 2459 @code 2460 UINT64 Msr; 2461 2462 Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C12_PMON_BOX_FILTER1); 2463 AsmWriteMsr64 (MSR_IVY_BRIDGE_C12_PMON_BOX_FILTER1, Msr); 2464 @endcode 2465 @note MSR_IVY_BRIDGE_C12_PMON_BOX_FILTER1 is defined as MSR_C12_PMON_BOX_FILTER1 in SDM. 2466 **/ 2467 #define MSR_IVY_BRIDGE_C12_PMON_BOX_FILTER1 0x00000E9A 2468 2469 2470 /** 2471 Package. Uncore C-box 13 perfmon local box wide control. 2472 2473 @param ECX MSR_IVY_BRIDGE_C13_PMON_BOX_CTL (0x00000EA4) 2474 @param EAX Lower 32-bits of MSR value. 2475 @param EDX Upper 32-bits of MSR value. 2476 2477 <b>Example usage</b> 2478 @code 2479 UINT64 Msr; 2480 2481 Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C13_PMON_BOX_CTL); 2482 AsmWriteMsr64 (MSR_IVY_BRIDGE_C13_PMON_BOX_CTL, Msr); 2483 @endcode 2484 @note MSR_IVY_BRIDGE_C13_PMON_BOX_CTL is defined as MSR_C13_PMON_BOX_CTL in SDM. 2485 **/ 2486 #define MSR_IVY_BRIDGE_C13_PMON_BOX_CTL 0x00000EA4 2487 2488 2489 /** 2490 Package. Uncore C-box 13 perfmon event select for C-box 13 counter 0. 2491 2492 @param ECX MSR_IVY_BRIDGE_C13_PMON_EVNTSEL0 (0x00000EB0) 2493 @param EAX Lower 32-bits of MSR value. 2494 @param EDX Upper 32-bits of MSR value. 2495 2496 <b>Example usage</b> 2497 @code 2498 UINT64 Msr; 2499 2500 Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C13_PMON_EVNTSEL0); 2501 AsmWriteMsr64 (MSR_IVY_BRIDGE_C13_PMON_EVNTSEL0, Msr); 2502 @endcode 2503 @note MSR_IVY_BRIDGE_C13_PMON_EVNTSEL0 is defined as MSR_C13_PMON_EVNTSEL0 in SDM. 2504 **/ 2505 #define MSR_IVY_BRIDGE_C13_PMON_EVNTSEL0 0x00000EB0 2506 2507 2508 /** 2509 Package. Uncore C-box 13 perfmon event select for C-box 13 counter 1. 2510 2511 @param ECX MSR_IVY_BRIDGE_C13_PMON_EVNTSEL1 (0x00000EB1) 2512 @param EAX Lower 32-bits of MSR value. 2513 @param EDX Upper 32-bits of MSR value. 2514 2515 <b>Example usage</b> 2516 @code 2517 UINT64 Msr; 2518 2519 Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C13_PMON_EVNTSEL1); 2520 AsmWriteMsr64 (MSR_IVY_BRIDGE_C13_PMON_EVNTSEL1, Msr); 2521 @endcode 2522 @note MSR_IVY_BRIDGE_C13_PMON_EVNTSEL1 is defined as MSR_C13_PMON_EVNTSEL1 in SDM. 2523 **/ 2524 #define MSR_IVY_BRIDGE_C13_PMON_EVNTSEL1 0x00000EB1 2525 2526 2527 /** 2528 Package. Uncore C-box 13 perfmon event select for C-box 13 counter 2. 2529 2530 @param ECX MSR_IVY_BRIDGE_C13_PMON_EVNTSEL2 (0x00000EB2) 2531 @param EAX Lower 32-bits of MSR value. 2532 @param EDX Upper 32-bits of MSR value. 2533 2534 <b>Example usage</b> 2535 @code 2536 UINT64 Msr; 2537 2538 Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C13_PMON_EVNTSEL2); 2539 AsmWriteMsr64 (MSR_IVY_BRIDGE_C13_PMON_EVNTSEL2, Msr); 2540 @endcode 2541 @note MSR_IVY_BRIDGE_C13_PMON_EVNTSEL2 is defined as MSR_C13_PMON_EVNTSEL2 in SDM. 2542 **/ 2543 #define MSR_IVY_BRIDGE_C13_PMON_EVNTSEL2 0x00000EB2 2544 2545 2546 /** 2547 Package. Uncore C-box 13 perfmon event select for C-box 13 counter 3. 2548 2549 @param ECX MSR_IVY_BRIDGE_C13_PMON_EVNTSEL3 (0x00000EB3) 2550 @param EAX Lower 32-bits of MSR value. 2551 @param EDX Upper 32-bits of MSR value. 2552 2553 <b>Example usage</b> 2554 @code 2555 UINT64 Msr; 2556 2557 Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C13_PMON_EVNTSEL3); 2558 AsmWriteMsr64 (MSR_IVY_BRIDGE_C13_PMON_EVNTSEL3, Msr); 2559 @endcode 2560 @note MSR_IVY_BRIDGE_C13_PMON_EVNTSEL3 is defined as MSR_C13_PMON_EVNTSEL3 in SDM. 2561 **/ 2562 #define MSR_IVY_BRIDGE_C13_PMON_EVNTSEL3 0x00000EB3 2563 2564 2565 /** 2566 Package. Uncore C-box 13 perfmon box wide filter. 2567 2568 @param ECX MSR_IVY_BRIDGE_C13_PMON_BOX_FILTER (0x00000EB4) 2569 @param EAX Lower 32-bits of MSR value. 2570 @param EDX Upper 32-bits of MSR value. 2571 2572 <b>Example usage</b> 2573 @code 2574 UINT64 Msr; 2575 2576 Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C13_PMON_BOX_FILTER); 2577 AsmWriteMsr64 (MSR_IVY_BRIDGE_C13_PMON_BOX_FILTER, Msr); 2578 @endcode 2579 @note MSR_IVY_BRIDGE_C13_PMON_BOX_FILTER is defined as MSR_C13_PMON_BOX_FILTER in SDM. 2580 **/ 2581 #define MSR_IVY_BRIDGE_C13_PMON_BOX_FILTER 0x00000EB4 2582 2583 2584 /** 2585 Package. Uncore C-box 13 perfmon counter 0. 2586 2587 @param ECX MSR_IVY_BRIDGE_C13_PMON_CTR0 (0x00000EB6) 2588 @param EAX Lower 32-bits of MSR value. 2589 @param EDX Upper 32-bits of MSR value. 2590 2591 <b>Example usage</b> 2592 @code 2593 UINT64 Msr; 2594 2595 Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C13_PMON_CTR0); 2596 AsmWriteMsr64 (MSR_IVY_BRIDGE_C13_PMON_CTR0, Msr); 2597 @endcode 2598 @note MSR_IVY_BRIDGE_C13_PMON_CTR0 is defined as MSR_C13_PMON_CTR0 in SDM. 2599 **/ 2600 #define MSR_IVY_BRIDGE_C13_PMON_CTR0 0x00000EB6 2601 2602 2603 /** 2604 Package. Uncore C-box 13 perfmon counter 1. 2605 2606 @param ECX MSR_IVY_BRIDGE_C13_PMON_CTR1 (0x00000EB7) 2607 @param EAX Lower 32-bits of MSR value. 2608 @param EDX Upper 32-bits of MSR value. 2609 2610 <b>Example usage</b> 2611 @code 2612 UINT64 Msr; 2613 2614 Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C13_PMON_CTR1); 2615 AsmWriteMsr64 (MSR_IVY_BRIDGE_C13_PMON_CTR1, Msr); 2616 @endcode 2617 @note MSR_IVY_BRIDGE_C13_PMON_CTR1 is defined as MSR_C13_PMON_CTR1 in SDM. 2618 **/ 2619 #define MSR_IVY_BRIDGE_C13_PMON_CTR1 0x00000EB7 2620 2621 2622 /** 2623 Package. Uncore C-box 13 perfmon counter 2. 2624 2625 @param ECX MSR_IVY_BRIDGE_C13_PMON_CTR2 (0x00000EB8) 2626 @param EAX Lower 32-bits of MSR value. 2627 @param EDX Upper 32-bits of MSR value. 2628 2629 <b>Example usage</b> 2630 @code 2631 UINT64 Msr; 2632 2633 Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C13_PMON_CTR2); 2634 AsmWriteMsr64 (MSR_IVY_BRIDGE_C13_PMON_CTR2, Msr); 2635 @endcode 2636 @note MSR_IVY_BRIDGE_C13_PMON_CTR2 is defined as MSR_C13_PMON_CTR2 in SDM. 2637 **/ 2638 #define MSR_IVY_BRIDGE_C13_PMON_CTR2 0x00000EB8 2639 2640 2641 /** 2642 Package. Uncore C-box 13 perfmon counter 3. 2643 2644 @param ECX MSR_IVY_BRIDGE_C13_PMON_CTR3 (0x00000EB9) 2645 @param EAX Lower 32-bits of MSR value. 2646 @param EDX Upper 32-bits of MSR value. 2647 2648 <b>Example usage</b> 2649 @code 2650 UINT64 Msr; 2651 2652 Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C13_PMON_CTR3); 2653 AsmWriteMsr64 (MSR_IVY_BRIDGE_C13_PMON_CTR3, Msr); 2654 @endcode 2655 @note MSR_IVY_BRIDGE_C13_PMON_CTR3 is defined as MSR_C13_PMON_CTR3 in SDM. 2656 **/ 2657 #define MSR_IVY_BRIDGE_C13_PMON_CTR3 0x00000EB9 2658 2659 2660 /** 2661 Package. Uncore C-box 13 perfmon box wide filter1. 2662 2663 @param ECX MSR_IVY_BRIDGE_C13_PMON_BOX_FILTER1 (0x00000EBA) 2664 @param EAX Lower 32-bits of MSR value. 2665 @param EDX Upper 32-bits of MSR value. 2666 2667 <b>Example usage</b> 2668 @code 2669 UINT64 Msr; 2670 2671 Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C13_PMON_BOX_FILTER1); 2672 AsmWriteMsr64 (MSR_IVY_BRIDGE_C13_PMON_BOX_FILTER1, Msr); 2673 @endcode 2674 @note MSR_IVY_BRIDGE_C13_PMON_BOX_FILTER1 is defined as MSR_C13_PMON_BOX_FILTER1 in SDM. 2675 **/ 2676 #define MSR_IVY_BRIDGE_C13_PMON_BOX_FILTER1 0x00000EBA 2677 2678 2679 /** 2680 Package. Uncore C-box 14 perfmon local box wide control. 2681 2682 @param ECX MSR_IVY_BRIDGE_C14_PMON_BOX_CTL (0x00000EC4) 2683 @param EAX Lower 32-bits of MSR value. 2684 @param EDX Upper 32-bits of MSR value. 2685 2686 <b>Example usage</b> 2687 @code 2688 UINT64 Msr; 2689 2690 Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C14_PMON_BOX_CTL); 2691 AsmWriteMsr64 (MSR_IVY_BRIDGE_C14_PMON_BOX_CTL, Msr); 2692 @endcode 2693 @note MSR_IVY_BRIDGE_C14_PMON_BOX_CTL is defined as MSR_C14_PMON_BOX_CTL in SDM. 2694 **/ 2695 #define MSR_IVY_BRIDGE_C14_PMON_BOX_CTL 0x00000EC4 2696 2697 2698 /** 2699 Package. Uncore C-box 14 perfmon event select for C-box 14 counter 0. 2700 2701 @param ECX MSR_IVY_BRIDGE_C14_PMON_EVNTSEL0 (0x00000ED0) 2702 @param EAX Lower 32-bits of MSR value. 2703 @param EDX Upper 32-bits of MSR value. 2704 2705 <b>Example usage</b> 2706 @code 2707 UINT64 Msr; 2708 2709 Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C14_PMON_EVNTSEL0); 2710 AsmWriteMsr64 (MSR_IVY_BRIDGE_C14_PMON_EVNTSEL0, Msr); 2711 @endcode 2712 @note MSR_IVY_BRIDGE_C14_PMON_EVNTSEL0 is defined as MSR_C14_PMON_EVNTSEL0 in SDM. 2713 **/ 2714 #define MSR_IVY_BRIDGE_C14_PMON_EVNTSEL0 0x00000ED0 2715 2716 2717 /** 2718 Package. Uncore C-box 14 perfmon event select for C-box 14 counter 1. 2719 2720 @param ECX MSR_IVY_BRIDGE_C14_PMON_EVNTSEL1 (0x00000ED1) 2721 @param EAX Lower 32-bits of MSR value. 2722 @param EDX Upper 32-bits of MSR value. 2723 2724 <b>Example usage</b> 2725 @code 2726 UINT64 Msr; 2727 2728 Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C14_PMON_EVNTSEL1); 2729 AsmWriteMsr64 (MSR_IVY_BRIDGE_C14_PMON_EVNTSEL1, Msr); 2730 @endcode 2731 @note MSR_IVY_BRIDGE_C14_PMON_EVNTSEL1 is defined as MSR_C14_PMON_EVNTSEL1 in SDM. 2732 **/ 2733 #define MSR_IVY_BRIDGE_C14_PMON_EVNTSEL1 0x00000ED1 2734 2735 2736 /** 2737 Package. Uncore C-box 14 perfmon event select for C-box 14 counter 2. 2738 2739 @param ECX MSR_IVY_BRIDGE_C14_PMON_EVNTSEL2 (0x00000ED2) 2740 @param EAX Lower 32-bits of MSR value. 2741 @param EDX Upper 32-bits of MSR value. 2742 2743 <b>Example usage</b> 2744 @code 2745 UINT64 Msr; 2746 2747 Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C14_PMON_EVNTSEL2); 2748 AsmWriteMsr64 (MSR_IVY_BRIDGE_C14_PMON_EVNTSEL2, Msr); 2749 @endcode 2750 @note MSR_IVY_BRIDGE_C14_PMON_EVNTSEL2 is defined as MSR_C14_PMON_EVNTSEL2 in SDM. 2751 **/ 2752 #define MSR_IVY_BRIDGE_C14_PMON_EVNTSEL2 0x00000ED2 2753 2754 2755 /** 2756 Package. Uncore C-box 14 perfmon event select for C-box 14 counter 3. 2757 2758 @param ECX MSR_IVY_BRIDGE_C14_PMON_EVNTSEL3 (0x00000ED3) 2759 @param EAX Lower 32-bits of MSR value. 2760 @param EDX Upper 32-bits of MSR value. 2761 2762 <b>Example usage</b> 2763 @code 2764 UINT64 Msr; 2765 2766 Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C14_PMON_EVNTSEL3); 2767 AsmWriteMsr64 (MSR_IVY_BRIDGE_C14_PMON_EVNTSEL3, Msr); 2768 @endcode 2769 @note MSR_IVY_BRIDGE_C14_PMON_EVNTSEL3 is defined as MSR_C14_PMON_EVNTSEL3 in SDM. 2770 **/ 2771 #define MSR_IVY_BRIDGE_C14_PMON_EVNTSEL3 0x00000ED3 2772 2773 2774 /** 2775 Package. Uncore C-box 14 perfmon box wide filter. 2776 2777 @param ECX MSR_IVY_BRIDGE_C14_PMON_BOX_FILTER (0x00000ED4) 2778 @param EAX Lower 32-bits of MSR value. 2779 @param EDX Upper 32-bits of MSR value. 2780 2781 <b>Example usage</b> 2782 @code 2783 UINT64 Msr; 2784 2785 Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C14_PMON_BOX_FILTER); 2786 AsmWriteMsr64 (MSR_IVY_BRIDGE_C14_PMON_BOX_FILTER, Msr); 2787 @endcode 2788 @note MSR_IVY_BRIDGE_C14_PMON_BOX_FILTER is defined as MSR_C14_PMON_BOX_FILTER in SDM. 2789 **/ 2790 #define MSR_IVY_BRIDGE_C14_PMON_BOX_FILTER 0x00000ED4 2791 2792 2793 /** 2794 Package. Uncore C-box 14 perfmon counter 0. 2795 2796 @param ECX MSR_IVY_BRIDGE_C14_PMON_CTR0 (0x00000ED6) 2797 @param EAX Lower 32-bits of MSR value. 2798 @param EDX Upper 32-bits of MSR value. 2799 2800 <b>Example usage</b> 2801 @code 2802 UINT64 Msr; 2803 2804 Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C14_PMON_CTR0); 2805 AsmWriteMsr64 (MSR_IVY_BRIDGE_C14_PMON_CTR0, Msr); 2806 @endcode 2807 @note MSR_IVY_BRIDGE_C14_PMON_CTR0 is defined as MSR_C14_PMON_CTR0 in SDM. 2808 **/ 2809 #define MSR_IVY_BRIDGE_C14_PMON_CTR0 0x00000ED6 2810 2811 2812 /** 2813 Package. Uncore C-box 14 perfmon counter 1. 2814 2815 @param ECX MSR_IVY_BRIDGE_C14_PMON_CTR1 (0x00000ED7) 2816 @param EAX Lower 32-bits of MSR value. 2817 @param EDX Upper 32-bits of MSR value. 2818 2819 <b>Example usage</b> 2820 @code 2821 UINT64 Msr; 2822 2823 Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C14_PMON_CTR1); 2824 AsmWriteMsr64 (MSR_IVY_BRIDGE_C14_PMON_CTR1, Msr); 2825 @endcode 2826 @note MSR_IVY_BRIDGE_C14_PMON_CTR1 is defined as MSR_C14_PMON_CTR1 in SDM. 2827 **/ 2828 #define MSR_IVY_BRIDGE_C14_PMON_CTR1 0x00000ED7 2829 2830 2831 /** 2832 Package. Uncore C-box 14 perfmon counter 2. 2833 2834 @param ECX MSR_IVY_BRIDGE_C14_PMON_CTR2 (0x00000ED8) 2835 @param EAX Lower 32-bits of MSR value. 2836 @param EDX Upper 32-bits of MSR value. 2837 2838 <b>Example usage</b> 2839 @code 2840 UINT64 Msr; 2841 2842 Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C14_PMON_CTR2); 2843 AsmWriteMsr64 (MSR_IVY_BRIDGE_C14_PMON_CTR2, Msr); 2844 @endcode 2845 @note MSR_IVY_BRIDGE_C14_PMON_CTR2 is defined as MSR_C14_PMON_CTR2 in SDM. 2846 **/ 2847 #define MSR_IVY_BRIDGE_C14_PMON_CTR2 0x00000ED8 2848 2849 2850 /** 2851 Package. Uncore C-box 14 perfmon counter 3. 2852 2853 @param ECX MSR_IVY_BRIDGE_C14_PMON_CTR3 (0x00000ED9) 2854 @param EAX Lower 32-bits of MSR value. 2855 @param EDX Upper 32-bits of MSR value. 2856 2857 <b>Example usage</b> 2858 @code 2859 UINT64 Msr; 2860 2861 Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C14_PMON_CTR3); 2862 AsmWriteMsr64 (MSR_IVY_BRIDGE_C14_PMON_CTR3, Msr); 2863 @endcode 2864 @note MSR_IVY_BRIDGE_C14_PMON_CTR3 is defined as MSR_C14_PMON_CTR3 in SDM. 2865 **/ 2866 #define MSR_IVY_BRIDGE_C14_PMON_CTR3 0x00000ED9 2867 2868 2869 /** 2870 Package. Uncore C-box 14 perfmon box wide filter1. 2871 2872 @param ECX MSR_IVY_BRIDGE_C14_PMON_BOX_FILTER1 (0x00000EDA) 2873 @param EAX Lower 32-bits of MSR value. 2874 @param EDX Upper 32-bits of MSR value. 2875 2876 <b>Example usage</b> 2877 @code 2878 UINT64 Msr; 2879 2880 Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C14_PMON_BOX_FILTER1); 2881 AsmWriteMsr64 (MSR_IVY_BRIDGE_C14_PMON_BOX_FILTER1, Msr); 2882 @endcode 2883 @note MSR_IVY_BRIDGE_C14_PMON_BOX_FILTER1 is defined as MSR_C14_PMON_BOX_FILTER1 in SDM. 2884 **/ 2885 #define MSR_IVY_BRIDGE_C14_PMON_BOX_FILTER1 0x00000EDA 2886 2887 #endif 2888