1 /** @file 2 Platform PEI module include file. 3 4 Copyright (c) 2006 - 2019 Intel Corporation. All rights reserved. <BR> 5 6 SPDX-License-Identifier: BSD-2-Clause-Patent 7 **/ 8 9 #ifndef _PLATFORM_PEI_H_INCLUDED_ 10 #define _PLATFORM_PEI_H_INCLUDED_ 11 12 VOID 13 AddIoMemoryBaseSizeHob ( 14 EFI_PHYSICAL_ADDRESS MemoryBase, 15 UINT64 MemorySize 16 ); 17 18 VOID 19 AddIoMemoryRangeHob ( 20 EFI_PHYSICAL_ADDRESS MemoryBase, 21 EFI_PHYSICAL_ADDRESS MemoryLimit 22 ); 23 24 VOID 25 AddMemoryBaseSizeHob ( 26 EFI_PHYSICAL_ADDRESS MemoryBase, 27 UINT64 MemorySize 28 ); 29 30 VOID 31 AddMemoryRangeHob ( 32 EFI_PHYSICAL_ADDRESS MemoryBase, 33 EFI_PHYSICAL_ADDRESS MemoryLimit 34 ); 35 36 VOID 37 AddUntestedMemoryBaseSizeHob ( 38 EFI_PHYSICAL_ADDRESS MemoryBase, 39 UINT64 MemorySize 40 ); 41 42 VOID 43 AddReservedMemoryBaseSizeHob ( 44 EFI_PHYSICAL_ADDRESS MemoryBase, 45 UINT64 MemorySize, 46 BOOLEAN Cacheable 47 ); 48 49 VOID 50 AddressWidthInitialization ( 51 VOID 52 ); 53 54 VOID 55 X58TsegMbytesInitialization ( 56 VOID 57 ); 58 59 EFI_STATUS 60 PublishPeiMemory ( 61 VOID 62 ); 63 64 UINT32 65 GetSystemMemorySizeBelow4gb ( 66 VOID 67 ); 68 69 VOID 70 InitializeRamRegions ( 71 VOID 72 ); 73 74 VOID 75 InstallFeatureControlCallback ( 76 VOID 77 ); 78 79 extern EFI_BOOT_MODE mBootMode; 80 81 extern BOOLEAN mS3Supported; 82 83 extern UINT8 mPhysMemAddressWidth; 84 85 extern UINT32 mMaxCpuCount; 86 87 extern UINT16 mHostBridgeDevId; 88 #endif // _PLATFORM_PEI_H_INCLUDED_ 89