1 /** @file 2 * Platform headers 3 * 4 * Copyright 2020 NXP 5 * Copyright 2020 Puresoftware Ltd 6 * 7 * SPDX-License-Identifier: BSD-2-Clause-Patent 8 * 9 **/ 10 11 12 #ifndef LX2160ARDB_PLATFORM_H 13 #define LX2160ARDB_PLATFORM_H 14 15 #define EFI_ACPI_ARM_OEM_REVISION 0x00000000 16 17 // Soc defines 18 #define SVR_SOC_VER(svr) (((svr) >> 8) & 0xFFFFFE) 19 #define SVR_MAJOR(svr) (((svr) >> 4) & 0xf) 20 #define SVR_MINOR(svr) (((svr) >> 0) & 0xf) 21 22 #define SVR_LX2160A 0x873600 23 24 // PCLK 25 #define DCFG_BASE 0x1E00000 26 #define DCFG_LEN 0x1FFFF 27 28 // Gic 29 #define GIC_VERSION 3 30 #define GICD_BASE 0x6000000 31 #define GICI_BASE 0x6020000 32 #define GICR_BASE 0x06200000 33 #define GICR_LEN 0x200000 34 #define GICC_BASE 0x0c0c0000 35 #define GICH_BASE 0x0c0d0000 36 #define GICV_BASE 0x0c0e0000 37 38 // UART 39 #define UART0_BASE 0x21C0000 40 #define UART1_BASE 0x21D0000 41 #define UART2_BASE 0x21E0000 42 #define UART3_BASE 0x21F0000 43 #define UART0_IT 64 44 #define UART1_IT 65 45 #define UART2_IT 104 46 #define UART3_IT 105 47 #define UART_LEN 0x10000 48 #define SPCR_FLOW_CONTROL_NONE 0 49 50 // Timer 51 #define TIMER_BLOCK_COUNT 1 52 #define TIMER_FRAME_COUNT 4 53 #define TIMER_WATCHDOG_COUNT 1 54 #define TIMER_BASE_ADDRESS 0x23E0000 // a.k.a CNTControlBase 55 #define TIMER_READ_BASE_ADDRESS 0x23F0000 // a.k.a CNTReadBase 56 #define TIMER_GT_BLOCK_0_ADDRESS 0x2890000 // a.k.a CNTCTLBase (Secure) 57 #define TIMER_GT_BASE_0_ADDRESS 0x28A0000 // a.k.a CNTBase0 58 #define TIMER_GT_BASE_1_ADDRESS 0x28B0000 // a.k.a CNTBase1 59 #define TIMER_GT_BASE_2_ADDRESS 0x28C0000 // a.k.a CNTBase2 60 #define TIMER_GT_BASE_3_ADDRESS 0x28D0000 // a.k.a CNTBase3 61 #define TIMER_GT_BASE_0_EL0_ADDRESS 0x28E0000 // a.k.a CNTBase0EL0 62 #define TIMER_GT_BASE_2_EL0_ADDRESS 0x28F0000 // a.k.a CNTBase2EL0 63 #define TIMER_WDT0_REFRESH_BASE 0x2390000 64 #define TIMER_WDT0_CONTROL_BASE 0x23A0000 65 #define TIMER_SEC_IT 29 66 #define TIMER_NON_SEC_IT 30 67 #define TIMER_VIRT_IT 27 68 #define TIMER_HYP_IT 26 69 #define TIMER_FRAME0_IT 78 70 #define TIMER_FRAME1_IT 79 71 #define TIMER_FRAME2_IT 92 72 #define TIMER_FRAME3_IT 93 73 #define TIMER_WDT0_IT 91 74 75 #define DEFAULT_PLAT_FREQ 700000000 76 77 // Mcfg 78 #define LX2160A_PCI_SEG0_CONFIG_BASE 0x9000000000 79 #define LX2160A_PCI_SEG0 0x2 80 #define LX2160A_PCI_SEG_BUSNUM_MIN 0x0 81 #define LX2160A_PCI_SEG_BUSNUM_MAX 0xff 82 #define LX2160A_PCI_SEG1_CONFIG_BASE 0xA000000000 83 #define LX2160A_PCI_SEG1 0x4 84 85 // Platform specific info needed by Configuration Manager 86 87 #define OEM_ACPI_TABLES 1 // OEM defined DSDT 88 89 #define CFG_MGR_TABLE_ID SIGNATURE_64 ('L','X','2','1','6','0',' ',' ') 90 91 #define PLAT_PCI_SEG0_CONFIG_BASE LX2160A_PCI_SEG0_CONFIG_BASE 92 #define PLAT_PCI_SEG0 LX2160A_PCI_SEG0 93 #define PLAT_PCI_SEG_BUSNUM_MIN LX2160A_PCI_SEG_BUSNUM_MIN 94 #define PLAT_PCI_SEG_BUSNUM_MAX LX2160A_PCI_SEG_BUSNUM_MAX 95 #define PLAT_PCI_SEG1_CONFIG_BASE LX2160A_PCI_SEG1_CONFIG_BASE 96 #define PLAT_PCI_SEG1 LX2160A_PCI_SEG1 97 98 #define PLAT_GIC_VERSION GIC_VERSION 99 #define PLAT_GICD_BASE GICD_BASE 100 #define PLAT_GICI_BASE GICI_BASE 101 #define PLAT_GICR_BASE GICR_BASE 102 #define PLAT_GICR_LEN GICR_LEN 103 #define PLAT_GICC_BASE GICC_BASE 104 #define PLAT_GICH_BASE GICH_BASE 105 #define PLAT_GICV_BASE GICV_BASE 106 107 #define PLAT_CPU_COUNT 16 108 #define PLAT_GTBLOCK_COUNT 1 109 #define PLAT_GTFRAME_COUNT 4 110 #define PLAT_PCI_CONFG_COUNT 2 111 112 #define PLAT_WATCHDOG_COUNT 1 113 #define PLAT_GIC_REDISTRIBUTOR_COUNT 1 114 #define PLAT_GIC_ITS_COUNT 1 115 116 /* GIC CPU Interface information 117 GIC_ENTRY (CPUInterfaceNumber, Mpidr, PmuIrq, VGicIrq, EnergyEfficiency) 118 */ 119 #define PLAT_GIC_CPU_INTERFACE { \ 120 GICC_ENTRY (0, GET_MPID (0, 0), 23, 0x19, 0), \ 121 GICC_ENTRY (1, GET_MPID (0, 1), 23, 0x19, 0), \ 122 GICC_ENTRY (2, GET_MPID (1, 0), 23, 0x19, 0), \ 123 GICC_ENTRY (3, GET_MPID (1, 1), 23, 0x19, 0), \ 124 GICC_ENTRY (4, GET_MPID (2, 0), 23, 0x19, 0), \ 125 GICC_ENTRY (5, GET_MPID (2, 1), 23, 0x19, 0), \ 126 GICC_ENTRY (6, GET_MPID (3, 0), 23, 0x19, 0), \ 127 GICC_ENTRY (7, GET_MPID (3, 1), 23, 0x19, 0), \ 128 GICC_ENTRY (8, GET_MPID (4, 0), 23, 0x19, 0), \ 129 GICC_ENTRY (9, GET_MPID (4, 1), 23, 0x19, 0), \ 130 GICC_ENTRY (10, GET_MPID (5, 0), 23, 0x19, 0), \ 131 GICC_ENTRY (11, GET_MPID (5, 1), 23, 0x19, 0), \ 132 GICC_ENTRY (12, GET_MPID (6, 0), 23, 0x19, 0), \ 133 GICC_ENTRY (13, GET_MPID (6, 1), 23, 0x19, 0), \ 134 GICC_ENTRY (14, GET_MPID (7, 0), 23, 0x19, 0), \ 135 GICC_ENTRY (15, GET_MPID (7, 1), 23, 0x19, 0) \ 136 } 137 138 // watchdogs 139 #define PLAT_WATCHDOG_INFO \ 140 { \ 141 TIMER_WDT0_CONTROL_BASE, \ 142 TIMER_WDT0_REFRESH_BASE, \ 143 TIMER_WDT0_IT, \ 144 SBSA_WATCHDOG_FLAGS \ 145 } \ 146 147 #define PLAT_TIMER_BLOCK_INFO \ 148 { \ 149 { \ 150 TIMER_GT_BLOCK_0_ADDRESS, \ 151 PLAT_GTFRAME_COUNT, \ 152 (CM_OBJECT_TOKEN)((UINT8*)&FslPlatformRepositoryInfo + \ 153 OFFSET_OF (EDKII_PLATFORM_REPOSITORY_INFO, GTBlock0TimerInfo)) \ 154 } \ 155 } \ 156 157 #define PLAT_TIMER_FRAME_INFO \ 158 { \ 159 { \ 160 0, /* UINT8 GTFrameNumber */ \ 161 TIMER_GT_BASE_0_ADDRESS, /* UINT64 CntBaseX */ \ 162 TIMER_GT_BASE_0_EL0_ADDRESS, /* UINT64 CntEL0BaseX */ \ 163 TIMER_FRAME0_IT, /* UINT32 GTxPhysicalTimerGSIV */ \ 164 GTDT_FRAME_FLAGS, /* UINT32 GTxPhysicalTimerFlags */ \ 165 TIMER_FRAME0_IT, /* UINT32 GTxVirtualTimerGSIV */ \ 166 GTDT_FRAME_FLAGS, /* UINT32 GTxVirtualTimerFlags */ \ 167 0 /* UINT32 GTxCommonFlags */ \ 168 }, /* Gtdt.Frames[0] */ \ 169 { \ 170 1, /* UINT8 GTFrameNumber */ \ 171 TIMER_GT_BASE_1_ADDRESS, /* UINT64 CntBaseX */ \ 172 GT_BLOCK_FRAME_RES_BASE, /* UINT64 CntEL0BaseX */ \ 173 TIMER_FRAME1_IT, /* UINT32 GTxPhysicalTimerGSIV */ \ 174 GTDT_FRAME_FLAGS, /* UINT32 GTxPhysicalTimerFlags */ \ 175 0, /* UINT32 GTxVirtualTimerGSIV */ \ 176 0, /* UINT32 GTxVirtualTimerFlags */ \ 177 GTDT_FRAME_COMMON_FLAGS /* UINT32 GTxCommonFlags */ \ 178 }, /* Gtdt.Frames[1] */ \ 179 { \ 180 2, /* UINT8 GTFrameNumber */ \ 181 TIMER_GT_BASE_2_ADDRESS, /* UINT64 CntBaseX */ \ 182 TIMER_GT_BASE_2_EL0_ADDRESS, /* UINT64 CntEL0BaseX */ \ 183 TIMER_FRAME2_IT, /* UINT32 GTxPhysicalTimerGSIV */ \ 184 GTDT_FRAME_FLAGS, /* UINT32 GTxPhysicalTimerFlags */ \ 185 0, /* UINT32 GTxVirtualTimerGSIV */ \ 186 0, /* UINT32 GTxVirtualTimerFlags */ \ 187 GTDT_FRAME_COMMON_FLAGS /* UINT32 GTxCommonFlags */ \ 188 },/* Gtdt.Frames[2] */ \ 189 { \ 190 3, /* UINT8 GTFrameNumber */ \ 191 TIMER_GT_BASE_3_ADDRESS, /* UINT64 CntBaseX */ \ 192 GT_BLOCK_FRAME_RES_BASE, /* UINT64 CntEL0BaseX */ \ 193 TIMER_FRAME3_IT, /* UINT32 GTxPhysicalTimerGSIV */ \ 194 GTDT_FRAME_FLAGS, /* UINT32 GTxPhysicalTimerFlags */ \ 195 0, /* UINT32 GTxVirtualTimerGSIV */ \ 196 0, /* UINT32 GTxVirtualTimerFlags */ \ 197 GTDT_FRAME_COMMON_FLAGS /* UINT32 GTxCommonFlags */ \ 198 }, /* Gtdt.Frames[3] */ \ 199 } \ 200 201 #define PLAT_GIC_DISTRIBUTOR_INFO \ 202 { \ 203 PLAT_GICD_BASE, /* UINT64 PhysicalBaseAddress */ \ 204 0, /* UINT32 SystemVectorBase */ \ 205 PLAT_GIC_VERSION /* UINT8 GicVersion */ \ 206 } \ 207 208 #define PLAT_GIC_REDISTRIBUTOR_INFO \ 209 { \ 210 PLAT_GICR_BASE, /* UINT64 DiscoveryRangeBaseAddress */ \ 211 PLAT_GICR_LEN /* UINT32 DiscoveryRangeLength */ \ 212 } \ 213 214 #define PLAT_GIC_ITS_INFO \ 215 { \ 216 0, /* UINT32 GIC ITS ID */ \ 217 PLAT_GICI_BASE, /* UINT64 The 64-bit physical address for ITS */ \ 218 0 /* UINT32 Populate the GIC ITS affinity in SRAT. */ \ 219 } \ 220 221 #define PLAT_MCFG_INFO \ 222 { \ 223 { \ 224 PLAT_PCI_SEG0_CONFIG_BASE, \ 225 PLAT_PCI_SEG0, \ 226 PLAT_PCI_SEG_BUSNUM_MIN, \ 227 PLAT_PCI_SEG_BUSNUM_MAX, \ 228 }, \ 229 { \ 230 PLAT_PCI_SEG1_CONFIG_BASE, \ 231 PLAT_PCI_SEG1, \ 232 PLAT_PCI_SEG_BUSNUM_MIN, \ 233 PLAT_PCI_SEG_BUSNUM_MAX, \ 234 } \ 235 } \ 236 237 #define PLAT_SPCR_INFO \ 238 { \ 239 UART0_BASE, \ 240 UART0_IT, \ 241 115200, \ 242 0, \ 243 EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_INTERFACE_TYPE_ARM_PL011_UART \ 244 } \ 245 246 #endif // LX2160ARDB_PLATFORM_H 247