1 /** @file
2   Print whole PCH_POLICY_PPI
3 
4   Copyright (c) 2019 - 2020 Intel Corporation. All rights reserved. <BR>
5 
6   SPDX-License-Identifier: BSD-2-Clause-Patent
7 **/
8 
9 #include "PeiPchPolicyLibrary.h"
10 #include <Private/PchHsio.h>
11 #include <Library/ConfigBlockLib.h>
12 
13 /**
14   Print USB_CONFIG and serial out.
15 
16   @param[in] UsbConfig         Pointer to a USB_CONFIG that provides the platform setting
17 
18 **/
19 VOID
20 PchPrintUsbConfig (
21   IN CONST USB_CONFIG     *UsbConfig
22   )
23 {
24   UINT32 Index;
25 
26   DEBUG ((DEBUG_INFO, "------------------ PCH USB Config ------------------\n"));
27   DEBUG ((DEBUG_INFO, " EnableComplianceMode           = %x\n", UsbConfig->EnableComplianceMode));
28   DEBUG ((DEBUG_INFO, " PdoProgramming                 = %x\n", UsbConfig->PdoProgramming));
29   DEBUG ((DEBUG_INFO, " OverCurrentEnable              = %x\n", UsbConfig->OverCurrentEnable));
30   DEBUG ((DEBUG_INFO, " XhciOcLock                     = %x\n", UsbConfig->XhciOcLock));
31   DEBUG ((DEBUG_INFO, " Usb2PhySusPgEnable             = %x\n", UsbConfig->Usb2PhySusPgEnable));
32 
33   for (Index = 0; Index < GetPchUsb2MaxPhysicalPortNum (); Index++) {
34     DEBUG ((DEBUG_INFO, " PortUsb20[%d].Enabled        = %x\n", Index, UsbConfig->PortUsb20[Index].Enable));
35     DEBUG ((DEBUG_INFO, " PortUsb20[%d].OverCurrentPin = OC%x\n", Index, UsbConfig->PortUsb20[Index].OverCurrentPin));
36     DEBUG ((DEBUG_INFO, " PortUsb20[%d].Afe.Petxiset   = %x\n", Index, UsbConfig->PortUsb20[Index].Afe.Petxiset));
37     DEBUG ((DEBUG_INFO, " PortUsb20[%d].Afe.Txiset     = %x\n", Index, UsbConfig->PortUsb20[Index].Afe.Txiset));
38     DEBUG ((DEBUG_INFO, " PortUsb20[%d].Afe.Predeemp   = %x\n", Index, UsbConfig->PortUsb20[Index].Afe.Predeemp));
39     DEBUG ((DEBUG_INFO, " PortUsb20[%d].Afe.Pehalfbit  = %x\n", Index, UsbConfig->PortUsb20[Index].Afe.Pehalfbit));
40   }
41 
42   for (Index = 0; Index < GetPchXhciMaxUsb3PortNum (); Index++) {
43     DEBUG ((DEBUG_INFO, " PortUsb30[%d] Enabled                  = %x\n", Index, UsbConfig->PortUsb30[Index].Enable));
44     DEBUG ((DEBUG_INFO, " PortUsb30[%d].OverCurrentPin           = OC%x\n", Index, UsbConfig->PortUsb30[Index].OverCurrentPin));
45     DEBUG ((DEBUG_INFO, " PortUsb30[%d].HsioTxDeEmphEnable       = %x\n", Index, UsbConfig->PortUsb30[Index].HsioTxDeEmphEnable));
46     DEBUG ((DEBUG_INFO, " PortUsb30[%d].HsioTxDeEmph             = %x\n", Index, UsbConfig->PortUsb30[Index].HsioTxDeEmph));
47     DEBUG ((DEBUG_INFO, " PortUsb30[%d].HsioTxDownscaleAmpEnable = %x\n", Index, UsbConfig->PortUsb30[Index].HsioTxDownscaleAmpEnable));
48     DEBUG ((DEBUG_INFO, " PortUsb30[%d].HsioTxDownscaleAmp       = %x\n", Index, UsbConfig->PortUsb30[Index].HsioTxDownscaleAmp));
49 
50     DEBUG ((DEBUG_INFO, " PortUsb30HsioRx[%d].HsioCtrlAdaptOffsetCfgEnable    = %x\n", Index, UsbConfig->PortUsb30HsioRx[Index].HsioCtrlAdaptOffsetCfgEnable));
51     DEBUG ((DEBUG_INFO, " PortUsb30HsioRx[%d].HsioCtrlAdaptOffsetCfg          = %x\n", Index, UsbConfig->PortUsb30HsioRx[Index].HsioCtrlAdaptOffsetCfg));
52     DEBUG ((DEBUG_INFO, " PortUsb30HsioRx[%d].HsioFilterSelNEnable            = %x\n", Index, UsbConfig->PortUsb30HsioRx[Index].HsioFilterSelNEnable));
53     DEBUG ((DEBUG_INFO, " PortUsb30HsioRx[%d].HsioFilterSelN                  = %x\n", Index, UsbConfig->PortUsb30HsioRx[Index].HsioFilterSelN));
54     DEBUG ((DEBUG_INFO, " PortUsb30HsioRx[%d].HsioFilterSelPEnable            = %x\n", Index, UsbConfig->PortUsb30HsioRx[Index].HsioFilterSelPEnable));
55     DEBUG ((DEBUG_INFO, " PortUsb30HsioRx[%d].HsioFilterSelP                  = %x\n", Index, UsbConfig->PortUsb30HsioRx[Index].HsioFilterSelP));
56     DEBUG ((DEBUG_INFO, " PortUsb30HsioRx[%d].HsioOlfpsCfgPullUpDwnResEnable  = %x\n", Index, UsbConfig->PortUsb30HsioRx[Index].HsioOlfpsCfgPullUpDwnResEnable));
57     DEBUG ((DEBUG_INFO, " PortUsb30HsioRx[%d].HsioOlfpsCfgPullUpDwnRes        = %x\n", Index, UsbConfig->PortUsb30HsioRx[Index].HsioOlfpsCfgPullUpDwnRes));
58   }
59 
60   DEBUG ((DEBUG_INFO, " XdciConfig.Enable= %x\n", UsbConfig->XdciConfig.Enable));
61 
62 }
63 
64 /**
65   Print PCH_PCIE_CONFIG and serial out.
66 
67   @param[in] PcieConfig         Pointer to a PCH_PCIE_CONFIG that provides the platform setting
68 
69 **/
70 VOID
71 PchPrintPcieConfig (
72   IN CONST PCH_PCIE_CONFIG      *PcieConfig
73   )
74 {
75   UINT32 Index;
76 
77   DEBUG ((DEBUG_INFO, "------------------ PCH PCIE Config ------------------\n"));
78   for (Index = 0; Index < GetPchMaxPciePortNum (); Index++) {
79     DEBUG ((DEBUG_INFO, " RootPort[%d] HotPlug= %x\n", Index, PcieConfig->RootPort[Index].HotPlug));
80     DEBUG ((DEBUG_INFO, " RootPort[%d] PmSci= %x\n", Index, PcieConfig->RootPort[Index].PmSci));
81     DEBUG ((DEBUG_INFO, " RootPort[%d] ExtSync= %x\n", Index, PcieConfig->RootPort[Index].ExtSync));
82     DEBUG ((DEBUG_INFO, " RootPort[%d] ClkReqDetect= %x\n", Index, PcieConfig->RootPort[Index].ClkReqDetect));
83     DEBUG ((DEBUG_INFO, " RootPort[%d] UnsupportedRequestReport= %x\n", Index, PcieConfig->RootPort[Index].UnsupportedRequestReport));
84     DEBUG ((DEBUG_INFO, " RootPort[%d] FatalErrorReport= %x\n", Index, PcieConfig->RootPort[Index].FatalErrorReport));
85     DEBUG ((DEBUG_INFO, " RootPort[%d] NoFatalErrorReport= %x\n", Index, PcieConfig->RootPort[Index].NoFatalErrorReport));
86     DEBUG ((DEBUG_INFO, " RootPort[%d] CorrectableErrorReport= %x\n", Index, PcieConfig->RootPort[Index].CorrectableErrorReport));
87     DEBUG ((DEBUG_INFO, " RootPort[%d] SystemErrorOnFatalError= %x\n", Index, PcieConfig->RootPort[Index].SystemErrorOnFatalError));
88     DEBUG ((DEBUG_INFO, " RootPort[%d] SystemErrorOnNonFatalError= %x\n", Index, PcieConfig->RootPort[Index].SystemErrorOnNonFatalError));
89     DEBUG ((DEBUG_INFO, " RootPort[%d] SystemErrorOnCorrectableError= %x\n", Index, PcieConfig->RootPort[Index].SystemErrorOnCorrectableError));
90     DEBUG ((DEBUG_INFO, " RootPort[%d] MaxPayload= %x\n", Index, PcieConfig->RootPort[Index].MaxPayload));
91     DEBUG ((DEBUG_INFO, " RootPort[%d] SlotImplemented= %x\n", Index, PcieConfig->RootPort[Index].SlotImplemented));
92     DEBUG ((DEBUG_INFO, " RootPort[%d] AcsEnabled= %x\n", Index, PcieConfig->RootPort[Index].AcsEnabled));
93     DEBUG ((DEBUG_INFO, " RootPort[%d] PtmEnabled= %x\n", Index, PcieConfig->RootPort[Index].PtmEnabled));
94     DEBUG ((DEBUG_INFO, " RootPort[%d] AdvancedErrorReporting= %x\n", Index, PcieConfig->RootPort[Index].AdvancedErrorReporting));
95     DEBUG ((DEBUG_INFO, " RootPort[%d] TransmitterHalfSwing= %x\n", Index, PcieConfig->RootPort[Index].TransmitterHalfSwing));
96     DEBUG ((DEBUG_INFO, " RootPort[%d] PcieSpeed= %x\n", Index, PcieConfig->RootPort[Index].PcieSpeed));
97     DEBUG ((DEBUG_INFO, " RootPort[%d] Gen3EqPh3Method= %x\n", Index, PcieConfig->RootPort[Index].Gen3EqPh3Method));
98     DEBUG ((DEBUG_INFO, " RootPort[%d] PhysicalSlotNumber= %x\n", Index, PcieConfig->RootPort[Index].PhysicalSlotNumber));
99     DEBUG ((DEBUG_INFO, " RootPort[%d] CompletionTimeout= %x\n", Index, PcieConfig->RootPort[Index].CompletionTimeout));
100     DEBUG ((DEBUG_INFO, " RootPort[%d] Aspm= %x\n", Index, PcieConfig->RootPort[Index].Aspm));
101     DEBUG ((DEBUG_INFO, " RootPort[%d] L1Substates= %x\n", Index, PcieConfig->RootPort[Index].L1Substates));
102     DEBUG ((DEBUG_INFO, " RootPort[%d] LtrEnable= %x\n", Index, PcieConfig->RootPort[Index].LtrEnable));
103     DEBUG ((DEBUG_INFO, " RootPort[%d] LtrConfigLock= %x\n", Index, PcieConfig->RootPort[Index].LtrConfigLock));
104     DEBUG ((DEBUG_INFO, " RootPort[%d] LtrMaxSnoopLatency= %x\n", Index, PcieConfig->RootPort[Index].LtrMaxSnoopLatency));
105     DEBUG ((DEBUG_INFO, " RootPort[%d] LtrMaxNoSnoopLatency= %x\n", Index, PcieConfig->RootPort[Index].LtrMaxNoSnoopLatency));
106     DEBUG ((DEBUG_INFO, " RootPort[%d] SnoopLatencyOverrideMode= %x\n", Index, PcieConfig->RootPort[Index].SnoopLatencyOverrideMode));
107     DEBUG ((DEBUG_INFO, " RootPort[%d] SnoopLatencyOverrideMultiplier= %x\n", Index, PcieConfig->RootPort[Index].SnoopLatencyOverrideMultiplier));
108     DEBUG ((DEBUG_INFO, " RootPort[%d] SnoopLatencyOverrideValue= %x\n", Index, PcieConfig->RootPort[Index].SnoopLatencyOverrideValue));
109     DEBUG ((DEBUG_INFO, " RootPort[%d] NonSnoopLatencyOverrideMode= %x\n", Index, PcieConfig->RootPort[Index].NonSnoopLatencyOverrideMode));
110     DEBUG ((DEBUG_INFO, " RootPort[%d] NonSnoopLatencyOverrideMultiplier= %x\n", Index, PcieConfig->RootPort[Index].NonSnoopLatencyOverrideMultiplier));
111     DEBUG ((DEBUG_INFO, " RootPort[%d] NonSnoopLatencyOverrideValue= %x\n", Index, PcieConfig->RootPort[Index].NonSnoopLatencyOverrideValue));
112     DEBUG ((DEBUG_INFO, " RootPort[%d] ForceLtrOverride= %x\n", Index, PcieConfig->RootPort[Index].ForceLtrOverride));
113     DEBUG ((DEBUG_INFO, " RootPort[%d] DetectTimeoutMs= %x\n", Index, PcieConfig->RootPort[Index].DetectTimeoutMs));
114     DEBUG ((DEBUG_INFO, " RootPort[%d] SlotPowerLimitScale= %x\n", Index, PcieConfig->RootPort[Index].SlotPowerLimitScale));
115     DEBUG ((DEBUG_INFO, " RootPort[%d] SlotPowerLimitValue= %x\n", Index, PcieConfig->RootPort[Index].SlotPowerLimitValue));
116     DEBUG ((DEBUG_INFO, " RootPort[%d] Uptp= %x\n", Index, PcieConfig->RootPort[Index].Uptp));
117     DEBUG ((DEBUG_INFO, " RootPort[%d] Dptp= %x\n", Index, PcieConfig->RootPort[Index].Dptp));
118     DEBUG ((DEBUG_INFO, " RootPort[%d] EnableCpm= %x\n", Index, PcieConfig->RootPort[Index].EnableCpm));
119 
120   }
121   for (Index = 0; Index < GetPchMaxPcieClockNum (); Index++) {
122     DEBUG ((DEBUG_INFO, " Clock[%d] Usage= %x\n", Index, PcieConfig->PcieClock[Index].Usage));
123     DEBUG ((DEBUG_INFO, " Clock[%d] ClkReq= %x\n", Index, PcieConfig->PcieClock[Index].ClkReq));
124   }
125   for (Index = 0; Index < PCH_PCIE_SWEQ_COEFFS_MAX; Index++) {
126     DEBUG ((DEBUG_INFO, " SwEqCoeffCm[%d] = %x\n", Index, PcieConfig->SwEqCoeffList[Index].Cm));
127     DEBUG ((DEBUG_INFO, " SwEqCoeffCp[%d] = %x\n", Index, PcieConfig->SwEqCoeffList[Index].Cp));
128   }
129   DEBUG ((DEBUG_INFO, " EnablePort8xhDecode= %x\n", PcieConfig->EnablePort8xhDecode));
130   DEBUG ((DEBUG_INFO, " PchPciePort8xhDecodePortIndex= %x\n", PcieConfig->PchPciePort8xhDecodePortIndex));
131   DEBUG ((DEBUG_INFO, " DisableRootPortClockGating= %x\n", PcieConfig->DisableRootPortClockGating));
132   DEBUG ((DEBUG_INFO, " EnablePeerMemoryWrite= %x\n", PcieConfig->EnablePeerMemoryWrite));
133   DEBUG ((DEBUG_INFO, " ComplianceTestMode= %x\n", PcieConfig->ComplianceTestMode));
134   DEBUG ((DEBUG_INFO, " RpFunctionSwap= %x\n", PcieConfig->RpFunctionSwap));
135   DEBUG ((DEBUG_INFO, " PcieDeviceOverrideTablePtr= %x\n", PcieConfig->PcieDeviceOverrideTablePtr));
136 }
137 
138 /**
139   Print PCH_SATA_CONFIG and serial out.
140 
141   @param[in]  SataCtrlIndex     SATA controller index
142   @param[in]  SataConfig        Pointer to a PCH_SATA_CONFIG that provides the platform setting
143 
144 **/
145 VOID
146 PchPrintSataConfig (
147   IN UINT32                     SataCtrlIndex,
148   IN CONST PCH_SATA_CONFIG      *SataConfig
149   )
150 {
151   UINT32 Index;
152 
153   DEBUG ((DEBUG_INFO, "--------------- PCH SATA Config for controller %d -----------\n", SataCtrlIndex));
154   DEBUG ((DEBUG_INFO, " Enable= %x\n", SataConfig->Enable));
155   DEBUG ((DEBUG_INFO, " SataMode= %x\n", SataConfig->SataMode));
156 
157   for (Index = 0; Index < GetPchMaxSataPortNum (SataCtrlIndex); Index++) {
158     DEBUG ((DEBUG_INFO, " PortSettings[%d] Enabled= %x\n", Index, SataConfig->PortSettings[Index].Enable));
159     DEBUG ((DEBUG_INFO, " PortSettings[%d] HotPlug= %x\n", Index, SataConfig->PortSettings[Index].HotPlug));
160     DEBUG ((DEBUG_INFO, " PortSettings[%d] InterlockSw= %x\n", Index, SataConfig->PortSettings[Index].InterlockSw));
161     DEBUG ((DEBUG_INFO, " PortSettings[%d] External= %x\n", Index, SataConfig->PortSettings[Index].External));
162     DEBUG ((DEBUG_INFO, " PortSettings[%d] SpinUp= %x\n", Index, SataConfig->PortSettings[Index].SpinUp));
163     DEBUG ((DEBUG_INFO, " PortSettings[%d] SolidStateDrive= %x\n", Index, SataConfig->PortSettings[Index].SolidStateDrive));
164     DEBUG ((DEBUG_INFO, " PortSettings[%d] DevSlp= %x\n", Index, SataConfig->PortSettings[Index].DevSlp));
165     DEBUG ((DEBUG_INFO, " PortSettings[%d] EnableDitoConfig= %x\n", Index, SataConfig->PortSettings[Index].EnableDitoConfig));
166     DEBUG ((DEBUG_INFO, " PortSettings[%d] DmVal= %x\n", Index, SataConfig->PortSettings[Index].DmVal));
167     DEBUG ((DEBUG_INFO, " PortSettings[%d] DitoVal= %x\n", Index, SataConfig->PortSettings[Index].DitoVal));
168     DEBUG ((DEBUG_INFO, " PortSettings[%d] ZpOdd= %x\n", Index, SataConfig->PortSettings[Index].ZpOdd));
169   }
170 
171   DEBUG ((DEBUG_INFO, " RaidDeviceId= %x\n", SataConfig->Rst.RaidDeviceId));
172   DEBUG ((DEBUG_INFO, " Sata interrupt mode =  %x\n", SataConfig->Rst.SataRstInterrupt));
173   DEBUG ((DEBUG_INFO, " Raid0= %x\n", SataConfig->Rst.Raid0));
174   DEBUG ((DEBUG_INFO, " Raid1= %x\n", SataConfig->Rst.Raid1));
175   DEBUG ((DEBUG_INFO, " Raid10= %x\n", SataConfig->Rst.Raid10));
176   DEBUG ((DEBUG_INFO, " Raid5= %x\n", SataConfig->Rst.Raid5));
177   DEBUG ((DEBUG_INFO, " Irrt= %x\n", SataConfig->Rst.Irrt));
178   DEBUG ((DEBUG_INFO, " OromUiBanner= %x\n", SataConfig->Rst.OromUiBanner));
179   DEBUG ((DEBUG_INFO, " OromUiDelay= %x\n", SataConfig->Rst.OromUiDelay));
180   DEBUG ((DEBUG_INFO, " HddUnlock= %x\n", SataConfig->Rst.HddUnlock));
181   DEBUG ((DEBUG_INFO, " LedLocate= %x\n", SataConfig->Rst.LedLocate));
182   DEBUG ((DEBUG_INFO, " IrrtOnly= %x\n", SataConfig->Rst.IrrtOnly));
183   DEBUG ((DEBUG_INFO, " SmartStorage= %x\n", SataConfig->Rst.SmartStorage));
184   DEBUG ((DEBUG_INFO, " LegacyOrom= %x\n", SataConfig->Rst.LegacyOrom));
185   DEBUG ((DEBUG_INFO, " OptaneMemory= %x\n", SataConfig->Rst.OptaneMemory));
186   DEBUG ((DEBUG_INFO, " CpuAttachedStorage= %x\n", SataConfig->Rst.CpuAttachedStorage));
187 
188   DEBUG ((DEBUG_INFO, " SpeedSupport= %x\n", SataConfig->SpeedLimit));
189   DEBUG ((DEBUG_INFO, " EsataSpeedLimit= %x\n", SataConfig->EsataSpeedLimit));
190   DEBUG ((DEBUG_INFO, " LedEnable= %x\n", SataConfig->LedEnable));
191   DEBUG ((DEBUG_INFO, " TestMode= %x\n", SataConfig->TestMode));
192   DEBUG ((DEBUG_INFO, " SalpSupport= %x\n", SataConfig->SalpSupport));
193   DEBUG ((DEBUG_INFO, " PwrOptEnable= %x\n", SataConfig->PwrOptEnable));
194 
195   for (Index = 0; Index < PCH_MAX_RST_PCIE_STORAGE_CR; Index++) {
196     DEBUG ((DEBUG_INFO, " RstPcieStorageRemap[%d].Enable                  = %x\n", Index, SataConfig->RstPcieStorageRemap[Index].Enable));
197     DEBUG ((DEBUG_INFO, " RstPcieStorageRemap[%d].RstPcieStoragePort      = %x\n", Index, SataConfig->RstPcieStorageRemap[Index].RstPcieStoragePort));
198     DEBUG ((DEBUG_INFO, " RstPcieStorageRemap[%d].DeviceResetDelay        = %x\n", Index, SataConfig->RstPcieStorageRemap[Index].DeviceResetDelay));
199   }
200   DEBUG ((DEBUG_INFO, " ThermalThrottling P0T1M %x\n", SataConfig->ThermalThrottling.P0T1M));
201   DEBUG ((DEBUG_INFO, " ThermalThrottling P0T2M %x\n", SataConfig->ThermalThrottling.P0T2M));
202   DEBUG ((DEBUG_INFO, " ThermalThrottling P0T3M %x\n", SataConfig->ThermalThrottling.P0T3M));
203   DEBUG ((DEBUG_INFO, " ThermalThrottling P0TDisp %x\n", SataConfig->ThermalThrottling.P0TDisp));
204   DEBUG ((DEBUG_INFO, " ThermalThrottling P0Tinact %x\n", SataConfig->ThermalThrottling.P0Tinact));
205   DEBUG ((DEBUG_INFO, " ThermalThrottling P0TDispFinit %x\n", SataConfig->ThermalThrottling.P0TDispFinit));
206   DEBUG ((DEBUG_INFO, " ThermalThrottling P1T1M %x\n", SataConfig->ThermalThrottling.P1T1M));
207   DEBUG ((DEBUG_INFO, " ThermalThrottling P1T2M %x\n", SataConfig->ThermalThrottling.P1T2M));
208   DEBUG ((DEBUG_INFO, " ThermalThrottling P1T3M %x\n", SataConfig->ThermalThrottling.P1T3M));
209   DEBUG ((DEBUG_INFO, " ThermalThrottling P1TDisp %x\n", SataConfig->ThermalThrottling.P1TDisp));
210   DEBUG ((DEBUG_INFO, " ThermalThrottling P1Tinact %x\n", SataConfig->ThermalThrottling.P1Tinact));
211   DEBUG ((DEBUG_INFO, " ThermalThrottling P1TDispFinit %x\n", SataConfig->ThermalThrottling.P1TDispFinit));
212   DEBUG ((DEBUG_INFO, " ThermalThrottling SuggestedSetting %x\n", SataConfig->ThermalThrottling.SuggestedSetting));
213 }
214 
215 /**
216   Print PCH_IOAPIC_CONFIG and serial out.
217 
218   @param[in] IoApicConfig         Pointer to a PCH_IOAPIC_CONFIG that provides the platform setting
219 
220 **/
221 VOID
222 PchPrintIoApicConfig (
223   IN CONST PCH_IOAPIC_CONFIG   *IoApicConfig
224   )
225 {
226   DEBUG ((DEBUG_INFO, "------------------ PCH IOAPIC Config ------------------\n"));
227   DEBUG ((DEBUG_INFO, " IoApicEntry24_119= %x\n", IoApicConfig->IoApicEntry24_119));
228   DEBUG ((DEBUG_INFO, " Enable8254ClockGating= %x\n", IoApicConfig->Enable8254ClockGating));
229   DEBUG ((DEBUG_INFO, " Enable8254ClockGatingOnS3= %x\n", IoApicConfig->Enable8254ClockGatingOnS3));
230   DEBUG ((DEBUG_INFO, " IoApicId= %x\n", IoApicConfig->IoApicId));
231 }
232 
233 /**
234   Print PCH_LOCK_DOWN_CONFIG and serial out.
235 
236   @param[in] LockDownConfig         Pointer to a PCH_LOCK_DOWN_CONFIG that provides the platform setting
237 
238 **/
239 VOID
240 PchPrintLockDownConfig (
241   IN CONST PCH_LOCK_DOWN_CONFIG   *LockDownConfig
242   )
243 {
244   DEBUG ((DEBUG_INFO, "------------------ PCH Lock Down Config ------------------\n"));
245   DEBUG ((DEBUG_INFO, " GlobalSmi= %x\n", LockDownConfig->GlobalSmi));
246   DEBUG ((DEBUG_INFO, " BiosInterface= %x\n", LockDownConfig->BiosInterface));
247   DEBUG ((DEBUG_INFO, " RtcMemoryLock= %x\n", LockDownConfig->RtcMemoryLock));
248   DEBUG ((DEBUG_INFO, " BiosLock= %x\n", LockDownConfig->BiosLock));
249   DEBUG ((DEBUG_INFO, " UnlockGpioPads= %x\n", LockDownConfig->UnlockGpioPads));
250 }
251 
252 /**
253   Print PCH_HDAUDIO_CONFIG and serial out.
254 
255   @param[in] HdaConfig         Pointer to a PCH_HDAUDIO_CONFIG that provides the platform setting
256 
257 **/
258 VOID
259 PchPrintHdAudioConfig (
260   IN CONST PCH_HDAUDIO_CONFIG   *HdaConfig
261   )
262 {
263   DEBUG ((DEBUG_INFO, "------------------ PCH HD-Audio Config ------------------\n"));
264   DEBUG ((DEBUG_INFO, " DSP Enable               = %x\n", HdaConfig->DspEnable));
265   DEBUG ((DEBUG_INFO, " DSP UAA Compliance       = %x\n", HdaConfig->DspUaaCompliance));
266   DEBUG ((DEBUG_INFO, " iDisp Codec Disconnect   = %x\n", HdaConfig->IDispCodecDisconnect));
267   DEBUG ((DEBUG_INFO, " Pme                      = %x\n", HdaConfig->Pme));
268   DEBUG ((DEBUG_INFO, " Codec Sx Wake Capability = %x\n", HdaConfig->CodecSxWakeCapability));
269   DEBUG ((DEBUG_INFO, " VC Type                  = %x\n", HdaConfig->VcType));
270   DEBUG ((DEBUG_INFO, " HD-A Link Frequency      = %x\n", HdaConfig->HdAudioLinkFrequency));
271   DEBUG ((DEBUG_INFO, " iDisp Link Frequency     = %x\n", HdaConfig->IDispLinkFrequency));
272   DEBUG ((DEBUG_INFO, " iDisp Link T-Mode        = %x\n", HdaConfig->IDispLinkTmode));
273   DEBUG ((DEBUG_INFO, " Audio Link: HDA Link     = %x\n", HdaConfig->AudioLinkHda));
274   DEBUG ((DEBUG_INFO, " Audio Link: DMIC#0       = %x\n", HdaConfig->AudioLinkDmic0));
275   DEBUG ((DEBUG_INFO, " Audio Link: DMIC#1       = %x\n", HdaConfig->AudioLinkDmic1));
276   DEBUG ((DEBUG_INFO, " Audio Link: SSP#0        = %x\n", HdaConfig->AudioLinkSsp0));
277   DEBUG ((DEBUG_INFO, " Audio Link: SSP#1        = %x\n", HdaConfig->AudioLinkSsp1));
278   DEBUG ((DEBUG_INFO, " Audio Link: SSP#2        = %x\n", HdaConfig->AudioLinkSsp1));
279   DEBUG ((DEBUG_INFO, " Audio Link: SoundWire#1  = %x\n", HdaConfig->AudioLinkSndw1));
280   DEBUG ((DEBUG_INFO, " Audio Link: SoundWire#2  = %x\n", HdaConfig->AudioLinkSndw2));
281   DEBUG ((DEBUG_INFO, " Audio Link: SoundWire#3  = %x\n", HdaConfig->AudioLinkSndw3));
282   DEBUG ((DEBUG_INFO, " Audio Link: SoundWire#4  = %x\n", HdaConfig->AudioLinkSndw4));
283   DEBUG ((DEBUG_INFO, " SoundWire Buffer RCOMP   = %x\n", HdaConfig->SndwBufferRcomp));
284   DEBUG ((DEBUG_INFO, " ResetWaitTimer           = %x\n", HdaConfig->ResetWaitTimer));
285   DEBUG ((DEBUG_INFO, " VerbTableEntryNum        = %x\n", HdaConfig->VerbTableEntryNum));
286   DEBUG ((DEBUG_INFO, " VerbTablePtr             = %x\n", HdaConfig->VerbTablePtr));
287 }
288 
289 /**
290   Print PCH_PM_CONFIG and serial out.
291 
292   @param[in] PmConfig         Pointer to a PCH_PM_CONFIG that provides the platform setting
293 
294 **/
295 VOID
296 PchPrintPmConfig (
297   IN CONST PCH_PM_CONFIG   *PmConfig
298   )
299 {
300   DEBUG ((DEBUG_INFO, "------------------ PCH PM Config ------------------\n"));
301 
302   DEBUG ((DEBUG_INFO, " WakeConfig PmeB0S5Dis               = %x\n", PmConfig->WakeConfig.PmeB0S5Dis));
303   DEBUG ((DEBUG_INFO, " WakeConfig WolEnableOverride        = %x\n", PmConfig->WakeConfig.WolEnableOverride));
304   DEBUG ((DEBUG_INFO, " WakeConfig LanWakeFromDeepSx        = %x\n", PmConfig->WakeConfig.LanWakeFromDeepSx));
305   DEBUG ((DEBUG_INFO, " WakeConfig PcieWakeFromDeepSx       = %x\n", PmConfig->WakeConfig.PcieWakeFromDeepSx));
306   DEBUG ((DEBUG_INFO, " WakeConfig WoWlanEnable             = %x\n", PmConfig->WakeConfig.WoWlanEnable));
307   DEBUG ((DEBUG_INFO, " WakeConfig WoWlanDeepSxEnable       = %x\n", PmConfig->WakeConfig.WoWlanDeepSxEnable));
308 
309   DEBUG ((DEBUG_INFO, " PchDeepSxPol                        = %x\n", PmConfig->PchDeepSxPol));
310   DEBUG ((DEBUG_INFO, " PchSlpS3MinAssert                   = %x\n", PmConfig->PchSlpS3MinAssert));
311   DEBUG ((DEBUG_INFO, " PchSlpS4MinAssert                   = %x\n", PmConfig->PchSlpS4MinAssert));
312   DEBUG ((DEBUG_INFO, " PchSlpSusMinAssert                  = %x\n", PmConfig->PchSlpSusMinAssert));
313   DEBUG ((DEBUG_INFO, " PchSlpAMinAssert                    = %x\n", PmConfig->PchSlpAMinAssert));
314   DEBUG ((DEBUG_INFO, " LpcClockRun                         = %x\n", PmConfig->LpcClockRun));
315   DEBUG ((DEBUG_INFO, " SlpStrchSusUp                       = %x\n", PmConfig->SlpStrchSusUp));
316   DEBUG ((DEBUG_INFO, " SlpLanLowDc                         = %x\n", PmConfig->SlpLanLowDc));
317   DEBUG ((DEBUG_INFO, " PwrBtnOverridePeriod                = %x\n", PmConfig->PwrBtnOverridePeriod));
318   DEBUG ((DEBUG_INFO, " DisableEnergyReport                 = %x\n", PmConfig->DisableEnergyReport));
319   DEBUG ((DEBUG_INFO, " DisableDsxAcPresentPulldown         = %x\n", PmConfig->DisableDsxAcPresentPulldown));
320   DEBUG ((DEBUG_INFO, " PchPwrCycDur                        = %x\n", PmConfig->PchPwrCycDur));
321   DEBUG ((DEBUG_INFO, " PciePllSsc                          = %x\n", PmConfig->PciePllSsc));
322   DEBUG ((DEBUG_INFO, " DisableNativePowerButton            = %x\n", PmConfig->DisableNativePowerButton));
323   DEBUG ((DEBUG_INFO, " SlpS0Enabled                        = %x\n", PmConfig->SlpS0Enable));
324   DEBUG ((DEBUG_INFO, " MeWakeSts                           = %x\n", PmConfig->MeWakeSts));
325   DEBUG ((DEBUG_INFO, " WolOvrWkSts                         = %x\n", PmConfig->WolOvrWkSts));
326   DEBUG ((DEBUG_INFO, " EnableTcoTimer                      = %x\n", PmConfig->EnableTcoTimer));
327   DEBUG ((DEBUG_INFO, " VrAlert                             = %x\n", PmConfig->VrAlert));
328   DEBUG ((DEBUG_INFO, " PowerButtonDebounce                 = %x\n", PmConfig->PowerButtonDebounce));
329   DEBUG ((DEBUG_INFO, " SlpS0VmRuntimeControl               = %x\n", PmConfig->SlpS0VmRuntimeControl));
330   DEBUG ((DEBUG_INFO, " SlpS0Vm070VSupport                  = %x\n", PmConfig->SlpS0Vm070VSupport));
331   DEBUG ((DEBUG_INFO, " SlpS0Vm075VSupport                  = %x\n", PmConfig->SlpS0Vm075VSupport));
332   DEBUG ((DEBUG_INFO, " SlpS0Override                       = %x\n", PmConfig->SlpS0Override));
333   DEBUG ((DEBUG_INFO, " SlpS0DisQForDebug                   = %x\n", PmConfig->SlpS0DisQForDebug));
334   DEBUG ((DEBUG_INFO, " PsOnEnable                          = %x\n", PmConfig->PsOnEnable));
335   DEBUG ((DEBUG_INFO, " CpuC10GatePinEnable                 = %x\n", PmConfig->CpuC10GatePinEnable));
336   DEBUG ((DEBUG_INFO, " PmcDbgMsgEn                         = %x\n", PmConfig->PmcDbgMsgEn));
337   DEBUG ((DEBUG_INFO, " ModPhySusPgEnable                   = %x\n", PmConfig->ModPhySusPgEnable));
338   DEBUG ((DEBUG_INFO, " SlpS0WithGbeSupport                 = %x\n", PmConfig->SlpS0WithGbeSupport));
339 }
340 
341 /**
342   Print PCH_DMI_CONFIG and serial out.
343 
344   @param[in] DmiConfig         Pointer to a PCH_DMI_CONFIG that provides the platform setting
345 
346 **/
347 VOID
348 PchPrintDmiConfig (
349   IN CONST PCH_DMI_CONFIG   *DmiConfig
350   )
351 {
352   DEBUG ((DEBUG_INFO, "------------------ PCH DMI Config ------------------\n"));
353   DEBUG ((DEBUG_INFO, " PwrOptEnable= %x\n", DmiConfig->PwrOptEnable));
354   DEBUG ((DEBUG_INFO, " DmiAspmCtrl= %x\n", DmiConfig->DmiAspmCtrl));
355 }
356 /**
357   Print PCH_LPC_SIRQ_CONFIG and serial out.
358 
359   @param[in] SerialIrqConfig         Pointer to a PCH_LPC_SIRQ_CONFIG that provides the platform setting
360 
361 **/
362 VOID
363 PchPrintSerialIrqConfig (
364   IN CONST PCH_LPC_SIRQ_CONFIG   *SerialIrqConfig
365   )
366 {
367   DEBUG ((DEBUG_INFO, "------------------ PCH LPC SIRQ Config ------------------\n"));
368   DEBUG ((DEBUG_INFO, " SirqEnable= %x\n", SerialIrqConfig->SirqEnable));
369   DEBUG ((DEBUG_INFO, " SirqMode= %x\n", SerialIrqConfig->SirqMode));
370   DEBUG ((DEBUG_INFO, " StartFramePulse= %x\n", SerialIrqConfig->StartFramePulse));
371 }
372 /**
373   Print PCH_THERMAL_CONFIG and serial out.
374 
375   @param[in] ThermalConfig         Pointer to a PCH_THERMAL_CONFIG that provides the platform setting
376 
377 **/
378 VOID
379 PchPrintThermalConfig (
380   IN CONST PCH_THERMAL_CONFIG   *ThermalConfig
381   )
382 {
383   UINTN Index;
384 
385   DEBUG ((DEBUG_INFO, "------------------ PCH Thermal Config ------------------\n"));
386   DEBUG ((DEBUG_INFO, " TsmicLock= %x\n", ThermalConfig->TsmicLock));
387   DEBUG ((DEBUG_INFO, " TTLevels T0Level %x centigrade degree\n", ThermalConfig->TTLevels.T0Level));
388   DEBUG ((DEBUG_INFO, " TTLevels T1Level %x centigrade degree\n", ThermalConfig->TTLevels.T1Level));
389   DEBUG ((DEBUG_INFO, " TTLevels T2Level %x centigrade degree\n", ThermalConfig->TTLevels.T2Level));
390   DEBUG ((DEBUG_INFO, " TTLevels TTEnable %x\n", ThermalConfig->TTLevels.TTEnable));
391   DEBUG ((DEBUG_INFO, " TTLevels TTState13Enable %x\n", ThermalConfig->TTLevels.TTState13Enable));
392   DEBUG ((DEBUG_INFO, " TTLevels TTLock %x\n", ThermalConfig->TTLevels.TTLock));
393   DEBUG ((DEBUG_INFO, " TTLevels SuggestedSetting %x\n", ThermalConfig->TTLevels.SuggestedSetting));
394   DEBUG ((DEBUG_INFO, " TTLevels PchCrossThrottling %x\n", ThermalConfig->TTLevels.PchCrossThrottling));
395 
396   DEBUG ((DEBUG_INFO, " DmiHaAWC DmiTsawEn %x\n", ThermalConfig->DmiHaAWC.DmiTsawEn));
397   DEBUG ((DEBUG_INFO, " DmiHaAWC TS0TW %x\n", ThermalConfig->DmiHaAWC.TS0TW));
398   DEBUG ((DEBUG_INFO, " DmiHaAWC TS1TW %x\n", ThermalConfig->DmiHaAWC.TS1TW));
399   DEBUG ((DEBUG_INFO, " DmiHaAWC TS2TW %x\n", ThermalConfig->DmiHaAWC.TS2TW));
400   DEBUG ((DEBUG_INFO, " DmiHaAWC TS3TW %x\n", ThermalConfig->DmiHaAWC.TS3TW));
401   DEBUG ((DEBUG_INFO, " DmiHaAWC SuggestedSetting %x\n", ThermalConfig->DmiHaAWC.SuggestedSetting));
402 
403   DEBUG ((DEBUG_INFO, " MemoryThrottling Enable= %x\n", ThermalConfig->MemoryThrottling.Enable));
404   for (Index = 0; Index < MaxTsGpioPin; Index++) {
405     DEBUG ((DEBUG_INFO, " MemoryThrottling TsGpioPinSetting PmsyncEnable= %x\n", ThermalConfig->MemoryThrottling.TsGpioPinSetting[Index].PmsyncEnable));
406     DEBUG ((DEBUG_INFO, " MemoryThrottling TsGpioPinSetting C0TransmitEnable= %x\n", ThermalConfig->MemoryThrottling.TsGpioPinSetting[Index].C0TransmitEnable));
407     DEBUG ((DEBUG_INFO, " MemoryThrottling TsGpioPinSetting PinSelection= %x\n", ThermalConfig->MemoryThrottling.TsGpioPinSetting[Index].PinSelection));
408   }
409   DEBUG ((DEBUG_INFO, " PchHotEnable = %x\n", ThermalConfig->PchHotEnable));
410   DEBUG ((DEBUG_INFO, " PchHotLevel = %x\n", ThermalConfig->PchHotLevel));
411 }
412 
413 /**
414   Print PCH_GENERAL_CONFIG and serial out.
415 
416   @param[in] PchGeneralConfig   Pointer to a PCH_GENERAL_CONFIG that provides the platform setting
417 
418 **/
419 VOID
420 PchPrintGeneralConfig (
421   IN CONST PCH_GENERAL_CONFIG   *PchGeneralConfig
422   )
423 {
424   DEBUG ((DEBUG_INFO, "------------------ PCH General Config ------------------\n"));
425   DEBUG ((DEBUG_INFO, " Crid= %x\n", PchGeneralConfig->Crid));
426   DEBUG ((DEBUG_INFO, " LegacyIoLowLatency = %x\n", PchGeneralConfig->LegacyIoLowLatency));
427 }
428 
429 /**
430   Print PCH_LAN_CONFIG and serial out.
431 
432   @param[in] LanConfig         Pointer to a PCH_LAN_CONFIG that provides the platform setting
433 
434 **/
435 VOID
436 PchPrintLanConfig (
437   IN CONST PCH_LAN_CONFIG   *LanConfig
438   )
439 {
440   DEBUG ((DEBUG_INFO, "------------------ PCH LAN Config ------------------\n"));
441   DEBUG ((DEBUG_INFO, " Enable= %x\n", LanConfig->Enable));
442   DEBUG ((DEBUG_INFO, " LtrEnable= %x\n", LanConfig->LtrEnable));
443 }
444 
445 /**
446   Print PCH_SERIAL_IO_CONFIG and serial out.
447 
448   @param[in] SerialIoConfig         Pointer to a PCH_SERIAL_IO_CONFIG that provides the platform setting
449 
450 **/
451 VOID
452 PchPrintSerialIoConfig (
453   IN CONST PCH_SERIAL_IO_CONFIG   *SerialIoConfig
454   )
455 {
456   UINTN Index;
457 #ifndef MDEPKG_NDEBUG
458   static UINT8 DeviceName[PCH_MAX_SERIALIO_CONTROLLERS][5] = {"I2C0","I2C1","I2C2","I2C3","I2C4","I2C5","SPI0","SPI1","SPI2","UA00","UA01","UA02"};
459 #endif
460 
461   DEBUG ((DEBUG_INFO, "------------------ PCH Serial IO Config ------------------\n"));
462   DEBUG_CODE_BEGIN ();
463   for (Index = 0; Index < GetPchMaxSerialIoControllersNum (); Index++) {
464     DEBUG ((DEBUG_INFO, " SerialIoController %a: Mode 0x%x\n", DeviceName[Index], SerialIoConfig->DevMode[Index]));
465   }
466   DEBUG_CODE_END ();
467   for (Index = 0; Index < GetPchMaxSerialIoSpiControllersNum (); Index++) {
468     DEBUG ((DEBUG_INFO, " SpiCsPolarity[%d] = 0x%x\n", Index, SerialIoConfig->SpiCsPolarity[Index]));
469   }
470   for (Index = 0; Index < GetPchMaxSerialIoUartControllersNum (); Index++) {
471     DEBUG ((DEBUG_INFO, " UartHwFlowCtrl[%d] = 0x%x\n", Index, SerialIoConfig->UartHwFlowCtrl[Index]));
472   }
473   for (Index = 0; Index < GetPchMaxSerialIoI2cControllersNum (); Index ++) {
474     DEBUG ((DEBUG_INFO, " I2cPadsTermination[%d] = 0x%x\n", Index, SerialIoConfig->I2cPadsTermination[Index]));
475   }
476   DEBUG ((DEBUG_INFO, " DebugUartNumber = 0x%x\n", SerialIoConfig->DebugUartNumber));
477   DEBUG ((DEBUG_INFO, " EnableDebugUartAfterPost = 0x%x\n", SerialIoConfig->EnableDebugUartAfterPost));
478   DEBUG ((DEBUG_INFO, " Uart0PinMuxing = 0x%x\n", SerialIoConfig->Uart0PinMuxing));
479 }
480 
481 /**
482   Print PCH_INTERRUPT_CONFIG and serial out
483 
484   @param[in] InterruptConfig        Pointer to Interrupt Configuration structure
485 
486 **/
487 VOID
488 PchPrintInterruptConfig (
489   IN CONST PCH_INTERRUPT_CONFIG     *InterruptConfig
490   )
491 {
492   UINTN Index;
493   //
494   // Print interrupt information
495   //
496   DEBUG ((DEBUG_INFO, "------------------ PCH Interrupt Config ------------------\n"));
497   DEBUG ((DEBUG_INFO, " Interrupt assignment:\n"));
498   DEBUG ((DEBUG_INFO, "  Dxx:Fx INTx IRQ\n"));
499   for (Index = 0; Index < InterruptConfig->NumOfDevIntConfig; Index++) {
500     DEBUG ((DEBUG_INFO, "  D%02d:F%d    %d %03d\n",
501             InterruptConfig->DevIntConfig[Index].Device,
502             InterruptConfig->DevIntConfig[Index].Function,
503             InterruptConfig->DevIntConfig[Index].IntX,
504             InterruptConfig->DevIntConfig[Index].Irq));
505   }
506   DEBUG ((DEBUG_INFO, " Legacy PIC interrupt routing:\n"));
507   DEBUG ((DEBUG_INFO, "  PIRQx    IRQx\n"));
508   for (Index = 0; Index < PCH_MAX_PXRC_CONFIG; Index++) {
509     DEBUG ((DEBUG_INFO, "  PIRQ%c -> IRQ%d\n", Index + 65, InterruptConfig->PxRcConfig[Index]));
510   }
511   DEBUG ((DEBUG_INFO, " Other interrupt configuration:\n"));
512   DEBUG ((DEBUG_INFO, "  GpioIrqRoute= %d\n", InterruptConfig->GpioIrqRoute));
513   DEBUG ((DEBUG_INFO, "  SciIrqSelect= %d\n", InterruptConfig->SciIrqSelect));
514   DEBUG ((DEBUG_INFO, "  TcoIrqEnable= %d\n", InterruptConfig->TcoIrqEnable));
515   DEBUG ((DEBUG_INFO, "  TcoIrqSelect= %d\n", InterruptConfig->TcoIrqSelect));
516 }
517 
518 /**
519   Print PCH_SCS_CONFIG and serial out.
520 
521   @param[in] ScsConfig         Pointer to a PCH_SCS_CONFIG that provides the platform setting
522 
523 **/
524 VOID
525 PchPrintScsConfig (
526   IN CONST PCH_SCS_CONFIG   *ScsConfig
527   )
528 {
529   DEBUG ((DEBUG_INFO, "------------------ PCH SCS Config ------------------\n"));
530   DEBUG ((DEBUG_INFO, " ScsEmmcEnabled = %x\n", ScsConfig->ScsEmmcEnabled));
531   DEBUG ((DEBUG_INFO, " ScsSdcardEnabled = %x\n", ScsConfig->ScsSdcardEnabled));
532   DEBUG ((DEBUG_INFO, " SdCardPowerEnableActiveHigh = %x\n", ScsConfig->SdCardPowerEnableActiveHigh));
533   DEBUG ((DEBUG_INFO, " ScsUfsEnabled = %x\n", ScsConfig->ScsUfsEnabled));
534   DEBUG ((DEBUG_INFO, " ScsEmmcHs400Enabled = %x\n", ScsConfig->ScsEmmcHs400Enabled));
535   DEBUG ((DEBUG_INFO, " ScsEmmcHs400TuningRequired = %x\n", ScsConfig->ScsEmmcHs400TuningRequired));
536   DEBUG ((DEBUG_INFO, " ScsEmmcHs400DllDataValid = %x\n", ScsConfig->ScsEmmcHs400DllDataValid));
537   DEBUG ((DEBUG_INFO, " ScsEmmcHs400RxStrobeDll1 = %x\n", ScsConfig->ScsEmmcHs400RxStrobeDll1));
538   DEBUG ((DEBUG_INFO, " ScsEmmcHs400TxDataDll = %x\n", ScsConfig->ScsEmmcHs400TxDataDll));
539   DEBUG ((DEBUG_INFO, " ScsEmmcHs400DriverStrength = %x\n", ScsConfig->ScsEmmcHs400DriverStrength));
540 }
541 
542 /**
543   Print PCH_ISH_CONFIG and serial out.
544 
545   @param[in] IshConfig         Pointer to a PCH_ISH_CONFIG that provides the platform setting
546 
547 **/
548 VOID
549 PchPrintIshConfig (
550   IN CONST PCH_ISH_CONFIG   *IshConfig
551   )
552 {
553   DEBUG ((DEBUG_INFO, "------------------ PCH ISH Config ------------------\n"));
554   DEBUG ((DEBUG_INFO, " SPI GPIO Assigned   = %x\n", IshConfig->SpiGpioAssign));
555   DEBUG ((DEBUG_INFO, " UART0 GPIO Assigned = %x\n", IshConfig->Uart0GpioAssign));
556   DEBUG ((DEBUG_INFO, " UART1 GPIO Assigned = %x\n", IshConfig->Uart1GpioAssign));
557   DEBUG ((DEBUG_INFO, " I2C0 GPIO Assigned  = %x\n", IshConfig->I2c0GpioAssign));
558   DEBUG ((DEBUG_INFO, " I2C1 GPIO Assigned  = %x\n", IshConfig->I2c1GpioAssign));
559   DEBUG ((DEBUG_INFO, " I2C2 GPIO Assigned  = %x\n", IshConfig->I2c2GpioAssign));
560   DEBUG ((DEBUG_INFO, " GP_0 GPIO Assigned  = %x\n", IshConfig->Gp0GpioAssign));
561   DEBUG ((DEBUG_INFO, " GP_1 GPIO Assigned  = %x\n", IshConfig->Gp1GpioAssign));
562   DEBUG ((DEBUG_INFO, " GP_2 GPIO Assigned  = %x\n", IshConfig->Gp2GpioAssign));
563   DEBUG ((DEBUG_INFO, " GP_3 GPIO Assigned  = %x\n", IshConfig->Gp3GpioAssign));
564   DEBUG ((DEBUG_INFO, " GP_4 GPIO Assigned  = %x\n", IshConfig->Gp4GpioAssign));
565   DEBUG ((DEBUG_INFO, " GP_5 GPIO Assigned  = %x\n", IshConfig->Gp5GpioAssign));
566   DEBUG ((DEBUG_INFO, " GP_6 GPIO Assigned  = %x\n", IshConfig->Gp6GpioAssign));
567   DEBUG ((DEBUG_INFO, " GP_7 GPIO Assigned  = %x\n", IshConfig->Gp7GpioAssign));
568 }
569 
570 /**
571   Print PCH_FLASH_PROTECTION_CONFIG and serial out.
572 
573   @param[in] FlashProtectConfig  Pointer to a PCH_FLASH_PROTECTION_CONFIG that provides the platform setting
574 
575 **/
576 VOID
577 PchPrintFlashProtectionConfig (
578   IN CONST PCH_FLASH_PROTECTION_CONFIG   *FlashProtectConfig
579   )
580 {
581   UINT32 Index;
582 
583   DEBUG ((DEBUG_INFO, "------------------ PCH Flash Protection Config ------------------\n"));
584   for (Index = 0; Index < PCH_FLASH_PROTECTED_RANGES; ++Index) {
585     DEBUG ((DEBUG_INFO, " WriteProtectionEnable[%d] = %x\n", Index, FlashProtectConfig->ProtectRange[Index].WriteProtectionEnable));
586     DEBUG ((DEBUG_INFO, " ReadProtectionEnable[%d]  = %x\n", Index, FlashProtectConfig->ProtectRange[Index].ReadProtectionEnable));
587     DEBUG ((DEBUG_INFO, " ProtectedRangeLimit[%d]   = %x\n", Index, FlashProtectConfig->ProtectRange[Index].ProtectedRangeLimit));
588     DEBUG ((DEBUG_INFO, " ProtectedRangeBase[%d]    = %x\n", Index, FlashProtectConfig->ProtectRange[Index].ProtectedRangeBase));
589   }
590 }
591 
592 /**
593   Print PCH_P2SB_CONFIG and serial out.
594 
595   @param[in] P2sbConfig                 Pointer to a PCH_P2SB_CONFIG that provides the platform setting
596 
597 **/
598 VOID
599 PchPrintP2sbConfig (
600   IN CONST PCH_P2SB_CONFIG              *P2sbConfig
601   )
602 {
603   DEBUG ((DEBUG_INFO, "------------------ PCH P2SB Config ------------------\n"));
604   DEBUG ((DEBUG_INFO, "SbAccessUnlock= %x\n", P2sbConfig->SbAccessUnlock));
605 }
606 
607 /**
608   Print PCH_ESPI_CONFIG.
609 
610   @param[in] EspiConfig         Pointer to a PCH_ESPI_CONFIG that provides the eSPI setting
611 
612 **/
613 VOID
614 PchPrintEspiConfig (
615   IN CONST PCH_ESPI_CONFIG   *EspiConfig
616   )
617 {
618   DEBUG ((DEBUG_INFO, "------------------ PCH eSPI Config ------------------\n"));
619   DEBUG ((DEBUG_INFO, " LGMR Enable %x\n", EspiConfig->LgmrEnable));
620   DEBUG ((DEBUG_INFO, " BME for Master and Slave Enabled %x\n", EspiConfig->BmeMasterSlaveEnabled));
621 }
622 
623 /**
624   Print PCH_CNVI_CONFIG.
625 
626   @param[in] CnviConfig         Pointer to a PCH_CNVI_CONFIG that provides the CNVi settings
627 
628 **/
629 VOID
630 PchPrintCnviConfig (
631   IN CONST PCH_CNVI_CONFIG   *CnviConfig
632   )
633 {
634   DEBUG ((DEBUG_INFO, "------------------ PCH CNVi Config ------------------\n"));
635   DEBUG ((DEBUG_INFO, "CNVi Mode = %x\n", CnviConfig->Mode));
636   DEBUG ((DEBUG_INFO, "CNVi MfUart1 type = %x\n", CnviConfig->MfUart1Type));
637 }
638 
639 /**
640   Print PCH_HSIO_CONFIG.
641 
642   @param[in] HsioConfig         Pointer to a PCH_HSIO_CONFIG that provides the eSPI setting
643 
644 **/
645 VOID
646 PchPrintHsioConfig (
647   IN CONST PCH_HSIO_CONFIG   *HsioConfig
648   )
649 {
650   PCH_HSIO_VER_INFO             *BiosChipsetInitVerInfoPtr;
651   DEBUG ((DEBUG_INFO, "------------------ PCH HSIO Config ------------------\n"));
652   DEBUG ((DEBUG_INFO, " ChipsetInit Binary Pointer            = %x\n", HsioConfig->ChipsetInitBinPtr));
653   DEBUG ((DEBUG_INFO, " ChipsetInit Binary Length             = %x\n", HsioConfig->ChipsetInitBinLen));
654   BiosChipsetInitVerInfoPtr = (PCH_HSIO_VER_INFO *) HsioConfig->ChipsetInitBinPtr;
655   if (HsioConfig->ChipsetInitBinPtr && HsioConfig->ChipsetInitBinLen) {
656     DEBUG ((DEBUG_INFO, " ChipsetInit Binary Base CRC           = %x\n", BiosChipsetInitVerInfoPtr->BaseCrc));
657     DEBUG ((DEBUG_INFO, " ChipsetInit Binary OEM CRC            = %x\n", BiosChipsetInitVerInfoPtr->OemCrc));
658     DEBUG ((DEBUG_INFO, " ChipsetInit Binary SUS CRC            = %x\n", BiosChipsetInitVerInfoPtr->SusCrc));
659     DEBUG ((DEBUG_INFO, " ChipsetInit Binary Version            = %x\n", BiosChipsetInitVerInfoPtr->Version));
660     DEBUG ((DEBUG_INFO, " ChipsetInit Binary Product            = %x\n", BiosChipsetInitVerInfoPtr->Product));
661     DEBUG ((DEBUG_INFO, " ChipsetInit Binary Metal Layer        = %x\n", BiosChipsetInitVerInfoPtr->MetalLayer));
662     DEBUG ((DEBUG_INFO, " ChipsetInit Binary Base Layer         = %x\n", BiosChipsetInitVerInfoPtr->BaseLayer));
663     DEBUG ((DEBUG_INFO, " ChipsetInit Binary OEM Version        = %x\n", BiosChipsetInitVerInfoPtr->OemVersion));
664     DEBUG ((DEBUG_INFO, " ChipsetInit Binary Debug Mode         = %x\n", BiosChipsetInitVerInfoPtr->DebugMode));
665     DEBUG ((DEBUG_INFO, " ChipsetInit Binary OEM CRC Valid      = %x\n", BiosChipsetInitVerInfoPtr->OemCrcValid));
666     DEBUG ((DEBUG_INFO, " ChipsetInit Binary SUS CRC Valid      = %x\n", BiosChipsetInitVerInfoPtr->SusCrcValid));
667     DEBUG ((DEBUG_INFO, " ChipsetInit Binary Base CRC Valid     = %x\n", BiosChipsetInitVerInfoPtr->BaseCrcValid));
668   }
669 }
670 
671 /**
672   Print whole PCH config blocks and serial out.
673 
674   @param[in] SiPolicyPpi    The RC Policy PPI instance
675 
676 **/
677 VOID
678 EFIAPI
679 PchPrintPolicyPpi (
680   IN  SI_POLICY_PPI     *SiPolicyPpi
681   )
682 {
683 DEBUG_CODE_BEGIN();
684   EFI_STATUS                      Status;
685   PCH_GENERAL_CONFIG              *PchGeneralConfig;
686   PCH_PCIE_CONFIG                 *PcieRpConfig;
687   PCH_SATA_CONFIG                 *SataConfig;
688   PCH_IOAPIC_CONFIG               *IoApicConfig;
689   PCH_DMI_CONFIG                  *DmiConfig;
690   PCH_FLASH_PROTECTION_CONFIG     *FlashProtectionConfig;
691   PCH_HDAUDIO_CONFIG              *HdAudioConfig;
692   PCH_INTERRUPT_CONFIG            *InterruptConfig;
693   PCH_ISH_CONFIG                  *IshConfig;
694   PCH_LAN_CONFIG                  *LanConfig;
695   PCH_P2SB_CONFIG                 *P2sbConfig;
696   PCH_LOCK_DOWN_CONFIG            *LockDownConfig;
697   PCH_PM_CONFIG                   *PmConfig;
698   PCH_SCS_CONFIG                  *ScsConfig;
699   PCH_SERIAL_IO_CONFIG            *SerialIoConfig;
700   PCH_LPC_SIRQ_CONFIG             *SerialIrqConfig;
701   PCH_THERMAL_CONFIG              *ThermalConfig;
702   USB_CONFIG                      *UsbConfig;
703   PCH_ESPI_CONFIG                 *EspiConfig;
704   PCH_CNVI_CONFIG                 *CnviConfig;
705   PCH_HSIO_CONFIG                 *HsioConfig;
706   UINT32                          SataCtrlIndex;
707 
708   Status = GetConfigBlock ((VOID *) SiPolicyPpi, &gPchGeneralConfigGuid, (VOID *) &PchGeneralConfig);
709   ASSERT_EFI_ERROR (Status);
710   Status = GetConfigBlock ((VOID *) SiPolicyPpi, &gPcieRpConfigGuid, (VOID *) &PcieRpConfig);
711   ASSERT_EFI_ERROR (Status);
712   Status = GetConfigBlock ((VOID *) SiPolicyPpi, &gIoApicConfigGuid, (VOID *) &IoApicConfig);
713   ASSERT_EFI_ERROR (Status);
714   Status = GetConfigBlock ((VOID *) SiPolicyPpi, &gDmiConfigGuid, (VOID *) &DmiConfig);
715   ASSERT_EFI_ERROR (Status);
716   Status = GetConfigBlock ((VOID *) SiPolicyPpi, &gFlashProtectionConfigGuid, (VOID *) &FlashProtectionConfig);
717   ASSERT_EFI_ERROR (Status);
718   Status = GetConfigBlock ((VOID *) SiPolicyPpi, &gHdAudioConfigGuid, (VOID *) &HdAudioConfig);
719   ASSERT_EFI_ERROR (Status);
720   Status = GetConfigBlock ((VOID *) SiPolicyPpi, &gInterruptConfigGuid, (VOID *) &InterruptConfig);
721   ASSERT_EFI_ERROR (Status);
722   Status = GetConfigBlock ((VOID *) SiPolicyPpi, &gIshConfigGuid, (VOID *) &IshConfig);
723   ASSERT_EFI_ERROR (Status);
724   Status = GetConfigBlock ((VOID *) SiPolicyPpi, &gLanConfigGuid, (VOID *) &LanConfig);
725   ASSERT_EFI_ERROR (Status);
726   Status = GetConfigBlock ((VOID *) SiPolicyPpi, &gLockDownConfigGuid, (VOID *) &LockDownConfig);
727   ASSERT_EFI_ERROR (Status);
728   Status = GetConfigBlock ((VOID *) SiPolicyPpi, &gP2sbConfigGuid, (VOID *) &P2sbConfig);
729   ASSERT_EFI_ERROR (Status);
730   Status = GetConfigBlock ((VOID *) SiPolicyPpi, &gPmConfigGuid, (VOID *) &PmConfig);
731   ASSERT_EFI_ERROR (Status);
732   Status = GetConfigBlock ((VOID *) SiPolicyPpi, &gScsConfigGuid, (VOID *) &ScsConfig);
733   ASSERT_EFI_ERROR (Status);
734   Status = GetConfigBlock ((VOID *) SiPolicyPpi, &gSerialIoConfigGuid, (VOID *) &SerialIoConfig);
735   ASSERT_EFI_ERROR (Status);
736   Status = GetConfigBlock ((VOID *) SiPolicyPpi, &gSerialIrqConfigGuid, (VOID *) &SerialIrqConfig);
737   ASSERT_EFI_ERROR (Status);
738   Status = GetConfigBlock ((VOID *) SiPolicyPpi, &gThermalConfigGuid, (VOID *) &ThermalConfig);
739   ASSERT_EFI_ERROR (Status);
740   Status = GetConfigBlock ((VOID *) SiPolicyPpi, &gUsbConfigGuid, (VOID *) &UsbConfig);
741   ASSERT_EFI_ERROR (Status);
742   Status = GetConfigBlock ((VOID *) SiPolicyPpi, &gEspiConfigGuid, (VOID *) &EspiConfig);
743   ASSERT_EFI_ERROR (Status);
744   Status = GetConfigBlock ((VOID *) SiPolicyPpi, &gCnviConfigGuid, (VOID *) &CnviConfig);
745   ASSERT_EFI_ERROR (Status);
746   Status = GetConfigBlock ((VOID *) SiPolicyPpi, &gHsioConfigGuid, (VOID *) &HsioConfig);
747   ASSERT_EFI_ERROR (Status);
748 
749   DEBUG ((DEBUG_INFO, "------------------------ PCH Print Policy Start ------------------------\n"));
750   DEBUG ((DEBUG_INFO, " Revision= %x\n", SiPolicyPpi->TableHeader.Header.Revision));
751 
752   PchPrintGeneralConfig (PchGeneralConfig);
753   PchPrintPcieConfig (PcieRpConfig);
754   for (SataCtrlIndex = 0; SataCtrlIndex < GetPchMaxSataControllerNum (); SataCtrlIndex++) {
755     SataConfig = GetPchSataConfig (SiPolicyPpi, SataCtrlIndex);
756     PchPrintSataConfig (SataCtrlIndex, SataConfig);
757   }
758   PchPrintUsbConfig (UsbConfig);
759   PchPrintIoApicConfig (IoApicConfig);
760   PchPrintHdAudioConfig (HdAudioConfig);
761   PchPrintLanConfig (LanConfig);
762   PchPrintLockDownConfig (LockDownConfig);
763   PchPrintThermalConfig (ThermalConfig);
764   PchPrintPmConfig (PmConfig);
765   PchPrintDmiConfig (DmiConfig);
766   PchPrintSerialIrqConfig (SerialIrqConfig);
767   PchPrintSerialIoConfig (SerialIoConfig);
768   PchPrintInterruptConfig (InterruptConfig);
769   PchPrintScsConfig (ScsConfig);
770   PchPrintIshConfig (IshConfig);
771   PchPrintFlashProtectionConfig (FlashProtectionConfig);
772   PchPrintP2sbConfig (P2sbConfig);
773   PchPrintEspiConfig (EspiConfig);
774   PchPrintCnviConfig (CnviConfig);
775   PchPrintHsioConfig (HsioConfig);
776 
777   DEBUG ((DEBUG_INFO, "------------------------ PCH Print Platform Protocol End --------------------------\n"));
778 DEBUG_CODE_END();
779 }
780