1 /** @file 2 This protocol provides the memory information data, such as 3 total physical memory size, memory frequency, memory size 4 of each dimm and rank. 5 6 Copyright (c) 2019 Intel Corporation. All rights reserved. <BR> 7 8 SPDX-License-Identifier: BSD-2-Clause-Patent 9 **/ 10 11 #ifndef _MEM_INFO_PROTOCOL_H_ 12 #define _MEM_INFO_PROTOCOL_H_ 13 14 15 // 16 // Extern the GUID for protocol users. 17 // 18 extern EFI_GUID gMemInfoProtocolGuid; 19 20 // 21 // Protocol definitions 22 // 23 #define NODE_NUM 1 24 #define CH_NUM 2 25 #define DIMM_NUM 2 26 #define RANK_NUM 2 27 #define SLOT_NUM (CH_NUM * DIMM_NUM) 28 #define PROFILE_NUM 4 // number of memory profiles supported 29 #define XMP_PROFILE_NUM 2 // number of XMP profiles supported 30 31 // 32 // Matches MrcDdrType enum in MRC 33 // 34 #ifndef MRC_DDR_TYPE_DDR4 35 #define MRC_DDR_TYPE_DDR4 0 36 #endif 37 #ifndef MRC_DDR_TYPE_DDR3 38 #define MRC_DDR_TYPE_DDR3 1 39 #endif 40 #ifndef MRC_DDR_TYPE_LPDDR3 41 #define MRC_DDR_TYPE_LPDDR3 2 42 #endif 43 #ifndef MRC_DDR_TYPE_UNKNOWN 44 #define MRC_DDR_TYPE_UNKNOWN 3 45 #endif 46 47 // 48 // Matches MrcDimmSts enum in MRC 49 // 50 #ifndef DIMM_ENABLED 51 #define DIMM_ENABLED 0 // DIMM/rank Pair is enabled, presence will be detected. 52 #endif 53 #ifndef DIMM_DISABLED 54 #define DIMM_DISABLED 1 // DIMM/rank Pair is disabled, regardless of presence. 55 #endif 56 #ifndef DIMM_PRESENT 57 #define DIMM_PRESENT 2 // There is a DIMM present in the slot/rank pair and it will be used. 58 #endif 59 #ifndef DIMM_NOT_PRESENT 60 #define DIMM_NOT_PRESENT 3 // There is no DIMM present in the slot/rank pair. 61 #endif 62 63 #pragma pack(1) 64 /// 65 /// Memory timing Structure 66 /// 67 typedef struct { 68 UINT32 tCK; ///< Offset 0 Memory cycle time, in femtoseconds. 69 UINT16 NMode; ///< Offset 4 Number of tCK cycles for the channel DIMM's command rate mode. 70 UINT16 tCL; ///< Offset 6 Number of tCK cycles for the channel DIMM's CAS latency. 71 UINT16 tCWL; ///< Offset 8 Number of tCK cycles for the channel DIMM's minimum CAS write latency time. 72 UINT16 tFAW; ///< Offset 10 Number of tCK cycles for the channel DIMM's minimum four activate window delay time. 73 UINT16 tRAS; ///< Offset 12 Number of tCK cycles for the channel DIMM's minimum active to precharge delay time. 74 UINT16 tRCDtRP; ///< Offset 14 Number of tCK cycles for the channel DIMM's minimum RAS# to CAS# delay time and Row Precharge delay time 75 UINT16 tREFI; ///< Offset 16 Number of tCK cycles for the channel DIMM's minimum Average Periodic Refresh Interval. 76 UINT16 tRFC; ///< Offset 18 Number of tCK cycles for the channel DIMM's minimum refresh recovery delay time. 77 UINT16 tRPab; ///< Offset 20 Number of tCK cycles for the channel DIMM's minimum row precharge delay time for all banks. 78 UINT16 tRRD; ///< Offset 22 Number of tCK cycles for the channel DIMM's minimum row active to row active delay time. 79 UINT16 tRTP; ///< Offset 24 Number of tCK cycles for the channel DIMM's minimum internal read to precharge command delay time. 80 UINT16 tWR; ///< Offset 26 Number of tCK cycles for the channel DIMM's minimum write recovery time. 81 UINT16 tWTR; ///< Offset 28 Number of tCK cycles for the channel DIMM's minimum internal write to read command delay time. 82 UINT16 tRRD_L; ///< Offset 30 Number of tCK cycles for the channel DIMM's minimum row active to row active delay time for same bank groups. 83 UINT16 tRRD_S; ///< Offset 32 Number of tCK cycles for the channel DIMM's minimum row active to row active delay time for different bank groups. 84 UINT16 tWTR_L; ///< Offset 34 Number of tCK cycles for the channel DIMM's minimum internal write to read command delay time for same bank groups. 85 UINT16 tWTR_S; ///< Offset 36 Number of tCK cycles for the channel DIMM's minimum internal write to read command delay time for different bank groups. 86 UINT8 Rsvd[2]; ///< Offset 38 87 } MEMORY_TIMING; 88 89 typedef struct { 90 UINT8 SG; ///< Number of tCK cycles between transactions in the same bank group. 91 UINT8 DG; ///< Number of tCK cycles between transactions when switching bank groups. 92 UINT8 DR; ///< Number of tCK cycles between transactions when switching between Ranks (in the same DIMM). 93 UINT8 DD; ///< Number of tCK cycles between transactions when switching between DIMMs 94 } TURNAROUND_TIMING; 95 96 // @todo use the MemInfoHob data instead of duplicate structure. 97 /// 98 /// Memory information Data Structure 99 /// 100 typedef struct { 101 MEMORY_TIMING Timing[PROFILE_NUM]; ///< Offset 0 Timming information for the DIMM 102 UINT32 memSize; ///< Offset 128 Total physical memory size 103 UINT16 ddrFreq; ///< Offset 132 DDR Current Frequency 104 UINT16 ddrFreqMax; ///< Offset 134 DDR Maximum Frequency 105 UINT16 dimmSize[NODE_NUM * CH_NUM * DIMM_NUM]; ///< Offset 136 Size of each DIMM 106 UINT16 VddVoltage[PROFILE_NUM]; ///< Offset 144 The voltage setting for the DIMM 107 UINT8 DimmStatus[NODE_NUM * CH_NUM * DIMM_NUM]; ///< Offset 152 The enumeration value from MrcDimmSts 108 UINT8 RankInDimm[NODE_NUM * CH_NUM * DIMM_NUM]; ///< Offset 156 No. of ranks in a dimm 109 UINT8 *DimmsSpdData[NODE_NUM * CH_NUM * DIMM_NUM]; ///< Offset 160 SPD data of each DIMM 110 UINT8 RefClk; ///< Offset 192 Reference Clock 111 UINT8 Ratio; ///< Offset 193 Clock Multiplier 112 BOOLEAN EccSupport; ///< Offset 194 ECC supported or not 113 UINT8 Profile; ///< Offset 195 Currently running memory profile 114 UINT8 XmpProfileEnable; ///< Offset 196: 0 = no XMP DIMMs in system 115 UINT8 DdrType; ///< Offset 197: Current DDR type, see DDR_TYPE_xxx defines above 116 UINT8 Reserved[2]; ///< Offset 198 Reserved bytes for future use 117 UINT32 DefaultXmptCK[XMP_PROFILE_NUM]; ///< Offset 200 The Default XMP tCK values read from SPD. 118 TURNAROUND_TIMING tRd2Rd[CH_NUM]; ///< Read-to-Read Turn Around Timings 119 TURNAROUND_TIMING tRd2Wr[CH_NUM]; ///< Read-to-Write Turn Around Timings 120 TURNAROUND_TIMING tWr2Rd[CH_NUM]; ///< Write-to-Read Turn Around Timings 121 TURNAROUND_TIMING tWr2Wr[CH_NUM]; ///< Write-to-Write Turn Around Timings 122 } MEMORY_INFO_DATA; 123 #pragma pack() 124 125 /// 126 /// Memory information Protocol definition 127 /// 128 typedef struct { 129 MEMORY_INFO_DATA MemInfoData; ///< Memory Information Data Structure 130 } MEM_INFO_PROTOCOL; 131 132 #endif 133