1 /** @file
2   This is part of the implementation of an Intel Graphics drivers OpRegion /
3   Software SCI interface between system BIOS, ASL code, and Graphics drivers.
4 
5   Copyright (c) 2019 - 2020 Intel Corporation. All rights reserved. <BR>
6 
7   SPDX-License-Identifier: BSD-2-Clause-Patent
8 **/
9 
10 #ifndef _IGD_OPREGION_INIT_H_
11 #define _IGD_OPREGION_INIT_H_
12 
13 ///
14 /// Statements that include other header files.
15 ///
16 #include <Uefi/UefiBaseType.h>
17 #include <Library/UefiBootServicesTableLib.h>
18 #include <Library/S3BootScriptLib.h>
19 #include <Library/DebugLib.h>
20 #include <Library/BaseMemoryLib.h>
21 #include <Library/MemoryAllocationLib.h>
22 #include <Library/IoLib.h>
23 #include <Library/PciSegmentLib.h>
24 #include <PchAccess.h>
25 #include <Library/PchCycleDecodingLib.h>
26 #include <Library/PmcLib.h>
27 #include <SaAccess.h>
28 #include <IndustryStandard/Pci22.h>
29 #include <CpuRegs.h>
30 #include <SaInit.h>
31 #include <Library/CpuPlatformLib.h>
32 #include <Library/HobLib.h>
33 #include <SiConfigHob.h>
34 
35 ///
36 /// Driver Consumed Protocol Prototypes
37 ///
38 #include <Protocol/PciIo.h>
39 #include <Protocol/PciRootBridgeIo.h>
40 #include <Protocol/LegacyBios.h>
41 #include <Protocol/SaPolicy.h>
42 
43 
44 #include <Private/Protocol/SaNvsArea.h>
45 
46 ///
47 /// Driver Produced Protocol Prototypes
48 ///
49 #include <Protocol/IgdOpRegion.h>
50 
51 ///
52 ///
53 /// OpRegion (Miscellaneous) defines.
54 ///
55 /// OpRegion Header defines.
56 ///
57 typedef UINT16  STRING_REF;
58 #define HEADER_SIGNATURE            "IntelGraphicsMem"
59 #define HEADER_SIZE                 0x2000
60 #define HEADER_OPREGION_VER         0x0200
61 #define HEADER_OPREGION_REV         0x00
62 #define HEADER_MBOX_SUPPORT         (HD_MBOX5 + HD_MBOX4 + HD_MBOX3 + HD_MBOX2 + HD_MBOX1)
63 #define HD_MBOX1                    BIT0
64 #define HD_MBOX2                    BIT1
65 #define HD_MBOX3                    BIT2
66 #define HD_MBOX4                    BIT3
67 #define HD_MBOX5                    BIT4
68 #define SVER_SIZE                   32
69 
70 ///
71 /// OpRegion Mailbox 1 EQUates.
72 ///
73 /// OpRegion Mailbox 3 EQUates.
74 ///
75 #define ALS_ENABLE            BIT0
76 #define BLC_ENABLE            BIT1
77 #define BACKLIGHT_BRIGHTNESS  0xFF
78 #define FIELD_VALID_BIT       BIT31
79 #define PFIT_ENABLE           BIT2
80 #define PFIT_OPRN_AUTO        0x00000000
81 #define PFIT_OPRN_SCALING     0x00000007
82 #define PFIT_OPRN_OFF         0x00000000
83 #define PFIT_SETUP_AUTO       0
84 #define PFIT_SETUP_SCALING    1
85 #define PFIT_SETUP_OFF        2
86 #define INIT_BRIGHT_LEVEL     0x64
87 #define PFIT_STRETCH          6
88 
89 ///
90 /// Video BIOS / VBT defines
91 ///
92 #define OPTION_ROM_SIGNATURE    0xAA55
93 #define VBIOS_LOCATION_PRIMARY  0xC0000
94 
95 #define VBT_SIGNATURE           SIGNATURE_32 ('$', 'V', 'B', 'T')
96 ///
97 /// Typedef stuctures
98 ///
99 #pragma pack(1)
100 typedef struct {
101   UINT16  Signature;  /// 0xAA55
102   UINT8   Size512;
103   UINT8   Reserved[21];
104   UINT16  PcirOffset;
105   UINT16  VbtOffset;
106 } INTEL_VBIOS_OPTION_ROM_HEADER;
107 #pragma pack()
108 
109 #pragma pack(1)
110 typedef struct {
111   UINT32  Signature;  /// "PCIR"
112   UINT16  VendorId;   /// 0x8086
113   UINT16  DeviceId;
114   UINT16  Reserved0;
115   UINT16  Length;
116   UINT8   Revision;
117   UINT8   ClassCode[3];
118   UINT16  ImageLength;
119   UINT16  CodeRevision;
120   UINT8   CodeType;
121   UINT8   Indicator;
122   UINT16  Reserved1;
123 } INTEL_VBIOS_PCIR_STRUCTURE;
124 #pragma pack()
125 
126 #pragma pack(1)
127 typedef struct {
128   UINT8   HeaderSignature[20];
129   UINT16  HeaderVersion;
130   UINT16  HeaderSize;
131   UINT16  HeaderVbtSize;
132   UINT8   HeaderVbtCheckSum;
133   UINT8   HeaderReserved;
134   UINT32  HeaderOffsetVbtDataBlock;
135   UINT32  HeaderOffsetAim1;
136   UINT32  HeaderOffsetAim2;
137   UINT32  HeaderOffsetAim3;
138   UINT32  HeaderOffsetAim4;
139   UINT8   DataHeaderSignature[16];
140   UINT16  DataHeaderVersion;
141   UINT16  DataHeaderSize;
142   UINT16  DataHeaderDataBlockSize;
143   UINT8   CoreBlockId;
144   UINT16  CoreBlockSize;
145   UINT16  CoreBlockBiosSize;
146   UINT8   CoreBlockBiosType;
147   UINT8   CoreBlockReleaseStatus;
148   UINT8   CoreBlockHWSupported;
149   UINT8   CoreBlockIntegratedHW;
150   UINT8   CoreBlockBiosBuild[4];
151   UINT8   CoreBlockBiosSignOn[155];
152 } VBIOS_VBT_STRUCTURE;
153 #pragma pack()
154 ///
155 /// Driver Private Function definitions
156 ///
157 
158 /**
159   Graphics OpRegion / Software SCI driver installation function.
160 
161   @retval EFI_SUCCESS     - The driver installed without error.
162   @retval EFI_ABORTED     - The driver encountered an error and could not complete
163                             installation of the ACPI tables.
164 **/
165 EFI_STATUS
166 IgdOpRegionInit (
167   VOID
168   );
169 
170 /**
171   Get Intel video BIOS VBT information (i.e. Pointer to VBT and VBT size).
172   The VBT (Video BIOS Table) is a block of customizable data that is built
173   within the video BIOS and edited by customers.
174 
175   @retval EFI_SUCCESS            - Video BIOS VBT information returned.
176   @exception EFI_UNSUPPORTED     - Could not find VBT information (*VBiosVbtPtr = NULL).
177 **/
178 EFI_STATUS
179 GetVBiosVbtEndOfDxe (
180   VOID
181   );
182 
183 /**
184   Update Graphics OpRegion after PCI enumeration.
185 
186   @retval EFI_SUCCESS     - The function completed successfully.
187 **/
188 EFI_STATUS
189 UpdateIgdOpRegionEndOfDxe (
190   VOID
191   );
192 #endif
193