1 /** @file
2 Print whole PCH_PREMEM_POLICY_PPI
3
4 Copyright (c) 2017 - 2020 Intel Corporation. All rights reserved.<BR>
5 SPDX-License-Identifier: BSD-2-Clause-Patent
6
7 **/
8 #include "PeiPchPolicyLibrary.h"
9 #include <Library/ConfigBlockLib.h>
10
11 /**
12 Print PCH_GENERAL_PREMEM_CONFIG and serial out.
13
14 @param[in] PchGeneralPreMemConfig Pointer to a PCH_GENERAL_PREMEM_CONFIG that provides the platform setting
15
16 **/
17 VOID
PchPrintGeneralPreMemConfig(IN CONST PCH_GENERAL_PREMEM_CONFIG * PchGeneralPreMemConfig)18 PchPrintGeneralPreMemConfig (
19 IN CONST PCH_GENERAL_PREMEM_CONFIG *PchGeneralPreMemConfig
20 )
21 {
22 DEBUG ((DEBUG_INFO, "------------------ PCH General PreMem Config -----------\n"));
23 DEBUG ((DEBUG_INFO, " AcpiBase= %x\n", PchGeneralPreMemConfig->AcpiBase));
24 DEBUG ((DEBUG_INFO, " Port80Route= %x\n", PchGeneralPreMemConfig->Port80Route));
25 }
26
27 /**
28 Print PCH_DCI_PREMEM_CONFIG and serial out.
29
30 @param[in] DciPreMemConfig Pointer to a PCH_DCI_PREMEM_CONFIG that provides the platform setting
31
32 **/
33 VOID
PchPrintDciPreMemConfig(IN CONST PCH_DCI_PREMEM_CONFIG * DciPreMemConfig)34 PchPrintDciPreMemConfig (
35 IN CONST PCH_DCI_PREMEM_CONFIG *DciPreMemConfig
36 )
37 {
38 DEBUG ((DEBUG_INFO, "------------------ PCH DCI PreMem Config ---------------\n"));
39 DEBUG ((DEBUG_INFO, "DciEn= %x\n", DciPreMemConfig->DciEn));
40 }
41
42 /**
43 Print PCH_WDT_PREMEM_CONFIG and serial out.
44
45 @param[in] WdtPreMemConfig Pointer to a PCH_WDT_PREMEM_CONFIG that provides the platform setting
46
47 **/
48 VOID
PchPrintWdtPreMemConfig(IN CONST PCH_WDT_PREMEM_CONFIG * WdtPreMemConfig)49 PchPrintWdtPreMemConfig (
50 IN CONST PCH_WDT_PREMEM_CONFIG *WdtPreMemConfig
51 )
52 {
53 DEBUG ((DEBUG_INFO, "------------------ PCH WDT PreMem Config ---------------\n"));
54 DEBUG ((DEBUG_INFO, "DisableAndLock= %x\n", WdtPreMemConfig->DisableAndLock));
55 }
56
57 /**
58 Print PCH_TRACE_HUB_CONFIG and serial out.
59
60 @param[in] TraceHubConfig Pointer to a PCH_TRACE_HUB_CONFIG that provides the platform setting
61
62 **/
63 VOID
PchPrintTraceHubPreMemConfig(IN CONST PCH_TRACE_HUB_PREMEM_CONFIG * TraceHubPreMemConfig)64 PchPrintTraceHubPreMemConfig (
65 IN CONST PCH_TRACE_HUB_PREMEM_CONFIG *TraceHubPreMemConfig
66 )
67 {
68 DEBUG ((DEBUG_INFO, "------------------ PCH TraceHub PreMem Config ----------\n"));
69 DEBUG ((DEBUG_INFO, "EnableMode= %x\n", TraceHubPreMemConfig->EnableMode));
70 DEBUG ((DEBUG_INFO, "MemReg0Size= %x\n", TraceHubPreMemConfig->MemReg0Size));
71 DEBUG ((DEBUG_INFO, "MemReg1Size= %x\n", TraceHubPreMemConfig->MemReg1Size));
72 }
73
74 /**
75 Print PCH_HPET_PREMEM_CONFIG and serial out.
76
77 @param[in] HpetPreMemConfig Pointer to a PCH_HPET_CONFIG that provides the platform setting
78
79 **/
80 VOID
PchPrintHpetPreMemConfig(IN CONST PCH_HPET_PREMEM_CONFIG * HpetPreMemConfig)81 PchPrintHpetPreMemConfig (
82 IN CONST PCH_HPET_PREMEM_CONFIG *HpetPreMemConfig
83 )
84 {
85 DEBUG ((DEBUG_INFO, "------------------ PCH HPET PreMem Config --------------\n"));
86 DEBUG ((DEBUG_INFO, " Enable %x\n", HpetPreMemConfig->Enable));
87 DEBUG ((DEBUG_INFO, " BdfValid %x\n", HpetPreMemConfig->BdfValid));
88 DEBUG ((DEBUG_INFO, " BusNumber %x\n", HpetPreMemConfig->BusNumber));
89 DEBUG ((DEBUG_INFO, " DeviceNumber %x\n", HpetPreMemConfig->DeviceNumber));
90 DEBUG ((DEBUG_INFO, " FunctionNumber %x\n", HpetPreMemConfig->FunctionNumber));
91 DEBUG ((DEBUG_INFO, " Base %x\n", HpetPreMemConfig->Base));
92 }
93
94 /**
95 Print PCH_SMBUS_CONFIG and serial out.
96
97 @param[in] SmbusConfig Pointer to a PCH_SMBUS_CONFIG that provides the platform setting
98
99 **/
100 VOID
PchPrintSmbusPreMemConfig(IN CONST PCH_SMBUS_PREMEM_CONFIG * SmbusPreMemConfig)101 PchPrintSmbusPreMemConfig (
102 IN CONST PCH_SMBUS_PREMEM_CONFIG *SmbusPreMemConfig
103 )
104 {
105 UINT32 Index;
106
107 DEBUG ((DEBUG_INFO, "------------------ PCH SMBUS PreMem Config -------------\n"));
108 DEBUG ((DEBUG_INFO, " Enable= %x\n", SmbusPreMemConfig->Enable));
109 DEBUG ((DEBUG_INFO, " ArpEnable= %x\n", SmbusPreMemConfig->ArpEnable));
110 DEBUG ((DEBUG_INFO, " DynamicPowerGating= %x\n", SmbusPreMemConfig->DynamicPowerGating));
111 DEBUG ((DEBUG_INFO, " SpdWriteDisable= %x\n", SmbusPreMemConfig->SpdWriteDisable));
112 DEBUG ((DEBUG_INFO, " SmbusIoBase= %x\n", SmbusPreMemConfig->SmbusIoBase));
113 DEBUG ((DEBUG_INFO, " NumRsvdSmbusAddresses= %x\n", SmbusPreMemConfig->NumRsvdSmbusAddresses));
114 DEBUG ((DEBUG_INFO, " RsvdSmbusAddressTable= {"));
115 for (Index = 0; Index < SmbusPreMemConfig->NumRsvdSmbusAddresses; ++Index) {
116 DEBUG ((DEBUG_INFO, " %02xh", SmbusPreMemConfig->RsvdSmbusAddressTable[Index]));
117 }
118 DEBUG ((DEBUG_INFO, " }\n"));
119 }
120
121 /**
122 Print PCH_LPC_PREMEM_CONFIG and serial out.
123
124 @param[in] LpcPreMemConfig Pointer to a PCH_LPC_PREMEM_CONFIG that provides the platform setting
125
126 **/
127 VOID
PchPrintLpcPreMemConfig(IN CONST PCH_LPC_PREMEM_CONFIG * LpcPreMemConfig)128 PchPrintLpcPreMemConfig (
129 IN CONST PCH_LPC_PREMEM_CONFIG *LpcPreMemConfig
130 )
131 {
132 DEBUG ((DEBUG_INFO, "------------------ PCH LPC PreMem Config ---------------\n"));
133 DEBUG ((DEBUG_INFO, "EnhancePort8xhDecoding= %x\n", LpcPreMemConfig->EnhancePort8xhDecoding));
134 }
135
136 /**
137 Print PCH_HSIO_PCIE_PREMEM_CONFIG and serial out.
138
139 @param[in] HsioPciePreMemConfig Pointer to a PCH_HSIO_PCIE_PREMEM_CONFIG that provides the platform setting
140
141 **/
142 VOID
PchPrintHsioPciePreMemConfig(IN CONST PCH_HSIO_PCIE_PREMEM_CONFIG * HsioPciePreMemConfig)143 PchPrintHsioPciePreMemConfig (
144 IN CONST PCH_HSIO_PCIE_PREMEM_CONFIG *HsioPciePreMemConfig
145 )
146 {
147 UINT32 Index;
148
149 DEBUG ((DEBUG_INFO, "------------------ HSIO PCIE PreMem Config -------------\n"));
150 DEBUG ((DEBUG_INFO, " PciePllSsc = %x\n", HsioPciePreMemConfig->PciePllSsc));
151 for (Index = 0; Index < GetPchMaxPciePortNum (); Index++) {
152 DEBUG ((DEBUG_INFO, " Rp[%d] HsioRxSetCtleEnable= %x\n", Index, HsioPciePreMemConfig->Lane[Index].HsioRxSetCtleEnable));
153 DEBUG ((DEBUG_INFO, " Rp[%d] HsioRxSetCtle= %x\n", Index, HsioPciePreMemConfig->Lane[Index].HsioRxSetCtle));
154 DEBUG ((DEBUG_INFO, " Rp[%d] HsioTxGen1DownscaleAmpEnable= %x\n", Index, HsioPciePreMemConfig->Lane[Index].HsioTxGen1DownscaleAmpEnable));
155 DEBUG ((DEBUG_INFO, " Rp[%d] HsioTxGen1DownscaleAmp= %x\n", Index, HsioPciePreMemConfig->Lane[Index].HsioTxGen1DownscaleAmp));
156 DEBUG ((DEBUG_INFO, " Rp[%d] HsioTxGen2DownscaleAmpEnable= %x\n", Index, HsioPciePreMemConfig->Lane[Index].HsioTxGen2DownscaleAmpEnable));
157 DEBUG ((DEBUG_INFO, " Rp[%d] HsioTxGen2DownscaleAmp= %x\n", Index, HsioPciePreMemConfig->Lane[Index].HsioTxGen2DownscaleAmp));
158 DEBUG ((DEBUG_INFO, " Rp[%d] HsioTxGen3DownscaleAmpEnable= %x\n", Index, HsioPciePreMemConfig->Lane[Index].HsioTxGen3DownscaleAmpEnable));
159 DEBUG ((DEBUG_INFO, " Rp[%d] HsioTxGen3DownscaleAmp= %x\n", Index, HsioPciePreMemConfig->Lane[Index].HsioTxGen3DownscaleAmp));
160 DEBUG ((DEBUG_INFO, " Rp[%d] HsioTxGen1DeEmphEnable= %x\n", Index, HsioPciePreMemConfig->Lane[Index].HsioTxGen1DeEmphEnable));
161 DEBUG ((DEBUG_INFO, " Rp[%d] HsioTxGen1DeEmph= %x\n", Index, HsioPciePreMemConfig->Lane[Index].HsioTxGen1DeEmph));
162 DEBUG ((DEBUG_INFO, " Rp[%d] HsioTxGen2DeEmph3p5Enable= %x\n", Index, HsioPciePreMemConfig->Lane[Index].HsioTxGen2DeEmph3p5Enable));
163 DEBUG ((DEBUG_INFO, " Rp[%d] HsioTxGen2DeEmph3p5= %x\n", Index, HsioPciePreMemConfig->Lane[Index].HsioTxGen2DeEmph3p5));
164 DEBUG ((DEBUG_INFO, " Rp[%d] HsioTxGen2DeEmph6p0Enable= %x\n", Index, HsioPciePreMemConfig->Lane[Index].HsioTxGen2DeEmph6p0Enable));
165 DEBUG ((DEBUG_INFO, " Rp[%d] HsioTxGen2DeEmph6p0= %x\n", Index, HsioPciePreMemConfig->Lane[Index].HsioTxGen2DeEmph6p0));
166 }
167 }
168
169 /**
170 Print PCH_HSIO_SATA_PREMEM_CONFIG and serial out.
171
172 @param[in] HsioSataPreMemConfig Pointer to a PCH_HSIO_SATA_PREMEM_CONFIG that provides the platform setting
173
174 **/
175 VOID
PchPrintHsioSataPreMemConfig(IN CONST PCH_HSIO_SATA_PREMEM_CONFIG * HsioSataPreMemConfig)176 PchPrintHsioSataPreMemConfig (
177 IN CONST PCH_HSIO_SATA_PREMEM_CONFIG *HsioSataPreMemConfig
178 )
179 {
180 UINT32 Index;
181
182 DEBUG ((DEBUG_INFO, "------------------ HSIO SATA PreMem Config -------------\n"));
183 for (Index = 0; Index < GetPchMaxSataPortNum (); Index++) {
184 DEBUG ((DEBUG_INFO, " PortSettings[%d] HsioRxGen1EqBoostMagEnable= %x\n", Index, HsioSataPreMemConfig->PortLane[Index].HsioRxGen1EqBoostMagEnable));
185 DEBUG ((DEBUG_INFO, " PortSettings[%d] HsioRxGen1EqBoostMag= %x\n", Index, HsioSataPreMemConfig->PortLane[Index].HsioRxGen1EqBoostMag));
186 DEBUG ((DEBUG_INFO, " PortSettings[%d] HsioRxGen2EqBoostMagEnable= %x\n", Index, HsioSataPreMemConfig->PortLane[Index].HsioRxGen2EqBoostMagEnable));
187 DEBUG ((DEBUG_INFO, " PortSettings[%d] HsioRxGen2EqBoostMag= %x\n", Index, HsioSataPreMemConfig->PortLane[Index].HsioRxGen2EqBoostMag));
188 DEBUG ((DEBUG_INFO, " PortSettings[%d] HsioRxGen3EqBoostMagEnable= %x\n", Index, HsioSataPreMemConfig->PortLane[Index].HsioRxGen3EqBoostMagEnable));
189 DEBUG ((DEBUG_INFO, " PortSettings[%d] HsioRxGen3EqBoostMag= %x\n", Index, HsioSataPreMemConfig->PortLane[Index].HsioRxGen3EqBoostMag));
190 DEBUG ((DEBUG_INFO, " PortSettings[%d] HsioTxGen1DownscaleAmpEnable= %x\n", Index, HsioSataPreMemConfig->PortLane[Index].HsioTxGen1DownscaleAmpEnable));
191 DEBUG ((DEBUG_INFO, " PortSettings[%d] HsioTxGen1DownscaleAmp= %x\n", Index, HsioSataPreMemConfig->PortLane[Index].HsioTxGen1DownscaleAmp));
192 DEBUG ((DEBUG_INFO, " PortSettings[%d] HsioTxGen2DownscaleAmpEnable= %x\n", Index, HsioSataPreMemConfig->PortLane[Index].HsioTxGen2DownscaleAmpEnable));
193 DEBUG ((DEBUG_INFO, " PortSettings[%d] HsioTxGen2DownscaleAmp= %x\n", Index, HsioSataPreMemConfig->PortLane[Index].HsioTxGen2DownscaleAmp));
194 DEBUG ((DEBUG_INFO, " PortSettings[%d] HsioTxGen3DownscaleAmpEnable= %x\n", Index, HsioSataPreMemConfig->PortLane[Index].HsioTxGen3DownscaleAmpEnable));
195 DEBUG ((DEBUG_INFO, " PortSettings[%d] HsioTxGen3DownscaleAmp= %x\n", Index, HsioSataPreMemConfig->PortLane[Index].HsioTxGen3DownscaleAmp));
196 DEBUG ((DEBUG_INFO, " PortSettings[%d] HsioTxGen1DeEmphEnable= %x\n", Index, HsioSataPreMemConfig->PortLane[Index].HsioTxGen1DeEmphEnable));
197 DEBUG ((DEBUG_INFO, " PortSettings[%d] HsioTxGen1DeEmph= %x\n", Index, HsioSataPreMemConfig->PortLane[Index].HsioTxGen1DeEmph));
198 DEBUG ((DEBUG_INFO, " PortSettings[%d] HsioTxGen2DeEmphEnable= %x\n", Index, HsioSataPreMemConfig->PortLane[Index].HsioTxGen2DeEmphEnable));
199 DEBUG ((DEBUG_INFO, " PortSettings[%d] HsioTxGen2DeEmph= %x\n", Index, HsioSataPreMemConfig->PortLane[Index].HsioTxGen2DeEmph));
200 DEBUG ((DEBUG_INFO, " PortSettings[%d] HsioTxGen3DeEmphEnable= %x\n", Index, HsioSataPreMemConfig->PortLane[Index].HsioTxGen3DeEmphEnable));
201 DEBUG ((DEBUG_INFO, " PortSettings[%d] HsioTxGen3DeEmph= %x\n", Index, HsioSataPreMemConfig->PortLane[Index].HsioTxGen3DeEmph));
202 }
203 }
204
205 /**
206 Print PCH_HSIO_PREMEM_CONFIG and serial out.
207
208 @param[in] HsioPreMemConfig Pointer to a PCH_HSIO_PREMEM_CONFIG that provides the platform setting
209
210 **/
211 VOID
PchPrintHsioPreMemConfig(IN CONST PCH_HSIO_PREMEM_CONFIG * HsioPreMemConfig)212 PchPrintHsioPreMemConfig (
213 IN CONST PCH_HSIO_PREMEM_CONFIG *HsioPreMemConfig
214 )
215 {
216 DEBUG ((DEBUG_INFO, "------------------ HSIO PreMem Config ------------------\n"));
217 DEBUG ((DEBUG_INFO, " ChipsetInitMessage : 0x%x\n", HsioPreMemConfig->ChipsetInitMessage));
218 DEBUG ((DEBUG_INFO, " BypassPhySyncReset : 0x%x\n", HsioPreMemConfig->BypassPhySyncReset));
219 }
220
221 /**
222 Print PCH_PCIE_RP_PREMEM_CONFIG and serial out.
223
224 @param[in] PcieRpPreMemConfig Pointer to a PCH_PCIE_RP_PREMEM_CONFIG that provides the platform setting
225
226 **/
227 VOID
PchPrintPcieRpPreMemConfig(IN CONST PCH_PCIE_RP_PREMEM_CONFIG * PcieRpPreMemConfig)228 PchPrintPcieRpPreMemConfig (
229 IN CONST PCH_PCIE_RP_PREMEM_CONFIG *PcieRpPreMemConfig
230 )
231 {
232 UINT32 Index;
233 DEBUG ((DEBUG_INFO, "------------------ PCH PCIe RP PreMem Config -----------\n"));
234
235 for (Index = 0; Index < GetPchMaxPciePortNum (); Index++) {
236 DEBUG ((DEBUG_INFO, " Port[%d] RpEnabled= %x\n", Index, (PcieRpPreMemConfig->RpEnabledMask & (UINT32) (1 << Index)) != 0 ));
237 }
238 }
239
240
241 /**
242 Print whole PCH_POLICY_PPI and serial out.
243
244 @param[in] SiPreMemPolicyPpi The RC PREMEM Policy PPI instance
245
246 **/
247 VOID
PchPreMemPrintPolicyPpi(IN SI_PREMEM_POLICY_PPI * SiPreMemPolicyPpi)248 PchPreMemPrintPolicyPpi (
249 IN SI_PREMEM_POLICY_PPI *SiPreMemPolicyPpi
250 )
251 {
252 DEBUG_CODE_BEGIN ();
253 EFI_STATUS Status;
254 PCH_GENERAL_PREMEM_CONFIG *PchGeneralPreMemConfig;
255 PCH_DCI_PREMEM_CONFIG *DciPreMemConfig;
256 PCH_WDT_PREMEM_CONFIG *WdtPreMemConfig;
257 PCH_TRACE_HUB_PREMEM_CONFIG *TraceHubPreMemConfig;
258 PCH_HPET_PREMEM_CONFIG *HpetPreMemConfig;
259 PCH_SMBUS_PREMEM_CONFIG *SmbusPreMemConfig;
260 PCH_LPC_PREMEM_CONFIG *LpcPreMemConfig;
261 PCH_HSIO_PCIE_PREMEM_CONFIG *HsioPciePreMemConfig;
262 PCH_HSIO_SATA_PREMEM_CONFIG *HsioSataPreMemConfig;
263 PCH_HSIO_PREMEM_CONFIG *HsioPreMemConfig;
264 PCH_PCIE_RP_PREMEM_CONFIG *PcieRpPreMemConfig;
265
266 Status = GetConfigBlock ((VOID *) SiPreMemPolicyPpi, &gPchGeneralPreMemConfigGuid, (VOID *) &PchGeneralPreMemConfig);
267 ASSERT_EFI_ERROR (Status);
268 Status = GetConfigBlock ((VOID *) SiPreMemPolicyPpi, &gDciPreMemConfigGuid, (VOID *) &DciPreMemConfig);
269 ASSERT_EFI_ERROR (Status);
270 Status = GetConfigBlock ((VOID *) SiPreMemPolicyPpi, &gWatchDogPreMemConfigGuid, (VOID *) &WdtPreMemConfig);
271 ASSERT_EFI_ERROR (Status);
272 Status = GetConfigBlock ((VOID *) SiPreMemPolicyPpi, &gTraceHubPreMemConfigGuid, (VOID *) &TraceHubPreMemConfig);
273 ASSERT_EFI_ERROR (Status);
274 Status = GetConfigBlock ((VOID *) SiPreMemPolicyPpi, &gHpetPreMemConfigGuid, (VOID *) &HpetPreMemConfig);
275 ASSERT_EFI_ERROR (Status);
276 Status = GetConfigBlock ((VOID *) SiPreMemPolicyPpi, &gSmbusPreMemConfigGuid, (VOID *) &SmbusPreMemConfig);
277 ASSERT_EFI_ERROR (Status);
278 Status = GetConfigBlock ((VOID *) SiPreMemPolicyPpi, &gLpcPreMemConfigGuid, (VOID *) &LpcPreMemConfig);
279 ASSERT_EFI_ERROR (Status);
280 Status = GetConfigBlock ((VOID *) SiPreMemPolicyPpi, &gHsioPciePreMemConfigGuid, (VOID *) &HsioPciePreMemConfig);
281 ASSERT_EFI_ERROR (Status);
282 Status = GetConfigBlock ((VOID *) SiPreMemPolicyPpi, &gHsioSataPreMemConfigGuid, (VOID *) &HsioSataPreMemConfig);
283 ASSERT_EFI_ERROR (Status);
284 Status = GetConfigBlock ((VOID *) SiPreMemPolicyPpi, &gHsioPreMemConfigGuid, (VOID *) &HsioPreMemConfig);
285 ASSERT_EFI_ERROR (Status);
286 Status = GetConfigBlock ((VOID *) SiPreMemPolicyPpi, &gPcieRpPreMemConfigGuid, (VOID *) &PcieRpPreMemConfig);
287 ASSERT_EFI_ERROR (Status);
288 DEBUG ((DEBUG_INFO, "------------------------ PCH Print PreMemPolicy Start ------------------------\n"));
289 DEBUG ((DEBUG_INFO, " Revision= %x\n", SiPreMemPolicyPpi->TableHeader.Header.Revision));
290
291 PchPrintGeneralPreMemConfig (PchGeneralPreMemConfig);
292 PchPrintDciPreMemConfig (DciPreMemConfig);
293 PchPrintWdtPreMemConfig (WdtPreMemConfig);
294 PchPrintTraceHubPreMemConfig (TraceHubPreMemConfig);
295 PchPrintHpetPreMemConfig (HpetPreMemConfig);
296 PchPrintSmbusPreMemConfig (SmbusPreMemConfig);
297 PchPrintLpcPreMemConfig (LpcPreMemConfig);
298 PchPrintHsioPciePreMemConfig (HsioPciePreMemConfig);
299 PchPrintHsioSataPreMemConfig (HsioSataPreMemConfig);
300 PchPrintHsioPreMemConfig (HsioPreMemConfig);
301 PchPrintPcieRpPreMemConfig (PcieRpPreMemConfig);
302
303 DEBUG ((DEBUG_INFO, "------------------------ PCH Print PreMemPolicy End --------------------------\n"));
304 DEBUG_CODE_END ();
305 }
306
307