1 /** @file 2 This protocol provides the memory information data, such as 3 total physical memory size, memory frequency, memory size 4 of each dimm and rank. 5 6 Copyright (c) 2017, Intel Corporation. All rights reserved.<BR> 7 SPDX-License-Identifier: BSD-2-Clause-Patent 8 9 **/ 10 #ifndef _MEM_INFO_PROTOCOL_H_ 11 #define _MEM_INFO_PROTOCOL_H_ 12 13 14 // 15 // Extern the GUID for protocol users. 16 // 17 extern EFI_GUID gMemInfoProtocolGuid; 18 19 // 20 // Protocol definitions 21 // 22 #define NODE_NUM 1 23 #define CH_NUM 2 24 #define DIMM_NUM 2 25 #define RANK_NUM 2 26 #define SLOT_NUM (CH_NUM * DIMM_NUM) 27 #define PROFILE_NUM 4 // number of memory profiles supported 28 #define XMP_PROFILE_NUM 2 // number of XMP profiles supported 29 30 // 31 // Matches MrcDdrType enum in MRC 32 // 33 #ifndef MRC_DDR_TYPE_DDR4 34 #define MRC_DDR_TYPE_DDR4 0 35 #endif 36 #ifndef MRC_DDR_TYPE_DDR3 37 #define MRC_DDR_TYPE_DDR3 1 38 #endif 39 #ifndef MRC_DDR_TYPE_LPDDR3 40 #define MRC_DDR_TYPE_LPDDR3 2 41 #endif 42 #ifndef MRC_DDR_TYPE_UNKNOWN 43 #define MRC_DDR_TYPE_UNKNOWN 3 44 #endif 45 46 // 47 // Matches MrcDimmSts enum in MRC 48 // 49 #ifndef DIMM_ENABLED 50 #define DIMM_ENABLED 0 // DIMM/rank Pair is enabled, presence will be detected. 51 #endif 52 #ifndef DIMM_DISABLED 53 #define DIMM_DISABLED 1 // DIMM/rank Pair is disabled, regardless of presence. 54 #endif 55 #ifndef DIMM_PRESENT 56 #define DIMM_PRESENT 2 // There is a DIMM present in the slot/rank pair and it will be used. 57 #endif 58 #ifndef DIMM_NOT_PRESENT 59 #define DIMM_NOT_PRESENT 3 // There is no DIMM present in the slot/rank pair. 60 #endif 61 62 #pragma pack(1) 63 /// 64 /// Memory timing Structure 65 /// 66 typedef struct { 67 UINT32 tCK; ///< Offset 0 Memory cycle time, in femtoseconds. 68 UINT16 NMode; ///< Offset 4 Number of tCK cycles for the channel DIMM's command rate mode. 69 UINT16 tCL; ///< Offset 6 Number of tCK cycles for the channel DIMM's CAS latency. 70 UINT16 tCWL; ///< Offset 8 Number of tCK cycles for the channel DIMM's minimum CAS write latency time. 71 UINT16 tFAW; ///< Offset 10 Number of tCK cycles for the channel DIMM's minimum four activate window delay time. 72 UINT16 tRAS; ///< Offset 12 Number of tCK cycles for the channel DIMM's minimum active to precharge delay time. 73 UINT16 tRCDtRP; ///< Offset 14 Number of tCK cycles for the channel DIMM's minimum RAS# to CAS# delay time and Row Precharge delay time 74 UINT16 tREFI; ///< Offset 16 Number of tCK cycles for the channel DIMM's minimum Average Periodic Refresh Interval. 75 UINT16 tRFC; ///< Offset 18 Number of tCK cycles for the channel DIMM's minimum refresh recovery delay time. 76 UINT16 tRPab; ///< Offset 20 Number of tCK cycles for the channel DIMM's minimum row precharge delay time for all banks. 77 UINT16 tRRD; ///< Offset 22 Number of tCK cycles for the channel DIMM's minimum row active to row active delay time. 78 UINT16 tRTP; ///< Offset 24 Number of tCK cycles for the channel DIMM's minimum internal read to precharge command delay time. 79 UINT16 tWR; ///< Offset 26 Number of tCK cycles for the channel DIMM's minimum write recovery time. 80 UINT16 tWTR; ///< Offset 28 Number of tCK cycles for the channel DIMM's minimum internal write to read command delay time. 81 UINT8 Rsvd[2]; ///< Offset 30 82 } MEMORY_TIMING; 83 84 // @todo use the MemInfoHob data instead of duplicate structure. 85 /// 86 /// Memory information Data Structure 87 /// 88 typedef struct { 89 MEMORY_TIMING Timing[PROFILE_NUM]; ///< Offset 0 Timming information for the DIMM 90 UINT32 memSize; ///< Offset 128 Total physical memory size 91 UINT16 ddrFreq; ///< Offset 132 DDR Current Frequency 92 UINT16 ddrFreqMax; ///< Offset 134 DDR Maximum Frequency 93 UINT16 dimmSize[NODE_NUM * CH_NUM * DIMM_NUM]; ///< Offset 136 Size of each DIMM 94 UINT16 VddVoltage[PROFILE_NUM]; ///< Offset 144 The voltage setting for the DIMM 95 UINT8 DimmStatus[NODE_NUM * CH_NUM * DIMM_NUM]; ///< Offset 152 The enumeration value from MrcDimmSts 96 UINT8 RankInDimm[NODE_NUM * CH_NUM * DIMM_NUM]; ///< Offset 156 Number of ranks in a DIMM 97 UINT8 *DimmsSpdData[NODE_NUM * CH_NUM * DIMM_NUM]; ///< Offset 160 SPD data of each DIMM 98 UINT8 RefClk; ///< Offset 192 Reference Clock 99 UINT8 Ratio; ///< Offset 193 Clock Multiplier 100 BOOLEAN EccSupport; ///< Offset 194 ECC supported or not 101 UINT8 Profile; ///< Offset 195 Currently running memory profile 102 UINT8 XmpProfileEnable; ///< Offset 196 If XMP capable DIMMs are detected, this will indicate which XMP Profiles are common among all DIMMs. 103 UINT8 DdrType; ///< Offset 197 Current DDR type, see DDR_TYPE_xxx defines above 104 UINT8 Reserved[2]; ///< Offset 198 Reserved bytes for future use 105 UINT32 DefaultXmptCK[XMP_PROFILE_NUM]; ///< Offset 200 The Default XMP tCK values read from SPD. 106 } MEMORY_INFO_DATA; 107 #pragma pack() 108 109 /// 110 /// Memory information Protocol definition 111 /// 112 typedef struct { 113 MEMORY_INFO_DATA MemInfoData; ///< Memory Information Data Structure 114 } MEM_INFO_PROTOCOL; 115 116 #endif 117