1 /** @file 2 The GUID definition for PchConfigHob 3 4 Copyright (c) 2021, Intel Corporation. All rights reserved.<BR> 5 SPDX-License-Identifier: BSD-2-Clause-Patent 6 **/ 7 #ifndef _PCH_CONFIG_HOB_H_ 8 #define _PCH_CONFIG_HOB_H_ 9 10 #include <ConfigBlock.h> 11 #include <SmbusConfig.h> 12 #include <InterruptConfig.h> 13 #include <PchPcieRpConfig.h> 14 #include <SataConfig.h> 15 #include <RstConfig.h> 16 #include <ConfigBlock/FlashProtectionConfig.h> 17 #include <FivrConfig.h> 18 #include <ThcConfig.h> 19 #include <SerialIoConfig.h> 20 21 22 extern EFI_GUID gPchConfigHobGuid; 23 24 #pragma pack (push,1) 25 26 /** 27 This structure contains the HOB which are related to PCH general config. 28 **/ 29 typedef struct { 30 /** 31 This member describes whether or not the Compatibility Revision ID (CRID) feature 32 of PCH should be enabled. <b>0: Disable</b>; 1: Enable 33 **/ 34 UINT32 Crid : 1; 35 UINT32 RsvdBits0 : 31; ///< Reserved bits 36 } GENERAL_HOB; 37 38 /** 39 The SMBUS_CONFIG block lists the reserved addresses for non-ARP capable devices in the platform. 40 **/ 41 typedef struct { 42 UINT8 RsvdBytes[3]; ///< Reserved bytes 43 UINT8 NumRsvdSmbusAddresses; ///< The number of elements in the RsvdSmbusAddressTable. 44 /** 45 Array of addresses reserved for non-ARP-capable SMBus devices. 46 **/ 47 UINT8 RsvdSmbusAddressTable[PCH_MAX_SMBUS_RESERVED_ADDRESS]; 48 } SMBUS_HOB; 49 50 /** 51 The INTERRUPT_HOB describes interrupt settings for PCH. 52 **/ 53 typedef struct { 54 UINT8 NumOfDevIntConfig; ///< Number of entries in DevIntConfig table 55 UINT8 GpioIrqRoute; ///< Interrupt routing for GPIO. Default is <b>14</b>. 56 UINT8 Rsvd0[2]; ///< Reserved bytes, align to multiple 4. 57 PCH_DEVICE_INTERRUPT_CONFIG DevIntConfig[PCH_MAX_DEVICE_INTERRUPT_CONFIG]; ///< Array which stores PCH devices interrupts settings 58 } INTERRUPT_HOB; 59 60 /** 61 The SERIAL_IO block provides the configurations to set the Serial IO controllers 62 **/ 63 typedef struct { 64 SERIAL_IO_SPI_CONFIG SpiDeviceConfig[PCH_MAX_SERIALIO_SPI_CONTROLLERS]; ///< SPI Configuration 65 SERIAL_IO_I2C_CONFIG I2cDeviceConfig[PCH_MAX_SERIALIO_I2C_CONTROLLERS]; ///< I2C Configuration 66 SERIAL_IO_UART_CONFIG UartDeviceConfig[PCH_MAX_SERIALIO_UART_CONTROLLERS]; ///< UART Configuration 67 } SERIAL_IO_HOB; 68 69 /** 70 The PCIERP_HOB block describes the expected configuration of the PCH PCI Express controllers 71 **/ 72 typedef struct { 73 /// 74 /// These members describe the configuration of each PCH PCIe root port. 75 /// 76 PCH_PCIE_ROOT_PORT_CONFIG RootPort[PCH_MAX_PCIE_ROOT_PORTS]; 77 PCH_PCIE_CLOCK PcieClock[PCH_MAX_PCIE_CLOCKS]; 78 /** 79 This member allows BIOS to control ICC PLL Shutdown by determining PCIe devices are LTR capable 80 or leaving untouched. 81 - <b>0: Disable, ICC PLL Shutdown is determined by PCIe device LTR capablility.</b> 82 - To allow ICC PLL shutdown if all present PCIe devices are LTR capable or if no PCIe devices are 83 presented for maximum power savings where possible. 84 - To disable ICC PLL shutdown when BIOS detects any non-LTR capable PCIe device for ensuring device 85 functionality. 86 - 1: Enable, To allow ICC PLL shutdown even if some devices do not support LTR capability. 87 **/ 88 UINT32 AllowNoLtrIccPllShutdown : 1; 89 UINT32 RsvdBits0 : 31; ///< Reserved bits 90 } PCIERP_HOB; 91 92 /** 93 The HDAUDIO_HOB block describes the configuration of the PCH cAVS controller 94 **/ 95 typedef struct { 96 UINT32 DspEnable : 1; ///< DSP enablement: 0: Disable; <b>1: Enable</b> 97 UINT32 DspUaaCompliance : 1; ///< UAA-mode Select: <b>0: Non-Uaa</b>; 1: UAA 98 UINT32 CodecSxWakeCapability : 1; ///< Capability to detect wake initiated by a codec in Sx, <b>0: Disable</b>; 1: Enable 99 UINT32 AudioLinkSndw1 : 1; ///< SoundWire1 link enablement: <b>0: Disable</b>; 1: Enable. Muxed with HDA 100 UINT32 AudioLinkSndw2 : 1; ///< SoundWire2 link enablement: <b>0: Disable</b>; 1: Enable. Muxed with SSP1 101 UINT32 AudioLinkSndw3 : 1; ///< SoundWire3 link enablement: <b>0: Disable</b>; 1: Enable. Muxed with DMIC1 102 UINT32 AudioLinkSndw4 : 1; ///< SoundWire4 link enablement: <b>0: Disable</b>; 1: Enable. Muxed with DMIC0 103 UINT32 Pme : 1; ///< Azalia wake-on-ring, <b>0: Disable</b>; 1: Enable 104 UINT32 RsvdBits0 : 24; ///< Reserved bits 105 } HDAUDIO_HOB; 106 107 /** 108 The SATA_HOB block describes the configuration of the PCH SATA controllers 109 **/ 110 typedef struct { 111 /** 112 This member describes whether or not the SATA controllers should be enabled. 0: Disable; <b>1: Enable</b>. 113 **/ 114 UINT32 Enable : 1; 115 UINT32 TestMode : 1; ///< <b>(Test)</b> <b>0: Disable</b>; 1: Allow entrance to the PCH SATA test modes 116 UINT32 RsvdBits0 : 30; ///< Reserved bits 117 /** 118 This member configures the features, property, and capability for each SATA port. 119 **/ 120 PCH_SATA_PORT_CONFIG PortSettings[PCH_MAX_SATA_PORTS]; 121 } SATA_HOB; 122 123 /** 124 The RST block describes the configuration of the RST PCIE Cycle Routers 125 **/ 126 typedef struct { 127 /** 128 This member describes the details of implementation of Intel RST for PCIe Storage remapping (Intel RST Driver is required) 129 **/ 130 RST_HARDWARE_REMAPPED_STORAGE_CONFIG RstHardwareRemappedStorageConfig[PCH_MAX_RST_PCIE_STORAGE_CR]; 131 } RST_HOB; 132 133 typedef struct { 134 UINT32 Enabled : 1; ///< Indicates that SD card has been enabled 135 UINT32 Reserved : 31; 136 } SD_CARD_HOB; 137 138 /** 139 The EMMC_HOB block describes integrated eMMC settings for PCH. 140 **/ 141 typedef struct { 142 UINT32 Enabled : 1; ///< Determine if eMMC is enabled - 0: Disabled, <b>1: Enabled</b>. 143 UINT32 Hs400Enabled : 1; ///< Determine eMMC HS400 Mode if EmmcEnabled - <b>0: Disabled</b>, 1: Enabled 144 /** 145 Determine if HS400 Training is required, set to FALSE if Hs400 Data is valid. <b>0: Disabled</b>, 1: Enabled. 146 First Boot or CMOS clear, system boot with Default settings, set tuning required. 147 Subsequent Boots, Get Variable 'Hs400TuningData' 148 - if failed to get variable, set tuning required 149 - if passed, retrieve Hs400DataValid, Hs400RxStrobe1Dll and Hs400TxDataDll from variable. Set tuning not required. 150 **/ 151 UINT32 Hs400DllDataValid : 1; ///< Set if HS400 Tuning Data Valid 152 UINT32 RsvdBits : 29; 153 } EMMC_HOB; 154 155 /** 156 The PCH_LOCK_DOWN_CONFIG block describes the expected configuration of the PCH 157 for security requirement. 158 **/ 159 typedef struct { 160 UINT32 GlobalSmi : 1; 161 /** 162 <b>(Test)</b> Enable BIOS Interface Lock Down bit to prevent writes to the Backup Control Register 163 Top Swap bit and the General Control and Status Registers Boot BIOS Straps. 0: Disable; <b>1: Enable</b>. 164 **/ 165 UINT32 BiosInterface : 1; 166 /** 167 Enable the BIOS Lock Enable (BLE) feature and set EISS bit (D31:F5:RegDCh[5]) 168 for the BIOS region protection. When it is enabled, the BIOS Region can only be 169 modified from SMM after EndOfDxe protocol is installed. 170 Note: When BiosLock is enabled, platform code also needs to update to take care 171 of BIOS modification (including SetVariable) in DXE or runtime phase after 172 EndOfDxe protocol is installed. 173 Enable InSMM.STS (EISS) in SPI 174 If this EISS bit is set, then WPD must be a '1' and InSMM.STS must be '1' also 175 in order to write to BIOS regions of SPI Flash. If this EISS bit is clear, 176 then the InSMM.STS is a don't care. 177 The BIOS must set the EISS bit while BIOS Guard support is enabled. 178 In recovery path, platform can temporary disable EISS for SPI programming in 179 PEI phase or early DXE phase. 180 0: Disable; <b>1: Enable.</b> 181 **/ 182 UINT32 BiosLock : 1; 183 UINT32 RsvdBits : 29; 184 } LOCK_DOWN_HOB; 185 186 /** 187 The PM_HOB block describes expected miscellaneous power management settings. 188 The PowerResetStatusClear field would clear the Power/Reset status bits, please 189 set the bits if you want PCH Init driver to clear it, if you want to check the 190 status later then clear the bits. 191 **/ 192 typedef struct { 193 UINT32 PsOnEnable : 1; ///< Indicates if PS_ON support has been enabled, <b>0: Disable</b>; 1: Enable. 194 UINT32 EnableTimedGpio0 : 1; ///< Enable Bit for Timed GPIO 0 <b>0 = disable</b>; 1 = enable 195 UINT32 EnableTimedGpio1 : 1; ///< Enable Bit for Timed GPIO 1 <b>0 = disable</b>; 1 = enable 196 UINT32 RsvdBits1 : 29; 197 } PM_HOB; 198 199 /** 200 FIVR_HOB block 201 **/ 202 typedef struct { 203 /** 204 Additional External Vnn VR rail configuration dedicated for Sx. 205 Required only if External Vnn VR needs different settings for Sx than 206 those specified in ExtVnnRail (refer to PCH_FIVR_CONFIG.ExtVnnRail) 207 **/ 208 FIVR_EXT_RAIL_CONFIG ExtVnnRailSx; 209 } FIVR_HOB; 210 211 /** 212 PCH Trace Hub HOB settings. 213 **/ 214 typedef struct { 215 UINT32 PchTraceHubMode : 2; ///< <b>0 = Disable</b>; 1 = Target Debugger mode; 2 = Host Debugger mode 216 UINT32 Rsvd1 : 30; ///< Reserved bits 217 /** 218 Trace hub memory buffer region size policy. 219 The avaliable memory size options are: 0:0MB (none), 1:1MB, <b>2:8MB</b>, 3:64MB, 4:128MB, 5:256MB, 6:512MB. 220 Note : Limitation of total buffer size (CPU + PCH) is 512MB. If iTbt is enabled, the total size limits to 256 MB. 221 Refer to TRACE_BUFFER_SIZE 222 **/ 223 UINT32 MemReg0Size; 224 UINT32 MemReg1Size; 225 } PCH_TRACEHUB_HOB; 226 227 /** 228 PCH eSPI HOB settings. 229 **/ 230 typedef struct { 231 UINT32 BmeMasterSlaveEnabled : 1; ///< <b>0 = BME disable</b>; 1 = BME enable 232 UINT32 RsvdBits : 31; ///< Reserved bits 233 } PCH_ESPI_HOB; 234 235 /** 236 THC HOB settings. 237 **/ 238 typedef struct { 239 THC_PORT ThcPort[2]; ///< Port Configuration 240 } THC_HOB; 241 242 243 /** 244 This structure contains the HOBs which are related to PCH controllers 245 **/ 246 typedef struct { 247 EFI_HOB_GUID_TYPE EfiHobGuidType; ///< GUID HOB type structure for gPchConfigHobGuid 248 GENERAL_HOB General; ///< Pch general HOB definition 249 INTERRUPT_HOB Interrupt; ///< Interrupt HOB definition 250 SERIAL_IO_HOB SerialIo; ///< Serial io HOB definition 251 PCIERP_HOB PcieRp; ///< PCIE root port HOB definition 252 SD_CARD_HOB SdCard; ///< SD card HOB definition 253 EMMC_HOB Emmc; ///< eMMC HOB definition 254 LOCK_DOWN_HOB LockDown; ///< Lock down HOB definition 255 PM_HOB Pm; ///< PM HOB definition 256 HDAUDIO_HOB HdAudio; ///< HD audio definition 257 SATA_HOB Sata[PCH_MAX_SATA_CONTROLLERS]; ///< SATA definition 258 RST_HOB Rst; ///< RST definition 259 PROTECTED_RANGE ProtectRange[PCH_FLASH_PROTECTED_RANGES]; 260 SMBUS_HOB Smbus; 261 PCH_TRACEHUB_HOB PchTraceHub; ///< PCH Trace Hub definition 262 PCH_ESPI_HOB Espi; ///< PCH eSPI definition 263 THC_HOB Thc; ///< PCH Tocuh Host Controller definition 264 FIVR_HOB Fivr; ///< PCH FIVR HOB definition 265 266 267 } PCH_CONFIG_HOB; 268 #pragma pack (pop) 269 #endif 270