1 /* Copyright (C) 2015 Intel Corporation
2 Decode Intel Broadwell D specific machine check errors.
3
4 mcelog is free software; you can redistribute it and/or
5 modify it under the terms of the GNU General Public
6 License as published by the Free Software Foundation; version
7 2.
8
9 mcelog is distributed in the hope that it will be useful,
10 but WITHOUT ANY WARRANTY; without even the implied warranty of
11 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
12 General Public License for more details.
13
14 You should find a copy of v2 of the GNU General Public License somewhere
15 on your Linux system; if not, write to the Free Software Foundation,
16 Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
17
18 Author: Tony Luck
19 */
20
21 #include "mcelog.h"
22 #include "bitfield.h"
23 #include "broadwell_de.h"
24 #include "memdb.h"
25
26 /* See IA32 SDM Vol3B Table 16-24 */
27
28 static char *pcu_1[] = {
29 [0x00] = "No Error",
30 [0x09] = "MC_MESSAGE_CHANNEL_TIMEOUT",
31 [0x13] = "MC_DMI_TRAINING_TIMEOUT",
32 [0x15] = "MC_DMI_CPU_RESET_ACK_TIMEOUT",
33 [0x1E] = "MC_VR_ICC_MAX_LT_FUSED_ICC_MAX",
34 [0x25] = "MC_SVID_COMMAN_TIMEOUT",
35 [0x26] = "MCA_PKGC_DIRECT_WAKE_RING_TIMEOUT",
36 [0x29] = "MC_VR_VOUT_MAC_LT_FUSED_SVID",
37 [0x2B] = "MC_PKGC_WATCHDOG_HANG_CBZ_DOWN",
38 [0x2C] = "MC_PKGC_WATCHDOG_HANG_CBZ_UP",
39 [0x44] = "MC_CRITICAL_VR_FAILED",
40 [0x46] = "MC_VID_RAMP_DOWN_FAILED",
41 [0x49] = "MC_SVID_WRITE_REG_VOUT_MAX_FAILED",
42 [0x4B] = "MC_BOOT_VID_TIMEOUT_DRAM_0",
43 [0x4F] = "MC_SVID_COMMAND_ERROR",
44 [0x52] = "MC_FIVR_CATAS_OVERVOL_FAULT",
45 [0x53] = "MC_FIVR_CATAS_OVERCUR_FAULT",
46 [0x57] = "MC_SVID_PKGC_REQUEST_FAILED",
47 [0x58] = "MC_SVID_IMON_REQUEST_FAILED",
48 [0x59] = "MC_SVID_ALERT_REQUEST_FAILED",
49 [0x62] = "MC_INVALID_PKGS_RSP_QPI",
50 [0x64] = "MC_INVALID_PKG_STATE_CONFIG",
51 [0x67] = "MC_HA_IMC_RW_BLOCK_ACK_TIMEOUT",
52 [0x6A] = "MC_MSGCH_PMREQ_CMP_TIMEOUT",
53 [0x72] = "MC_WATCHDOG_TIMEOUT_PKGS_MAIN",
54 [0x81] = "MC_RECOVERABLE_DIE_THERMAL_TOO_HOT"
55 };
56
57 static struct field pcu_mc4[] = {
58 FIELD(24, pcu_1),
59 {}
60 };
61
62 /* See IA32 SDM Vol3B Table 16-18 */
63
64 static struct field memctrl_mc9[] = {
65 SBITFIELD(16, "Address parity error"),
66 SBITFIELD(17, "HA Wrt buffer Data parity error"),
67 SBITFIELD(18, "HA Wrt byte enable parity error"),
68 SBITFIELD(19, "Corrected patrol scrub error"),
69 SBITFIELD(20, "Uncorrected patrol scrub error"),
70 SBITFIELD(21, "Corrected spare error"),
71 SBITFIELD(22, "Uncorrected spare error"),
72 SBITFIELD(23, "Corrected memory read error"),
73 SBITFIELD(24, "iMC, WDB, parity errors"),
74 {}
75 };
76
bdw_de_decode_model(int cputype,int bank,u64 status,u64 misc)77 void bdw_de_decode_model(int cputype, int bank, u64 status, u64 misc)
78 {
79 switch (bank) {
80 case 4:
81 Wprintf("PCU: ");
82 switch (EXTRACT(status, 0, 15) & ~(1ull << 12)) {
83 case 0x402: case 0x403:
84 Wprintf("Internal errors ");
85 break;
86 case 0x406:
87 Wprintf("Intel TXT errors ");
88 break;
89 case 0x407:
90 Wprintf("Other UBOX Internal errors ");
91 break;
92 }
93 if (EXTRACT(status, 16, 19) & 3)
94 Wprintf("PCU internal error ");
95 if (EXTRACT(status, 20, 23) & 4)
96 Wprintf("Ubox error ");
97 decode_bitfield(status, pcu_mc4);
98 break;
99 case 9: case 10:
100 Wprintf("MemCtrl: ");
101 decode_bitfield(status, memctrl_mc9);
102 break;
103 }
104 }
105