1 /* 2 * SPDX-License-Identifier: BSD-2-Clause 3 * 4 * Copyright (c) 2019 Andes Technology Corporation 5 * 6 * Authors: 7 * Zong Li <zong@andestech.com> 8 * Nylon Chen <nylon7@andestech.com> 9 */ 10 11 #ifndef _AE350_PLATFORM_H_ 12 #define _AE350_PLATFORM_H_ 13 14 #define AE350_HART_COUNT 4 15 16 #define AE350_PLIC_ADDR 0xe4000000 17 #define AE350_PLIC_NUM_SOURCES 71 18 19 #define AE350_PLICSW_ADDR 0xe6400000 20 21 #define AE350_PLMT_ADDR 0xe6000000 22 23 #define AE350_L2C_ADDR 0xe0500000 24 25 #define AE350_UART_ADDR_OFFSET 0x20 26 #define AE350_UART_ADDR (0xf0300000 + AE350_UART_ADDR_OFFSET) 27 #define AE350_UART_FREQUENCY 19660800 28 #define AE350_UART_BAUDRATE 38400 29 #define AE350_UART_REG_SHIFT 2 30 #define AE350_UART_REG_WIDTH 0 31 32 /*Memory and Miscellaneous Registers*/ 33 #define CSR_MILMB 0x7c0 34 #define CSR_MDLMB 0x7c1 35 #define CSR_MECC_CDOE 0x7c2 36 #define CSR_MNVEC 0x7c3 37 #define CSR_MPFTCTL 0x7c5 38 #define CSR_MCACHECTL 0x7ca 39 #define CSR_MCCTLBEGINADDR 0x7cb 40 #define CSR_MCCTLCOMMAND 0x7cc 41 #define CSR_MCCTLDATA 0x7cc 42 #define CSR_SCCTLDATA 0x9cd 43 #define CSR_UCCTLBEGINADDR 0x80c 44 #define CSR_MMISCCTL 0x7d0 45 46 enum sbi_ext_andes_fid { 47 SBI_EXT_ANDES_GET_MCACHE_CTL_STATUS = 0, 48 SBI_EXT_ANDES_GET_MMISC_CTL_STATUS, 49 SBI_EXT_ANDES_SET_MCACHE_CTL, 50 SBI_EXT_ANDES_SET_MMISC_CTL, 51 SBI_EXT_ANDES_ICACHE_OP, 52 SBI_EXT_ANDES_DCACHE_OP, 53 SBI_EXT_ANDES_L1CACHE_I_PREFETCH, 54 SBI_EXT_ANDES_L1CACHE_D_PREFETCH, 55 SBI_EXT_ANDES_NON_BLOCKING_LOAD_STORE, 56 SBI_EXT_ANDES_WRITE_AROUND, 57 }; 58 59 /* nds v5 mmisc_ctl register*/ 60 #define V5_MMISC_CTL_VEC_PLIC_OFFSET 1 61 #define V5_MMISC_CTL_RVCOMPM_OFFSET 2 62 #define V5_MMISC_CTL_BRPE_OFFSET 3 63 #define V5_MMISC_CTL_MSA_OR_UNA_OFFSET 6 64 #define V5_MMISC_CTL_NON_BLOCKING_OFFSET 8 65 #define V5_MCACHE_CTL_L1I_PREFETCH_OFFSET 9 66 #define V5_MCACHE_CTL_L1D_PREFETCH_OFFSET 10 67 #define V5_MCACHE_CTL_DC_WAROUND_OFFSET_1 13 68 #define V5_MCACHE_CTL_DC_WAROUND_OFFSET_2 14 69 70 #define V5_MMISC_CTL_VEC_PLIC_EN (1UL << V5_MMISC_CTL_VEC_PLIC_OFFSET) 71 #define V5_MMISC_CTL_RVCOMPM_EN (1UL << V5_MMISC_CTL_RVCOMPM_OFFSET) 72 #define V5_MMISC_CTL_BRPE_EN (1UL << V5_MMISC_CTL_BRPE_OFFSET) 73 #define V5_MMISC_CTL_MSA_OR_UNA_EN (1UL << V5_MMISC_CTL_MSA_OR_UNA_OFFSET) 74 #define V5_MMISC_CTL_NON_BLOCKING_EN (1UL << V5_MMISC_CTL_NON_BLOCKING_OFFSET) 75 #define V5_MCACHE_CTL_L1I_PREFETCH_EN (1UL << V5_MCACHE_CTL_L1I_PREFETCH_OFFSET) 76 #define V5_MCACHE_CTL_L1D_PREFETCH_EN (1UL << V5_MCACHE_CTL_L1D_PREFETCH_OFFSET) 77 #define V5_MCACHE_CTL_DC_WAROUND_1_EN (1UL << V5_MCACHE_CTL_DC_WAROUND_OFFSET_1) 78 #define V5_MCACHE_CTL_DC_WAROUND_2_EN (1UL << V5_MCACHE_CTL_DC_WAROUND_OFFSET_2) 79 80 #define V5_MMISC_CTL_MASK (V5_MMISC_CTL_VEC_PLIC_EN | V5_MMISC_CTL_RVCOMPM_EN \ 81 | V5_MMISC_CTL_BRPE_EN | V5_MMISC_CTL_MSA_OR_UNA_EN | V5_MMISC_CTL_NON_BLOCKING_EN) 82 83 /* nds mcache_ctl register*/ 84 #define V5_MCACHE_CTL_IC_EN_OFFSET 0 85 #define V5_MCACHE_CTL_DC_EN_OFFSET 1 86 #define V5_MCACHE_CTL_IC_ECCEN_OFFSET 2 87 #define V5_MCACHE_CTL_DC_ECCEN_OFFSET 4 88 #define V5_MCACHE_CTL_IC_RWECC_OFFSET 6 89 #define V5_MCACHE_CTL_DC_RWECC_OFFSET 7 90 #define V5_MCACHE_CTL_CCTL_SUEN_OFFSET 8 91 92 /*nds cctl command*/ 93 #define V5_UCCTL_L1D_WBINVAL_ALL 6 94 #define V5_UCCTL_L1D_WB_ALL 7 95 96 #define V5_MCACHE_CTL_IC_EN (1UL << V5_MCACHE_CTL_IC_EN_OFFSET) 97 #define V5_MCACHE_CTL_DC_EN (1UL << V5_MCACHE_CTL_DC_EN_OFFSET) 98 #define V5_MCACHE_CTL_IC_RWECC (1UL << V5_MCACHE_CTL_IC_RWECC_OFFSET) 99 #define V5_MCACHE_CTL_DC_RWECC (1UL << V5_MCACHE_CTL_DC_RWECC_OFFSET) 100 #define V5_MCACHE_CTL_CCTL_SUEN (1UL << V5_MCACHE_CTL_CCTL_SUEN_OFFSET) 101 102 #define V5_MCACHE_CTL_MASK (V5_MCACHE_CTL_IC_EN | V5_MCACHE_CTL_DC_EN \ 103 | V5_MCACHE_CTL_IC_RWECC | V5_MCACHE_CTL_DC_RWECC \ 104 | V5_MCACHE_CTL_CCTL_SUEN | V5_MCACHE_CTL_L1I_PREFETCH_EN \ 105 | V5_MCACHE_CTL_L1D_PREFETCH_EN | V5_MCACHE_CTL_DC_WAROUND_1_EN \ 106 | V5_MCACHE_CTL_DC_WAROUND_2_EN) 107 108 #define V5_L2C_CTL_OFFSET 0x8 109 #define V5_L2C_CTL_ENABLE_OFFSET 0 110 #define V5_L2C_CTL_IPFDPT_OFFSET 3 111 #define V5_L2C_CTL_DPFDPT_OFFSET 5 112 #define V5_L2C_CTL_TRAMOCTL_OFFSET 8 113 #define V5_L2C_CTL_TRAMICTL_OFFSET 10 114 #define V5_L2C_CTL_DRAMOCTL_OFFSET 11 115 #define V5_L2C_CTL_DRAMICTL_OFFSET 13 116 117 #define V5_L2C_CTL_ENABLE_MASK (1UL << V5_L2C_CTL_ENABLE_OFFSET) 118 #define V5_L2C_CTL_IPFDPT_MASK (3UL << V5_L2C_CTL_IPFDPT_OFFSET) 119 #define V5_L2C_CTL_DPFDPT_MASK (3UL << V5_L2C_CTL_DPFDPT_OFFSET) 120 #define V5_L2C_CTL_TRAMOCTL_MASK (3UL << V5_L2C_CTL_TRAMOCTL_OFFSET) 121 #define V5_L2C_CTL_TRAMICTL_MASK (1UL << V5_L2C_CTL_TRAMICTL_OFFSET) 122 #define V5_L2C_CTL_DRAMOCTL_MASK (3UL << V5_L2C_CTL_DRAMOCTL_OFFSET) 123 #define V5_L2C_CTL_DRAMICTL_MASK (1UL << V5_L2C_CTL_DRAMICTL_OFFSET) 124 125 #endif /* _AE350_PLATFORM_H_ */ 126