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README.mdH A D06-Jul-20206.8 KiB192163

cpuid.goH A D06-Jul-202040.5 KiB1,5051,146

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cpuid_arm64.sH A D06-Jul-2020837 2714

cpuid_test.goH A D06-Jul-202024.5 KiB874668

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detect_intel.goH A D06-Jul-2020926 3426

detect_ref.goH A D06-Jul-2020448 158

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mockcpu_test.goH A D06-Jul-20205.2 KiB213190

private-gen.goH A D06-Jul-202012.4 KiB486369

README.md

1# cpuid
2Package cpuid provides information about the CPU running the current program.
3
4CPU features are detected on startup, and kept for fast access through the life of the application.
5Currently x86 / x64 (AMD64/i386) and ARM (ARM64) is supported, and no external C (cgo) code is used, which should make the library very easy to use.
6
7You can access the CPU information by accessing the shared CPU variable of the cpuid library.
8
9Package home: https://github.com/klauspost/cpuid
10
11[![GoDoc][1]][2] [![Build Status][3]][4]
12
13[1]: https://godoc.org/github.com/klauspost/cpuid?status.svg
14[2]: https://godoc.org/github.com/klauspost/cpuid
15[3]: https://travis-ci.org/klauspost/cpuid.svg?branch=master
16[4]: https://travis-ci.org/klauspost/cpuid
17
18# features
19
20## x86 CPU Instructions
21*  **CMOV** (i686 CMOV)
22*  **NX** (NX (No-Execute) bit)
23*  **AMD3DNOW** (AMD 3DNOW)
24*  **AMD3DNOWEXT** (AMD 3DNowExt)
25*  **MMX** (standard MMX)
26*  **MMXEXT** (SSE integer functions or AMD MMX ext)
27*  **SSE** (SSE functions)
28*  **SSE2** (P4 SSE functions)
29*  **SSE3** (Prescott SSE3 functions)
30*  **SSSE3** (Conroe SSSE3 functions)
31*  **SSE4** (Penryn SSE4.1 functions)
32*  **SSE4A** (AMD Barcelona microarchitecture SSE4a instructions)
33*  **SSE42** (Nehalem SSE4.2 functions)
34*  **AVX** (AVX functions)
35*  **AVX2** (AVX2 functions)
36*  **FMA3** (Intel FMA 3)
37*  **FMA4** (Bulldozer FMA4 functions)
38*  **XOP** (Bulldozer XOP functions)
39*  **F16C** (Half-precision floating-point conversion)
40*  **BMI1** (Bit Manipulation Instruction Set 1)
41*  **BMI2** (Bit Manipulation Instruction Set 2)
42*  **TBM** (AMD Trailing Bit Manipulation)
43*  **LZCNT** (LZCNT instruction)
44*  **POPCNT** (POPCNT instruction)
45*  **AESNI** (Advanced Encryption Standard New Instructions)
46*  **CLMUL** (Carry-less Multiplication)
47*  **HTT** (Hyperthreading (enabled))
48*  **HLE** (Hardware Lock Elision)
49*  **RTM** (Restricted Transactional Memory)
50*  **RDRAND** (RDRAND instruction is available)
51*  **RDSEED** (RDSEED instruction is available)
52*  **ADX** (Intel ADX (Multi-Precision Add-Carry Instruction Extensions))
53*  **SHA** (Intel SHA Extensions)
54*  **AVX512F** (AVX-512 Foundation)
55*  **AVX512DQ** (AVX-512 Doubleword and Quadword Instructions)
56*  **AVX512IFMA** (AVX-512 Integer Fused Multiply-Add Instructions)
57*  **AVX512PF** (AVX-512 Prefetch Instructions)
58*  **AVX512ER** (AVX-512 Exponential and Reciprocal Instructions)
59*  **AVX512CD** (AVX-512 Conflict Detection Instructions)
60*  **AVX512BW** (AVX-512 Byte and Word Instructions)
61*  **AVX512VL** (AVX-512 Vector Length Extensions)
62*  **AVX512VBMI** (AVX-512 Vector Bit Manipulation Instructions)
63*  **AVX512VBMI2** (AVX-512 Vector Bit Manipulation Instructions, Version 2)
64*  **AVX512VNNI** (AVX-512 Vector Neural Network Instructions)
65*  **AVX512VPOPCNTDQ** (AVX-512 Vector Population Count Doubleword and Quadword)
66*  **GFNI** (Galois Field New Instructions)
67*  **VAES** (Vector AES)
68*  **AVX512BITALG** (AVX-512 Bit Algorithms)
69*  **VPCLMULQDQ** (Carry-Less Multiplication Quadword)
70*  **AVX512BF16** (AVX-512 BFLOAT16 Instructions)
71*  **AVX512VP2INTERSECT** (AVX-512 Intersect for D/Q)
72*  **MPX** (Intel MPX (Memory Protection Extensions))
73*  **ERMS** (Enhanced REP MOVSB/STOSB)
74*  **RDTSCP** (RDTSCP Instruction)
75*  **CX16** (CMPXCHG16B Instruction)
76*  **SGX** (Software Guard Extensions, with activation details)
77*  **VMX** (Virtual Machine Extensions)
78
79## Performance
80*  **RDTSCP()** Returns current cycle count. Can be used for benchmarking.
81*  **SSE2SLOW** (SSE2 is supported, but usually not faster)
82*  **SSE3SLOW** (SSE3 is supported, but usually not faster)
83*  **ATOM** (Atom processor, some SSSE3 instructions are slower)
84*  **Cache line** (Probable size of a cache line).
85*  **L1, L2, L3 Cache size** on newer Intel/AMD CPUs.
86
87## ARM CPU features
88
89# ARM FEATURE DETECTION DISABLED!
90
91See [#52](https://github.com/klauspost/cpuid/issues/52).
92
93Currently only `arm64` platforms are implemented.
94
95*  **FP**  Single-precision and double-precision floating point
96*  **ASIMD**  Advanced SIMD
97*  **EVTSTRM**  Generic timer
98*  **AES**  AES instructions
99*  **PMULL**  Polynomial Multiply instructions (PMULL/PMULL2)
100*  **SHA1**  SHA-1 instructions (SHA1C, etc)
101*  **SHA2**      SHA-2 instructions (SHA256H, etc)
102*  **CRC32**   CRC32/CRC32C instructions
103*  **ATOMICS**   Large System Extensions (LSE)
104*  **FPHP** Half-precision floating point
105*  **ASIMDHP**  Advanced SIMD half-precision floating point
106*  **ARMCPUID**  Some CPU ID registers readable at user-level
107*  **ASIMDRDM**  Rounding Double Multiply Accumulate/Subtract (SQRDMLAH/SQRDMLSH)
108*  **JSCVT** Javascript-style double->int convert (FJCVTZS)
109*  **FCMA**  Floating point complex number addition and multiplication
110*  **LRCPC**  Weaker release consistency (LDAPR, etc)
111*  **DCPOP**  Data cache clean to Point of Persistence (DC CVAP)
112*  **SHA3**  SHA-3 instructions (EOR3, RAXI, XAR, BCAX)
113*  **SM3** SM3 instructions
114*  **SM4**  SM4 instructions
115*  **ASIMDDP**  SIMD Dot Product
116*  **SHA512**  SHA512 instructions
117*  **SVE** Scalable Vector Extension
118*  **GPA**  Generic Pointer Authentication
119
120## Cpu Vendor/VM
121* **Intel**
122* **AMD**
123* **VIA**
124* **Transmeta**
125* **NSC**
126* **KVM**  (Kernel-based Virtual Machine)
127* **MSVM** (Microsoft Hyper-V or Windows Virtual PC)
128* **VMware**
129* **XenHVM**
130* **Bhyve**
131* **Hygon**
132
133# installing
134
135```go get github.com/klauspost/cpuid```
136
137# example
138
139```Go
140package main
141
142import (
143	"fmt"
144	"github.com/klauspost/cpuid"
145)
146
147func main() {
148	// Print basic CPU information:
149	fmt.Println("Name:", cpuid.CPU.BrandName)
150	fmt.Println("PhysicalCores:", cpuid.CPU.PhysicalCores)
151	fmt.Println("ThreadsPerCore:", cpuid.CPU.ThreadsPerCore)
152	fmt.Println("LogicalCores:", cpuid.CPU.LogicalCores)
153	fmt.Println("Family", cpuid.CPU.Family, "Model:", cpuid.CPU.Model)
154	fmt.Println("Features:", cpuid.CPU.Features)
155	fmt.Println("Cacheline bytes:", cpuid.CPU.CacheLine)
156	fmt.Println("L1 Data Cache:", cpuid.CPU.Cache.L1D, "bytes")
157	fmt.Println("L1 Instruction Cache:", cpuid.CPU.Cache.L1D, "bytes")
158	fmt.Println("L2 Cache:", cpuid.CPU.Cache.L2, "bytes")
159	fmt.Println("L3 Cache:", cpuid.CPU.Cache.L3, "bytes")
160
161	// Test if we have a specific feature:
162	if cpuid.CPU.SSE() {
163		fmt.Println("We have Streaming SIMD Extensions")
164	}
165}
166```
167
168Sample output:
169```
170>go run main.go
171Name: Intel(R) Core(TM) i5-2540M CPU @ 2.60GHz
172PhysicalCores: 2
173ThreadsPerCore: 2
174LogicalCores: 4
175Family 6 Model: 42
176Features: CMOV,MMX,MMXEXT,SSE,SSE2,SSE3,SSSE3,SSE4.1,SSE4.2,AVX,AESNI,CLMUL
177Cacheline bytes: 64
178We have Streaming SIMD Extensions
179```
180
181# private package
182
183In the "private" folder you can find an autogenerated version of the library you can include in your own packages.
184
185For this purpose all exports are removed, and functions and constants are lowercased.
186
187This is not a recommended way of using the library, but provided for convenience, if it is difficult for you to use external packages.
188
189# license
190
191This code is published under an MIT license. See LICENSE file for more information.
192