1 /*
2 * This file is part of the superiotool project.
3 *
4 * Copyright (C) 2006 coresystems GmbH <info@coresystems.de>
5 * Copyright (C) 2007-2008 Uwe Hermann <uwe@hermann-uwe.de>
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
20 */
21
22 #include "superiotool.h"
23
24 #define DEVICE_ID_BYTE1_REG 0x20
25 #define DEVICE_ID_BYTE2_REG 0x21
26
27 #define VENDOR_ID_BYTE1_REG 0x23
28 #define VENDOR_ID_BYTE2_REG 0x24
29
30 #define FINTEK_VENDOR_ID 0x3419
31
32 static const struct superio_registers reg_table[] = {
33 {0x0106, "F71862FG / F71863FG", { /* Same ID? Datasheet typo? */
34 /* We assume reserved bits are read as 0. */
35 {NOLDN, NULL,
36 {0x20,0x21,0x23,0x24,0x25,0x26,0x27,0x28,0x29,0x2a,
37 0x2b,0x2c,0x2d,EOT},
38 {0x06,0x01,0x19,0x34,0x00,0x00,MISC,0x00,0x00,0x00,
39 0x00,0x00,0x08,EOT}},
40 {0x0, "Floppy",
41 {0x30,0x60,0x61,0x70,0x74,0xf0,0xf2,0xf4,EOT},
42 {0x01,0x03,0xf0,0x06,0x02,0x0e,0x03,0x00,EOT}},
43 {0x1, "COM1",
44 {0x30,0x60,0x61,0x70,0xf0,EOT},
45 {0x01,0x03,0xf8,0x04,0x00,EOT}},
46 {0x2, "COM2",
47 {0x30,0x60,0x61,0x70,0xf0,0xf1,EOT},
48 {0x01,0x02,0xf8,0x03,0x00,0x00,EOT}},
49 {0x3, "Parallel port",
50 {0x30,0x60,0x61,0x70,0x74,0xf0,EOT},
51 {0x01,0x03,0x78,0x07,0x03,0x42,EOT}},
52 {0x4, "Hardware monitor",
53 {0x30,0x60,0x61,0x70,EOT},
54 {0x01,0x02,0x95,0x00,EOT}},
55 {0x5, "Keyboard",
56 {0x30,0x60,0x61,0x70,0x72,EOT},
57 {0x01,0x00,0x60,0x00,0x00,EOT}},
58 {0x6, "GPIO",
59 {0xf0,0xf1,0xf2,0xf3,0xe0,0xe1,0xe2,0xe3,0xd0,0xd1,
60 0xd2,0xd3,0xc0,0xc1,0xc2,0xc3,0xb0,0xb1,0xb2,0xb3,
61 EOT},
62 {0x00,0x0f,NANA,0x00,0x00,0xff,NANA,0x00,0x00,0xff,
63 NANA,0x00,0x00,0x0f,NANA,0x00,0x00,0x3f,NANA,0x00,
64 EOT}},
65 {0x7, "VID",
66 {0x30,0x60,0x61, 0xf0,0xf1,0xf2,0xf3,0xf4,0xf5,0xf6,
67 0xf7,EOT},
68 {0x00,0x00,0x00, 0x00,0x00,MISC,0x00,NANA,0x00,0x00,
69 0x00,EOT}},
70 {0x8, "SPI",
71 {0xf0,0xf1,0xf2,0xf3,0xf4,0xf5,0xf6,0xf7,0xf8,0xfa,
72 0xfb,0xfc,0xfd,0xfe,0xff,EOT},
73 {0x10,0x04,0x01,NANA,0x00,0x00,0x00,NANA,0x00,0x00,
74 0x00,0x00,0x00,0x00,0x00,EOT}},
75 {0xa, "PME, ACPI",
76 {0x30,0xf0,0xf1,0xf4,0xf5,0xf7,EOT},
77 {0x00,0x00,NANA,0x06,0x1c,0x01,EOT}},
78 {EOT}}},
79 {0x2307, "F71889", {
80 /* We assume reserved bits are read as 0. */
81 {NOLDN, NULL,
82 {0x20,0x21,0x23,0x24,0x25,0x26,0x27,0x28,0x2a,0x2b,
83 0x2c,0x2d,EOT},
84 {0x07,0x23,0x19,0x34,0x00,0x00,0x00,0x00,0xf0,0x30,
85 0x00,0x08,EOT}},
86 {0x0, "Floppy",
87 {0x30,0x60,0x61,0x70,0x74,0xf0,0xf2,0xf4,EOT},
88 {0x01,0x03,0xf0,0x06,0x02,0x0e,0x03,0x00,EOT}},
89 {0x1, "COM1",
90 {0x30,0x60,0x61,0x70,0xf0,EOT},
91 {0x01,0x03,0xf8,0x04,0x00,EOT}},
92 {0x2, "COM2",
93 {0x30,0x60,0x61,0x70,0xf0,0xf1,EOT},
94 {0x01,0x02,0xf8,0x03,0x00,0x04,EOT}},
95 {0x3, "Parallel port",
96 {0x30,0x60,0x61,0x70,0x74,0xf0,EOT},
97 {0x01,0x03,0x78,0x07,0x03,0x42,EOT}},
98 {0x4, "Hardware monitor",
99 {0x30,0x60,0x61,0x70,EOT},
100 {0x01,0x02,0x95,0x00,EOT}},
101 {0x5, "Keyboard",
102 {0x30,0x60,0x61,0x70,0x72,0xfe,EOT},
103 {0x01,0x00,0x60,0x01,0x0c,0x81,EOT}},
104 {0x6, "GPIO",
105 {0x80,0x81,0x82,0x83,0x90,0x91,0x92,0x93,0xa0,0xa1,
106 0xa2,0xa3,0xb0,0xb1,0xb2,0xc0,0xc1,0xc2,0xc3,0xd0,
107 0xd1,0xd2,0xd3,0xe0,0xe1,0xe2,0xe3,0xf0,0xf1,0xf2,
108 0xf3,0xfe,0xff,EOT},
109 {0x00,0xff,NANA,0x00,0x00,0xff,NANA,0x00,0x00,0x1f,
110 NANA,0x00,0x00,0xff,NANA,0x00,0xff,NANA,0x00,0x00,
111 0xff,NANA,0x00,0x00,0x7f,NANA,0x00,0x00,0x7f,NANA,
112 0x00,0x00,0x00,EOT}},
113 {0x7, "VID",
114 {0x30,0x60,0x61,EOT},
115 {0x00,0x00,0x00,EOT}},
116 {0x8, "SPI",
117 {0xf0,0xf1,0xf2,0xf3,0xf4,0xf5,0xf6,0xf7,0xf8,0xfa,
118 0xfb,0xfc,0xfd,0xfe,0xff,EOT},
119 {0x00,RSVD,0x01,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
120 0x00,0x00,0x00,0x00,0x00,EOT}},
121 {0xa, "PME, ACPI",
122 {0x30,0xf0,0xf1,0xf4,0xf5,0xf6,EOT},
123 {0x00,0x00,0x00,0x26,0x1c,0x07,EOT}},
124 {0xb, "VREF",
125 {0xf0,0xf1,0xf2,0xf3,0xff,EOT},
126 {0x64,0x64,0x64,0x00,0x00,EOT}},
127 {EOT}}},
128 {0x4103, "F71872F/FG / F71806F/FG", { /* Same ID? Datasheet typo? */
129 {NOLDN, NULL,
130 {0x20,0x21,0x22,0x23,0x24,0x25,0x26,0x27,0x28,
131 0x29,0x2a,0x2b,0x2c,0x2d,EOT},
132 {0x03,0x41,RSVD,0x19,0x34,0x00,0x00,MISC,0x66,
133 0x80,0x00,0x00,0x00,0x04,EOT}},
134 {0x0, "Floppy",
135 {0x30,0x60,0x61,0x70,0x74,0xf0,0xf2,0xf4,EOT},
136 {0x01,0x03,0xf0,0x06,0x02,0x0e,0x03,0x00,EOT}},
137 {0x1, "COM1",
138 {0x30,0x60,0x61,0x70,0xf0,EOT},
139 {0x01,0x03,0xf8,0x04,0x00,EOT}},
140 {0x2, "COM2",
141 {0x30,0x60,0x61,0x70,0xf0,0xf1,EOT},
142 {0x01,0x02,0xf8,0x03,0x00,0x04,EOT}},
143 {0x3, "Parallel port",
144 {0x30,0x60,0x61,0x70,0x74,0xf0,EOT},
145 {0x01,0x03,0x78,0x07,0x03,0x42,EOT}},
146 {0x4, "Hardware monitor",
147 {0x30,0x60,0x61,0x70,EOT},
148 {0x00,0x02,0x95,0x00,EOT}},
149 {0x5, "Keyboard", /* Only documented on F71872F/FG. */
150 {0x30,0x60,0x61,0x70,0x72,0xf0,0xf1,EOT},
151 {0x01,0x00,0x60,0x00,0x00,0x83,0x00,EOT}},
152 {0x6, "GPIO",
153 {0x70,0xe0,0xe1,0xe2,0xe3,0xe4,0xe5,0xe6,0xe7,0xe8,
154 0xe9,0xf0,0xf1,0xf2,0xf3,0xf4,0xf5,0xf6,0xf7,0xf8,
155 EOT},
156 {0x00,0x00,0x00,NANA,0x00,0x00,0x00,0x00,0x00,0x00,
157 0x7f,0x00,0x7f,NANA,0x00,0xff,NANA,0x00,0x03,NANA,
158 EOT}},
159 {0x7, "VID",
160 {0x30,0x60,0x61,EOT},
161 {0x00,0x00,0x00,EOT}},
162 {0xa, "PME, ACPI",
163 {0x30,0xf0,0xf1,0xf4,0xf5,EOT},
164 {0x00,0x00,0x61,0x06,0x3c,EOT}},
165 {EOT}}},
166 {0x4105, "F71882FG/F71883FG", { /* Same ID? Datasheet typo? */
167 /* We assume reserved bits are read as 0. */
168 {NOLDN, NULL,
169 {0x20,0x21,0x23,0x24,0x25,0x26,0x27,0x28,0x29,0x2a,
170 0x2b,0x2c,0x2d,EOT},
171 {0x05,0x41,0x19,0x34,0x00,0x00,0x00,0x00,0x00,0x00,
172 0x00,0x08,0x08,EOT}},
173 {0x0, "Floppy",
174 {0x30,0x60,0x61,0x70,0x74,0xf0,0xf2,0xf4,EOT},
175 {0x01,0x03,0xf0,0x06,0x02,0x0e,0x03,0x00,EOT}},
176 {0x1, "COM1",
177 {0x30,0x60,0x61,0x70,0xf0,EOT},
178 {0x01,0x03,0xf8,0x04,0x00,EOT}},
179 {0x2, "COM2",
180 {0x30,0x60,0x61,0x70,0xf0,0xf1,EOT},
181 {0x01,0x02,0xf8,0x03,0x00,0x04,EOT}},
182 {0x3, "Parallel port",
183 {0x30,0x60,0x61,0x70,0x74,0xf0,EOT},
184 {0x01,0x03,0x78,0x07,0x03,0x42,EOT}},
185 {0x4, "Hardware monitor",
186 {0x30,0x60,0x61,0x70,EOT},
187 {0x01,0x02,0x95,0x00,EOT}},
188 {0x5, "Keyboard",
189 {0x30,0x60,0x61,0x70,0x72,0xf0,EOT},
190 {0x01,0x00,0x60,0x00,0x00,0x83,EOT}},
191 {0x6, "GPIO",
192 {0x70,0xe0,0xe1,0xe2,0xe3,0xd0,0xd1,0xd2,0xd3,0xc0,
193 0xc1,0xc2,0xc3,0xb0,0xb1,0xb2,0xb3,0xf0,0xf1,0xf2,
194 0xf3,EOT},
195 {0x00,0x00,0xff,NANA,0x00,0x00,0xff,NANA,0x00,0x00,
196 0x0f,NANA,0x00,0x00,0x0f,NANA,0x00,0x00,0xff,NANA,
197 0x00,EOT}},
198 {0x7, "VID",
199 {0x30,0x60,0x61,EOT},
200 {0x00,0x00,0x00,EOT}},
201 {0x7, "SPI",
202 {0xf0,0xf1,0xf2,0xf3,0xf4,0xf5,0xf6,0xf7,0xf8,0xfa,
203 0xfb,0xfc,0xfd,0xfe,0xff,EOT},
204 {0x10,0x04,0x01,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
205 0x00,0x00,0x00,0x00,0x00,EOT}},
206 {0xa, "PME, ACPI",
207 {0x30,0xf0,0xf1,0xf4,0xf5,EOT},
208 {0x00,0x00,0x01,0x06,0x1c,EOT}},
209 {EOT}}},
210 {0x0604, "F71805F/FG", {
211 /* We assume reserved bits are read as 0. */
212 {NOLDN, NULL,
213 {0x20,0x21,0x23,0x24,0x25,0x26,0x27,0x28,0x29,EOT},
214 {0x04,0x06,0x19,0x34,0x00,0x00,0x3f,0x08,0x00,EOT}},
215 {0x0, "Floppy",
216 {0x30,0x60,0x61,0x70,0x74,0xf0,0xf2,0xf4,EOT},
217 {0x01,0x03,0xf0,0x06,0x02,0x0e,0x03,0x00,EOT}},
218 {0x1, "COM1",
219 {0x30,0x60,0x61,0x70,0xf0,EOT},
220 {0x01,0x03,0xf8,0x04,0x00,EOT}},
221 {0x2, "COM2",
222 {0x30,0x60,0x61,0x70,0xf0,0xf1,EOT},
223 {0x01,0x02,0xf8,0x03,0x00,0x04,EOT}},
224 {0x3, "Parallel port",
225 {0x30,0x60,0x61,0x70,0x74,0xf0,EOT},
226 {0x01,0x03,0x78,0x07,0x03,0x42,EOT}},
227 {0x4, "Hardware monitor",
228 {0x30,0x60,0x61,0x70,EOT},
229 {0x00,0x02,0x95,0x00,EOT}},
230 {0x6, "GPIO",
231 {0x70,0xe0,0xe1,0xe2,0xe3,0xe4,0xe5,0xe6,0xe7,0xe8,
232 0xe9,0xf0,0xf1,0xf3,0xf4,EOT},
233 {0x00,0x00,0x00,NANA,0x00,0x00,0x00,0x00,0x00,0x00,
234 0x00,0x00,NANA,0x00,NANA,EOT}},
235 {0xa, "PME",
236 {0x30,0xf0,0xf1,EOT},
237 {0x00,0x00,0x00,EOT}},
238 {EOT}}},
239 {0x0581, "F8000", { /* Fintek/ASUS F8000 */
240 {EOT}}},
241 {0x0802, "F81216D/DG", {
242 {NOLDN, NULL,
243 {0x25,0x2f,EOT},
244 {0x00,RSVD,EOT}},
245 {0x0, "UART1",
246 {0x30,0x60,0x61,0x70,0xf0,0xf1,EOT},
247 {NANA,NANA,NANA,NANA,0x00,0x40,EOT}},
248 {0x1, "UART2",
249 {0x30,0x60,0x61,0x70,0xf0,EOT},
250 {NANA,NANA,NANA,NANA,0x00,EOT}},
251 {0x2, "UART3",
252 {0x30,0x60,0x61,0x70,0xf0,EOT},
253 {NANA,NANA,NANA,NANA,0x00,EOT}},
254 {0x3, "UART4",
255 {0x30,0x60,0x61,0x70,0xf0,EOT},
256 {NANA,NANA,NANA,NANA,0x00,EOT}},
257 {0x8, "WDT",
258 {0x30,0x60,0x61,0x70,0xf0,0xf1,EOT},
259 {0x00,NANA,NANA,NANA,NANA,NANA,EOT}},
260 {EOT}}},
261 {0x1602, "F81216AD", {
262 {NOLDN, NULL,
263 {0x25,0x27,EOT},
264 {0x00,NANA,EOT}},
265 {0x0, "UART1",
266 {0x30,0x60,0x61,0x70,0xf0,0xf1,0xf4,0xf5,EOT},
267 {NANA,NANA,NANA,NANA,0x00,0x40,0x00,0x00,EOT}},
268 {0x1, "UART2",
269 {0x30,0x60,0x61,0x70,0xf0,0xf4,0xf5,EOT},
270 {NANA,NANA,NANA,NANA,0x00,0x00,0x00,EOT}},
271 {0x2, "UART3",
272 {0x30,0x60,0x61,0x70,0xf0,0xf4,0xf5,EOT},
273 {NANA,NANA,NANA,NANA,0x00,0x00,0x00,EOT}},
274 {0x3, "UART4",
275 {0x30,0x60,0x61,0x70,0xf0,0xf4,0xf5,EOT},
276 {NANA,NANA,NANA,NANA,0x00,0x00,0x00,EOT}},
277 {0x8, "WDT",
278 {0x30,0x60,0x61,0x70,0xf0,0xf1,EOT},
279 {0x00,NANA,NANA,NANA,NANA,NANA,EOT}},
280 {EOT}}},
281 {0x0407, "F81865F/F-I", {
282 {NOLDN, NULL,
283 {0x02,0x07,0x20,0x21,0x23,0x24,0x25,0x26,0x27,0x28,0x29,0x2a-1,0x2a-2,0x2b,0x2c,0x2d,EOT},
284 {NANA,0x00,0x07,0x04,0x19,0x34,NANA,NANA,NANA,0x00,0x00,0x00,0x00,0x1f,0x00,0x08,EOT}},
285 {0x00, "FDC",
286 {0x30,0x60,0x61,0x70,0x74,0xf0,0xf2,0xf4,EOT},
287 {NANA,0x03,0xf0,NANA,NANA,NANA,NANA,NANA,EOT}},
288 {0x03, "LPT",
289 {0x30,0x60,0x61,0x70,0x74,0xf0,EOT},
290 {NANA,0x03,0x78,NANA,NANA,NANA,EOT}},
291 {0x04, "HWMON",
292 {0x30,0x60,0x61,0x70,EOT},
293 {NANA,0x02,0x95,NANA,EOT}},
294 {0x05, "KBC",
295 {0x30,0x60,0x61,0x70,0x72,0xfe,0xf0,EOT},
296 {NANA,0x00,0x60,NANA,NANA,NANA,0x71,EOT}},
297 {0x06, "GPIO",
298 {0x30,0x60,0x61,0x70,0xf1,0xf2,0xf3,0xf3,0xf4,0xf5,0xf6,0xf7,0xf8,0xf9,0xe0,0xe1,0xe2,0xe3,0xef,0xd0,0xd1,0xd2,0xd3,0xc0,0xc1,0xc2,0xc3,0xb0,0xb1,0xb2,0xb3,0xa0,0xa1,0xa2,0xa3,0x90,0x91,0x92,0x93,EOT},
299 {NANA,0x00,0x60,NANA,0x00,NANA,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xff,NANA,0x00,NANA,0x00,0xff,NANA,0x00,0x00,0xff,NANA,0x00,0x00,0xff,NANA,0x00,0x00,0xff,NANA,0x00,NANA,NANA,NANA,NANA,EOT}},
300 {0x07, "WDT",
301 {0x30,0x60,0x61,0xf5,0xf6,0xfa,EOT},
302 {NANA,0x00,0x00,0x00,0x00,NANA,EOT}},
303 {0x08, "SPI",
304 {0xf0,0xf1,0xf2,0xf3,0xf4,0xf5,0xf6,0xf7,0xf8,0xfa,0xfb,0xfc,0xfd,0xfe,0xff,EOT},
305 {0x10,0x04,NANA,NANA,0x00,0x00,NANA,NANA,0x00,0x00,0x00,0x00,0x00,0x00,0x00,EOT}},
306 {0x0a, "PME & ACPI",
307 {0x30,0xf0,0xf1,0xf2,0xf3,0xf4,0xf5,0xf6,EOT},
308 {NANA,NANA,NANA,NANA,NANA,0x06,NANA,0x00,EOT}},
309 {0x0b, "RTC",
310 {0x30,0x60,0x61,0x70,EOT},
311 {NANA,0x00,0x00,NANA,EOT}},
312 {0x10, "UART1",
313 {0x30,0x60,0x61,0x70,0xf0,0xf2,0xf4,0xf5,EOT},
314 {NANA,0x03,0xf8,NANA,NANA,NANA,0x00,0x00,EOT}},
315 {0x11, "UART2",
316 {0x30,0x60,0x61,0x70,0xf0,0xf2,0xf4,0xf5,EOT},
317 {NANA,0x02,0xf8,NANA,NANA,NANA,0x00,0x00,EOT}},
318 {0x12, "UART3",
319 {0x30,0x60,0x61,0x70,0xf0,0xf2,0xf4,0xf5,EOT},
320 {NANA,0x03,0xe8,NANA,NANA,NANA,0x00,0x00,EOT}},
321 {0x13, "UART4",
322 {0x30,0x60,0x61,0x70,0xf0,0xf2,0xf4,0xf5,EOT},
323 {NANA,0x02,0xe8,NANA,NANA,NANA,0x00,0x00,EOT}},
324 {0x14, "UART5",
325 {0x30,0x60,0x61,0x70,0xf0,0xf2,0xf4,0xf5,EOT},
326 {NANA,0x00,0x00,NANA,NANA,NANA,0x00,0x00,EOT}},
327 {0x15, "UART6",
328 {0x30,0x60,0x61,0x70,0xf0,0xf2,0xf4,0xf5,EOT},
329 {NANA,0x00,0x00,NANA,NANA,NANA,0x00,0x00,EOT}},
330 {EOT}}},
331 {EOT}
332 };
333
probe_idregs_fintek(uint16_t port)334 void probe_idregs_fintek(uint16_t port)
335 {
336 uint16_t vid, did;
337
338 probing_for("Fintek", "", port);
339
340 enter_conf_mode_winbond_fintek_ite_8787(port);
341
342 did = regval(port, DEVICE_ID_BYTE1_REG);
343 did |= (regval(port, DEVICE_ID_BYTE2_REG) << 8);
344
345 vid = regval(port, VENDOR_ID_BYTE1_REG);
346 vid |= (regval(port, VENDOR_ID_BYTE2_REG) << 8);
347
348 if (vid != FINTEK_VENDOR_ID || superio_unknown(reg_table, did)) {
349 if (verbose)
350 printf(NOTFOUND "vid=0x%04x, id=0x%04x\n", vid, did);
351 exit_conf_mode_winbond_fintek_ite_8787(port);
352 return;
353 }
354
355 printf("Found Fintek %s (vid=0x%04x, id=0x%04x) at 0x%x\n",
356 get_superio_name(reg_table, did), vid, did, port);
357 chip_found = 1;
358
359 dump_superio("Fintek", reg_table, port, did, LDN_SEL);
360
361 exit_conf_mode_winbond_fintek_ite_8787(port);
362 }
363
364
probe_idregs_fintek_alternative(uint16_t port)365 void probe_idregs_fintek_alternative(uint16_t port)
366 {
367 uint16_t vid, did;
368
369 probing_for("Fintek", "", port);
370
371 enter_conf_mode_fintek_7777(port);
372
373 did = regval(port, DEVICE_ID_BYTE1_REG);
374 did |= (regval(port, DEVICE_ID_BYTE2_REG) << 8);
375
376 vid = regval(port, VENDOR_ID_BYTE1_REG);
377 vid |= (regval(port, VENDOR_ID_BYTE2_REG) << 8);
378
379 if (vid != FINTEK_VENDOR_ID || superio_unknown(reg_table, did)) {
380 if (verbose)
381 printf(NOTFOUND "vid=0x%04x, id=0x%04x\n", vid, did);
382 exit_conf_mode_fintek_7777(port);
383 return;
384 }
385
386 printf("Found Fintek %s (vid=0x%04x, id=0x%04x) at 0x%x\n",
387 get_superio_name(reg_table, did), vid, did, port);
388 chip_found = 1;
389
390 dump_superio("Fintek", reg_table, port, did, LDN_SEL);
391
392 exit_conf_mode_fintek_7777(port);
393 }
394
print_fintek_chips(void)395 void print_fintek_chips(void)
396 {
397 print_vendor_chips("Fintek", reg_table);
398 }
399