1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * Copyright 2013-2015 Freescale Semiconductor, Inc. 4 */ 5 6 #ifndef __ARCH_FSL_LSCH2_IMMAP_H__ 7 #define __ARCH_FSL_LSCH2_IMMAP_H__ 8 9 #include <fsl_immap.h> 10 #ifndef __ASSEMBLY__ 11 #include <linux/bitops.h> 12 #endif 13 14 #define CONFIG_SYS_IMMR 0x01000000 15 #define CONFIG_SYS_DCSRBAR 0x20000000 16 #define CONFIG_SYS_DCSR_DCFG_ADDR (CONFIG_SYS_DCSRBAR + 0x00140000) 17 #define CONFIG_SYS_DCSR_COP_CCP_ADDR (CONFIG_SYS_DCSRBAR + 0x02008040) 18 19 #define CONFIG_SYS_FSL_DDR_ADDR (CONFIG_SYS_IMMR + 0x00080000) 20 #define CONFIG_SYS_GIC400_ADDR (CONFIG_SYS_IMMR + 0x00400000) 21 #define CONFIG_SYS_IFC_ADDR (CONFIG_SYS_IMMR + 0x00530000) 22 #define SYS_FSL_QSPI_ADDR (CONFIG_SYS_IMMR + 0x00550000) 23 #define CONFIG_SYS_FSL_ESDHC_ADDR (CONFIG_SYS_IMMR + 0x00560000) 24 #define CONFIG_SYS_FSL_CSU_ADDR (CONFIG_SYS_IMMR + 0x00510000) 25 #define CONFIG_SYS_FSL_GUTS_ADDR (CONFIG_SYS_IMMR + 0x00ee0000) 26 #define CONFIG_SYS_FSL_RST_ADDR (CONFIG_SYS_IMMR + 0x00ee00b0) 27 #define CONFIG_SYS_FSL_SCFG_ADDR (CONFIG_SYS_IMMR + 0x00570000) 28 #define CONFIG_SYS_FSL_BMAN_ADDR (CONFIG_SYS_IMMR + 0x00890000) 29 #define CONFIG_SYS_FSL_QMAN_ADDR (CONFIG_SYS_IMMR + 0x00880000) 30 #define CONFIG_SYS_FSL_FMAN_ADDR (CONFIG_SYS_IMMR + 0x00a00000) 31 #define CONFIG_SYS_FSL_SERDES_ADDR (CONFIG_SYS_IMMR + 0x00ea0000) 32 #define CONFIG_SYS_FSL_DCFG_ADDR (CONFIG_SYS_IMMR + 0x00ee0000) 33 #define CONFIG_SYS_FSL_CLK_ADDR (CONFIG_SYS_IMMR + 0x00ee1000) 34 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR + 0x011c0500) 35 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR + 0x011c0600) 36 #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_IMMR + 0x011d0500) 37 #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_IMMR + 0x011d0600) 38 #define CONFIG_SYS_XHCI_USB1_ADDR (CONFIG_SYS_IMMR + 0x01f00000) 39 #define CONFIG_SYS_XHCI_USB2_ADDR (CONFIG_SYS_IMMR + 0x02000000) 40 #define CONFIG_SYS_XHCI_USB3_ADDR (CONFIG_SYS_IMMR + 0x02100000) 41 #define CONFIG_SYS_EHCI_USB1_ADDR (CONFIG_SYS_IMMR + 0x07600000) 42 #define CONFIG_SYS_PCIE1_ADDR (CONFIG_SYS_IMMR + 0x2400000) 43 #define CONFIG_SYS_PCIE2_ADDR (CONFIG_SYS_IMMR + 0x2500000) 44 #define CONFIG_SYS_PCIE3_ADDR (CONFIG_SYS_IMMR + 0x2600000) 45 #define CONFIG_SYS_SEC_MON_ADDR (CONFIG_SYS_IMMR + 0xe90000) 46 #define CONFIG_SYS_SFP_ADDR (CONFIG_SYS_IMMR + 0xe80200) 47 48 #define CONFIG_SYS_BMAN_NUM_PORTALS 10 49 #define CONFIG_SYS_BMAN_MEM_BASE 0x508000000 50 #define CONFIG_SYS_BMAN_MEM_PHYS (0xf00000000ull + \ 51 CONFIG_SYS_BMAN_MEM_BASE) 52 #define CONFIG_SYS_BMAN_MEM_SIZE 0x08000000 53 #define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x10000 54 #define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x10000 55 #define CONFIG_SYS_BMAN_CENA_BASE CONFIG_SYS_BMAN_MEM_BASE 56 #define CONFIG_SYS_BMAN_CENA_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) 57 #define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \ 58 CONFIG_SYS_BMAN_CENA_SIZE) 59 #define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) 60 #define CONFIG_SYS_BMAN_SWP_ISDR_REG 0x3E80 61 #define CONFIG_SYS_QMAN_NUM_PORTALS 10 62 #define CONFIG_SYS_QMAN_MEM_BASE 0x500000000 63 #define CONFIG_SYS_QMAN_MEM_PHYS CONFIG_SYS_QMAN_MEM_BASE 64 #define CONFIG_SYS_QMAN_MEM_SIZE 0x08000000 65 #define CONFIG_SYS_QMAN_SP_CENA_SIZE 0x10000 66 #define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x10000 67 #define CONFIG_SYS_QMAN_CENA_BASE CONFIG_SYS_QMAN_MEM_BASE 68 #define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) 69 #define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \ 70 CONFIG_SYS_QMAN_CENA_SIZE) 71 #define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) 72 #define CONFIG_SYS_QMAN_SWP_ISDR_REG 0x3680 73 74 #define CONFIG_SYS_FSL_TIMER_ADDR 0x02b00000 75 76 #define I2C1_BASE_ADDR (CONFIG_SYS_IMMR + 0x01180000) 77 #define I2C2_BASE_ADDR (CONFIG_SYS_IMMR + 0x01190000) 78 #define I2C3_BASE_ADDR (CONFIG_SYS_IMMR + 0x011a0000) 79 #define I2C4_BASE_ADDR (CONFIG_SYS_IMMR + 0x011b0000) 80 81 #define WDOG1_BASE_ADDR (CONFIG_SYS_IMMR + 0x01ad0000) 82 83 #define QSPI0_BASE_ADDR (CONFIG_SYS_IMMR + 0x00550000) 84 #define DSPI1_BASE_ADDR (CONFIG_SYS_IMMR + 0x01100000) 85 86 #define GPIO1_BASE_ADDR (CONFIG_SYS_IMMR + 0x1300000) 87 #define GPIO2_BASE_ADDR (CONFIG_SYS_IMMR + 0x1310000) 88 #define GPIO3_BASE_ADDR (CONFIG_SYS_IMMR + 0x1320000) 89 #define GPIO4_BASE_ADDR (CONFIG_SYS_IMMR + 0x1330000) 90 91 #define QE_BASE_ADDR (CONFIG_SYS_IMMR + 0x1400000) 92 93 #define LPUART_BASE (CONFIG_SYS_IMMR + 0x01950000) 94 95 #define EDMA_BASE_ADDR (CONFIG_SYS_IMMR + 0x01c00000) 96 97 #define AHCI_BASE_ADDR (CONFIG_SYS_IMMR + 0x02200000) 98 99 #define QDMA_BASE_ADDR (CONFIG_SYS_IMMR + 0x07380000) 100 #define QMAN_CQSIDR_REG 0x20a80 101 102 #define CONFIG_SYS_PCIE1_PHYS_ADDR 0x4000000000ULL 103 #define CONFIG_SYS_PCIE2_PHYS_ADDR 0x4800000000ULL 104 #define CONFIG_SYS_PCIE3_PHYS_ADDR 0x5000000000ULL 105 /* LUT registers */ 106 #ifdef CONFIG_ARCH_LS1012A 107 #define PCIE_LUT_BASE 0xC0000 108 #else 109 #define PCIE_LUT_BASE 0x10000 110 #endif 111 #define PCIE_LUT_LCTRL0 0x7F8 112 #define PCIE_LUT_DBG 0x7FC 113 114 /* TZ Address Space Controller Definitions */ 115 #define TZASC1_BASE 0x01100000 /* as per CCSR map. */ 116 #define TZASC2_BASE 0x01110000 /* as per CCSR map. */ 117 #define TZASC3_BASE 0x01120000 /* as per CCSR map. */ 118 #define TZASC4_BASE 0x01130000 /* as per CCSR map. */ 119 #define TZASC_BUILD_CONFIG_REG(x) ((TZASC1_BASE + (x * 0x10000))) 120 #define TZASC_ACTION_REG(x) ((TZASC1_BASE + (x * 0x10000)) + 0x004) 121 #define TZASC_GATE_KEEPER(x) ((TZASC1_BASE + (x * 0x10000)) + 0x008) 122 #define TZASC_REGION_BASE_LOW_0(x) ((TZASC1_BASE + (x * 0x10000)) + 0x100) 123 #define TZASC_REGION_BASE_HIGH_0(x) ((TZASC1_BASE + (x * 0x10000)) + 0x104) 124 #define TZASC_REGION_TOP_LOW_0(x) ((TZASC1_BASE + (x * 0x10000)) + 0x108) 125 #define TZASC_REGION_TOP_HIGH_0(x) ((TZASC1_BASE + (x * 0x10000)) + 0x10C) 126 #define TZASC_REGION_ATTRIBUTES_0(x) ((TZASC1_BASE + (x * 0x10000)) + 0x110) 127 #define TZASC_REGION_ID_ACCESS_0(x) ((TZASC1_BASE + (x * 0x10000)) + 0x114) 128 129 #define TP_ITYP_AV 0x00000001 /* Initiator available */ 130 #define TP_ITYP_TYPE(x) (((x) & 0x6) >> 1) /* Initiator Type */ 131 #define TP_ITYP_TYPE_ARM 0x0 132 #define TP_ITYP_TYPE_PPC 0x1 /* PowerPC */ 133 #define TP_ITYP_TYPE_OTHER 0x2 /* StarCore DSP */ 134 #define TP_ITYP_TYPE_HA 0x3 /* HW Accelerator */ 135 #define TP_ITYP_THDS(x) (((x) & 0x18) >> 3) /* # threads */ 136 #define TP_ITYP_VER(x) (((x) & 0xe0) >> 5) /* Initiator Version */ 137 #define TY_ITYP_VER_A7 0x1 138 #define TY_ITYP_VER_A53 0x2 139 #define TY_ITYP_VER_A57 0x3 140 #define TY_ITYP_VER_A72 0x4 141 142 #define TP_CLUSTER_EOC 0xc0000000 /* end of clusters */ 143 #define TP_CLUSTER_INIT_MASK 0x0000003f /* initiator mask */ 144 #define TP_INIT_PER_CLUSTER 4 145 146 /* 147 * Define default values for some CCSR macros to make header files cleaner* 148 * 149 * To completely disable CCSR relocation in a board header file, define 150 * CONFIG_SYS_CCSR_DO_NOT_RELOCATE. This will force CONFIG_SYS_CCSRBAR_PHYS 151 * to a value that is the same as CONFIG_SYS_CCSRBAR. 152 */ 153 154 #ifdef CONFIG_SYS_CCSRBAR_PHYS 155 #error "Do not define CONFIG_SYS_CCSRBAR_PHYS directly. Use \ 156 CONFIG_SYS_CCSRBAR_PHYS_LOW and/or CONFIG_SYS_CCSRBAR_PHYS_HIGH instead." 157 #endif 158 159 #ifdef CONFIG_SYS_CCSR_DO_NOT_RELOCATE 160 #undef CONFIG_SYS_CCSRBAR_PHYS_HIGH 161 #undef CONFIG_SYS_CCSRBAR_PHYS_LOW 162 #define CONFIG_SYS_CCSRBAR_PHYS_HIGH 0 163 #endif 164 165 #ifndef CONFIG_SYS_CCSRBAR 166 #define CONFIG_SYS_CCSRBAR 0x01000000 167 #endif 168 169 #ifndef CONFIG_SYS_CCSRBAR_PHYS_HIGH 170 #define CONFIG_SYS_CCSRBAR_PHYS_HIGH 0 171 #endif 172 173 #ifndef CONFIG_SYS_CCSRBAR_PHYS_LOW 174 #define CONFIG_SYS_CCSRBAR_PHYS_LOW 0x01000000 175 #endif 176 177 #define CONFIG_SYS_CCSRBAR_PHYS ((CONFIG_SYS_CCSRBAR_PHYS_HIGH * 1ull) << 32 | \ 178 CONFIG_SYS_CCSRBAR_PHYS_LOW) 179 180 struct sys_info { 181 unsigned long freq_processor[CONFIG_MAX_CPUS]; 182 /* frequency of platform PLL */ 183 unsigned long freq_systembus; 184 unsigned long freq_ddrbus; 185 unsigned long freq_localbus; 186 unsigned long freq_cga_m2; 187 #ifdef CONFIG_SYS_DPAA_FMAN 188 unsigned long freq_fman[CONFIG_SYS_NUM_FMAN]; 189 #endif 190 unsigned long freq_qman; 191 }; 192 193 #define CONFIG_SYS_FSL_FM1_OFFSET 0xa00000 194 #define CONFIG_SYS_FSL_FM1_RX0_1G_OFFSET 0xa88000 195 #define CONFIG_SYS_FSL_FM1_RX1_1G_OFFSET 0xa89000 196 #define CONFIG_SYS_FSL_FM1_RX2_1G_OFFSET 0xa8a000 197 #define CONFIG_SYS_FSL_FM1_RX3_1G_OFFSET 0xa8b000 198 #define CONFIG_SYS_FSL_FM1_RX4_1G_OFFSET 0xa8c000 199 #define CONFIG_SYS_FSL_FM1_RX5_1G_OFFSET 0xa8d000 200 201 #define CONFIG_SYS_FSL_FM1_DTSEC1_OFFSET 0xae0000 202 #define CONFIG_SYS_FSL_FM1_ADDR \ 203 (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_FM1_OFFSET) 204 #define CONFIG_SYS_FSL_FM1_DTSEC1_ADDR \ 205 (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_FM1_DTSEC1_OFFSET) 206 207 #define CONFIG_SYS_FSL_SEC_OFFSET 0x700000ull 208 #define CONFIG_SYS_FSL_JR0_OFFSET 0x710000ull 209 #define FSL_SEC_JR0_OFFSET CONFIG_SYS_FSL_JR0_OFFSET 210 #define FSL_SEC_JR1_OFFSET 0x720000ull 211 #define FSL_SEC_JR2_OFFSET 0x730000ull 212 #define FSL_SEC_JR3_OFFSET 0x740000ull 213 #define CONFIG_SYS_FSL_SEC_ADDR \ 214 (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_SEC_OFFSET) 215 #define CONFIG_SYS_FSL_JR0_ADDR \ 216 (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_JR0_OFFSET) 217 #define FSL_SEC_JR0_BASE_ADDR (CONFIG_SYS_IMMR + FSL_SEC_JR0_OFFSET) 218 #define FSL_SEC_JR1_BASE_ADDR (CONFIG_SYS_IMMR + FSL_SEC_JR1_OFFSET) 219 #define FSL_SEC_JR2_BASE_ADDR (CONFIG_SYS_IMMR + FSL_SEC_JR2_OFFSET) 220 #define FSL_SEC_JR3_BASE_ADDR (CONFIG_SYS_IMMR + FSL_SEC_JR3_OFFSET) 221 222 /* Device Configuration and Pin Control */ 223 #define DCFG_DCSR_PORCR1 0x0 224 #define DCFG_DCSR_ECCCR2 0x524 225 #define DISABLE_PFE_ECC BIT(13) 226 227 struct ccsr_gur { 228 u32 porsr1; /* POR status 1 */ 229 #define FSL_CHASSIS2_CCSR_PORSR1_RCW_MASK 0xFF800000 230 u32 porsr2; /* POR status 2 */ 231 u8 res_008[0x20-0x8]; 232 u32 gpporcr1; /* General-purpose POR configuration */ 233 u32 gpporcr2; 234 #define FSL_CHASSIS2_DCFG_FUSESR_VID_SHIFT 25 235 #define FSL_CHASSIS2_DCFG_FUSESR_VID_MASK 0x1F 236 #define FSL_CHASSIS2_DCFG_FUSESR_ALTVID_SHIFT 20 237 #define FSL_CHASSIS2_DCFG_FUSESR_ALTVID_MASK 0x1F 238 u32 dcfg_fusesr; /* Fuse status register */ 239 u8 res_02c[0x70-0x2c]; 240 u32 devdisr; /* Device disable control */ 241 #define FSL_CHASSIS2_DEVDISR2_DTSEC1_1 0x80000000 242 #define FSL_CHASSIS2_DEVDISR2_DTSEC1_2 0x40000000 243 #define FSL_CHASSIS2_DEVDISR2_DTSEC1_3 0x20000000 244 #define FSL_CHASSIS2_DEVDISR2_DTSEC1_4 0x10000000 245 #define FSL_CHASSIS2_DEVDISR2_DTSEC1_5 0x08000000 246 #define FSL_CHASSIS2_DEVDISR2_DTSEC1_6 0x04000000 247 #define FSL_CHASSIS2_DEVDISR2_DTSEC1_9 0x00800000 248 #define FSL_CHASSIS2_DEVDISR2_DTSEC1_10 0x00400000 249 #define FSL_CHASSIS2_DEVDISR2_10GEC1_1 0x00800000 250 #define FSL_CHASSIS2_DEVDISR2_10GEC1_2 0x00400000 251 #define FSL_CHASSIS2_DEVDISR2_10GEC1_3 0x80000000 252 #define FSL_CHASSIS2_DEVDISR2_10GEC1_4 0x40000000 253 u32 devdisr2; /* Device disable control 2 */ 254 u32 devdisr3; /* Device disable control 3 */ 255 u32 devdisr4; /* Device disable control 4 */ 256 u32 devdisr5; /* Device disable control 5 */ 257 u32 devdisr6; /* Device disable control 6 */ 258 u32 devdisr7; /* Device disable control 7 */ 259 u8 res_08c[0x94-0x8c]; 260 u32 coredisru; /* uppper portion for support of 64 cores */ 261 u32 coredisrl; /* lower portion for support of 64 cores */ 262 u8 res_09c[0xa0-0x9c]; 263 u32 pvr; /* Processor version */ 264 u32 svr; /* System version */ 265 u32 mvr; /* Manufacturing version */ 266 u8 res_0ac[0xb0-0xac]; 267 u32 rstcr; /* Reset control */ 268 u32 rstrqpblsr; /* Reset request preboot loader status */ 269 u8 res_0b8[0xc0-0xb8]; 270 u32 rstrqmr1; /* Reset request mask */ 271 u8 res_0c4[0xc8-0xc4]; 272 u32 rstrqsr1; /* Reset request status */ 273 u8 res_0cc[0xd4-0xcc]; 274 u32 rstrqwdtmrl; /* Reset request WDT mask */ 275 u8 res_0d8[0xdc-0xd8]; 276 u32 rstrqwdtsrl; /* Reset request WDT status */ 277 u8 res_0e0[0xe4-0xe0]; 278 u32 brrl; /* Boot release */ 279 u8 res_0e8[0x100-0xe8]; 280 u32 rcwsr[16]; /* Reset control word status */ 281 #define FSL_CHASSIS2_RCWSR0_SYS_PLL_RAT_SHIFT 25 282 #define FSL_CHASSIS2_RCWSR0_SYS_PLL_RAT_MASK 0x1f 283 #define FSL_CHASSIS2_RCWSR0_MEM_PLL_RAT_SHIFT 16 284 #define FSL_CHASSIS2_RCWSR0_MEM_PLL_RAT_MASK 0x3f 285 #define FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_MASK 0xffff0000 286 #define FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_SHIFT 16 287 #define FSL_CHASSIS2_RCWSR4_SRDS2_PRTCL_MASK 0x0000ffff 288 #define FSL_CHASSIS2_RCWSR4_SRDS2_PRTCL_SHIFT 0 289 #define RCW_SB_EN_REG_INDEX 7 290 #define RCW_SB_EN_MASK 0x00200000 291 292 u8 res_140[0x200-0x140]; 293 u32 scratchrw[4]; /* Scratch Read/Write */ 294 u8 res_210[0x300-0x210]; 295 u32 scratchw1r[4]; /* Scratch Read (Write once) */ 296 u8 res_310[0x400-0x310]; 297 u32 crstsr[12]; 298 u8 res_430[0x500-0x430]; 299 300 /* PCI Express n Logical I/O Device Number register */ 301 u32 dcfg_ccsr_pex1liodnr; 302 u32 dcfg_ccsr_pex2liodnr; 303 u32 dcfg_ccsr_pex3liodnr; 304 u32 dcfg_ccsr_pex4liodnr; 305 /* RIO n Logical I/O Device Number register */ 306 u32 dcfg_ccsr_rio1liodnr; 307 u32 dcfg_ccsr_rio2liodnr; 308 u32 dcfg_ccsr_rio3liodnr; 309 u32 dcfg_ccsr_rio4liodnr; 310 /* USB Logical I/O Device Number register */ 311 u32 dcfg_ccsr_usb1liodnr; 312 u32 dcfg_ccsr_usb2liodnr; 313 u32 dcfg_ccsr_usb3liodnr; 314 u32 dcfg_ccsr_usb4liodnr; 315 /* SD/MMC Logical I/O Device Number register */ 316 u32 dcfg_ccsr_sdmmc1liodnr; 317 u32 dcfg_ccsr_sdmmc2liodnr; 318 u32 dcfg_ccsr_sdmmc3liodnr; 319 u32 dcfg_ccsr_sdmmc4liodnr; 320 /* RIO Message Unit Logical I/O Device Number register */ 321 u32 dcfg_ccsr_riomaintliodnr; 322 323 u8 res_544[0x550-0x544]; 324 u32 sataliodnr[4]; 325 u8 res_560[0x570-0x560]; 326 327 u32 dcfg_ccsr_misc1liodnr; 328 u32 dcfg_ccsr_misc2liodnr; 329 u32 dcfg_ccsr_misc3liodnr; 330 u32 dcfg_ccsr_misc4liodnr; 331 u32 dcfg_ccsr_dma1liodnr; 332 u32 dcfg_ccsr_dma2liodnr; 333 u32 dcfg_ccsr_dma3liodnr; 334 u32 dcfg_ccsr_dma4liodnr; 335 u32 dcfg_ccsr_spare1liodnr; 336 u32 dcfg_ccsr_spare2liodnr; 337 u32 dcfg_ccsr_spare3liodnr; 338 u32 dcfg_ccsr_spare4liodnr; 339 u8 res_5a0[0x600-0x5a0]; 340 u32 dcfg_ccsr_pblsr; 341 342 u32 pamubypenr; 343 u32 dmacr1; 344 345 u8 res_60c[0x610-0x60c]; 346 u32 dcfg_ccsr_gensr1; 347 u32 dcfg_ccsr_gensr2; 348 u32 dcfg_ccsr_gensr3; 349 u32 dcfg_ccsr_gensr4; 350 u32 dcfg_ccsr_gencr1; 351 u32 dcfg_ccsr_gencr2; 352 u32 dcfg_ccsr_gencr3; 353 u32 dcfg_ccsr_gencr4; 354 u32 dcfg_ccsr_gencr5; 355 u32 dcfg_ccsr_gencr6; 356 u32 dcfg_ccsr_gencr7; 357 u8 res_63c[0x658-0x63c]; 358 u32 dcfg_ccsr_cgensr1; 359 u32 dcfg_ccsr_cgensr0; 360 u8 res_660[0x678-0x660]; 361 u32 dcfg_ccsr_cgencr1; 362 363 u32 dcfg_ccsr_cgencr0; 364 u8 res_680[0x700-0x680]; 365 u32 dcfg_ccsr_sriopstecr; 366 u32 dcfg_ccsr_dcsrcr; 367 368 u8 res_708[0x740-0x708]; /* add more registers when needed */ 369 u32 tp_ityp[64]; /* Topology Initiator Type Register */ 370 struct { 371 u32 upper; 372 u32 lower; 373 } tp_cluster[16]; 374 u8 res_8c0[0xa00-0x8c0]; /* add more registers when needed */ 375 u32 dcfg_ccsr_qmbm_warmrst; 376 u8 res_a04[0xa20-0xa04]; /* add more registers when needed */ 377 u32 dcfg_ccsr_reserved0; 378 u32 dcfg_ccsr_reserved1; 379 }; 380 381 #define SCFG_QSPI_CLKSEL 0x40100000 382 #define SCFG_USBDRVVBUS_SELCR_USB1 0x00000000 383 #define SCFG_USBDRVVBUS_SELCR_USB2 0x00000001 384 #define SCFG_USBDRVVBUS_SELCR_USB3 0x00000002 385 #define SCFG_USBPWRFAULT_INACTIVE 0x00000000 386 #define SCFG_USBPWRFAULT_SHARED 0x00000001 387 #define SCFG_USBPWRFAULT_DEDICATED 0x00000002 388 #define SCFG_USBPWRFAULT_USB3_SHIFT 4 389 #define SCFG_USBPWRFAULT_USB2_SHIFT 2 390 #define SCFG_USBPWRFAULT_USB1_SHIFT 0 391 392 #define SCFG_BASE 0x01570000 393 #define SCFG_USB3PRM1CR_USB1 0x070 394 #define SCFG_USB3PRM2CR_USB1 0x074 395 #define SCFG_USB3PRM1CR_USB2 0x07C 396 #define SCFG_USB3PRM2CR_USB2 0x080 397 #define SCFG_USB3PRM1CR_USB3 0x088 398 #define SCFG_USB3PRM2CR_USB3 0x08c 399 #define SCFG_USB_TXVREFTUNE 0x9 400 #define SCFG_USB_SQRXTUNE_MASK 0x7 401 #define SCFG_USB_PCSTXSWINGFULL 0x47 402 #define SCFG_USB_PHY1 0x084F0000 403 #define SCFG_USB_PHY2 0x08500000 404 #define SCFG_USB_PHY3 0x08510000 405 #define SCFG_USB_PHY_RX_OVRD_IN_HI 0x200c 406 #define USB_PHY_RX_EQ_VAL_1 0x0000 407 #define USB_PHY_RX_EQ_VAL_2 0x0080 408 #define USB_PHY_RX_EQ_VAL_3 0x0380 409 #define USB_PHY_RX_EQ_VAL_4 0x0b80 410 411 #define SCFG_SNPCNFGCR_SECRDSNP 0x80000000 412 #define SCFG_SNPCNFGCR_SECWRSNP 0x40000000 413 #define SCFG_SNPCNFGCR_SATARDSNP 0x00800000 414 #define SCFG_SNPCNFGCR_SATAWRSNP 0x00400000 415 #define SCFG_SNPCNFGCR_USB1RDSNP 0x00200000 416 #define SCFG_SNPCNFGCR_USB1WRSNP 0x00100000 417 #define SCFG_SNPCNFGCR_USB2RDSNP 0x00008000 418 #define SCFG_SNPCNFGCR_USB2WRSNP 0x00010000 419 #define SCFG_SNPCNFGCR_USB3RDSNP 0x00002000 420 #define SCFG_SNPCNFGCR_USB3WRSNP 0x00004000 421 422 /* RGMIIPCR bit definitions*/ 423 #define SCFG_RGMIIPCR_EN_AUTO BIT(3) 424 #define SCFG_RGMIIPCR_SETSP_1000M BIT(2) 425 #define SCFG_RGMIIPCR_SETSP_100M 0 426 #define SCFG_RGMIIPCR_SETSP_10M BIT(1) 427 #define SCFG_RGMIIPCR_SETFD BIT(0) 428 429 /* PFEASBCR bit definitions */ 430 #define SCFG_PFEASBCR_ARCACHE0 BIT(31) 431 #define SCFG_PFEASBCR_AWCACHE0 BIT(30) 432 #define SCFG_PFEASBCR_ARCACHE1 BIT(29) 433 #define SCFG_PFEASBCR_AWCACHE1 BIT(28) 434 #define SCFG_PFEASBCR_ARSNP BIT(27) 435 #define SCFG_PFEASBCR_AWSNP BIT(26) 436 437 /* WR_QoS1 PFE bit definitions */ 438 #define SCFG_WR_QOS1_PFE1_QOS GENMASK(27, 24) 439 #define SCFG_WR_QOS1_PFE2_QOS GENMASK(23, 20) 440 441 /* RD_QoS1 PFE bit definitions */ 442 #define SCFG_RD_QOS1_PFE1_QOS GENMASK(27, 24) 443 #define SCFG_RD_QOS1_PFE2_QOS GENMASK(23, 20) 444 445 /* Supplemental Configuration Unit */ 446 struct ccsr_scfg { 447 u8 res_000[0x100-0x000]; 448 u32 usb2_icid; 449 u32 usb3_icid; 450 u8 res_108[0x114-0x108]; 451 u32 dma_icid; 452 u32 sata_icid; 453 u32 usb1_icid; 454 u32 qe_icid; 455 u32 sdhc_icid; 456 u32 edma_icid; 457 u32 etr_icid; 458 u32 core_sft_rst[4]; 459 u8 res_140[0x158-0x140]; 460 u32 altcbar; 461 u32 qspi_cfg; 462 u8 res_160[0x164 - 0x160]; 463 u32 wr_qos1; 464 u32 wr_qos2; 465 u32 rd_qos1; 466 u32 rd_qos2; 467 u8 res_174[0x180 - 0x174]; 468 u32 dmamcr; 469 u8 res_184[0x188-0x184]; 470 u32 gic_align; 471 u32 debug_icid; 472 u8 res_190[0x1a4-0x190]; 473 u32 snpcnfgcr; 474 u8 res_1a8[0x1ac-0x1a8]; 475 u32 intpcr; 476 u8 res_1b0[0x204-0x1b0]; 477 u32 coresrencr; 478 u8 res_208[0x220-0x208]; 479 u32 rvbar0_0; 480 u32 rvbar0_1; 481 u32 rvbar1_0; 482 u32 rvbar1_1; 483 u32 rvbar2_0; 484 u32 rvbar2_1; 485 u32 rvbar3_0; 486 u32 rvbar3_1; 487 u32 lpmcsr; 488 u8 res_244[0x400-0x244]; 489 u32 qspidqscr; 490 u32 ecgtxcmcr; 491 u32 sdhciovselcr; 492 u32 rcwpmuxcr0; 493 u32 usbdrvvbus_selcr; 494 u32 usbpwrfault_selcr; 495 u32 usb_refclk_selcr1; 496 u32 usb_refclk_selcr2; 497 u32 usb_refclk_selcr3; 498 u8 res_424[0x434 - 0x424]; 499 u32 rgmiipcr; 500 u32 res_438; 501 u32 rgmiipsr; 502 u32 pfepfcssr1; 503 u32 pfeintencr1; 504 u32 pfepfcssr2; 505 u32 pfeintencr2; 506 u32 pfeerrcr; 507 u32 pfeeerrintencr; 508 u32 pfeasbcr; 509 u32 pfebsbcr; 510 u8 res_460[0x484 - 0x460]; 511 u32 mdioselcr; 512 u8 res_468[0x600 - 0x488]; 513 u32 scratchrw[4]; 514 u8 res_610[0x680-0x610]; 515 u32 corebcr; 516 u8 res_684[0x1000-0x684]; 517 u32 pex1msiir; 518 u32 pex1msir; 519 u8 res_1008[0x2000-0x1008]; 520 u32 pex2; 521 u32 pex2msir; 522 u8 res_2008[0x3000-0x2008]; 523 u32 pex3msiir; 524 u32 pex3msir; 525 }; 526 527 /* Clocking */ 528 struct ccsr_clk { 529 struct { 530 u32 clkcncsr; /* core cluster n clock control status */ 531 u8 res_004[0x0c]; 532 u32 clkcghwacsr; /* Clock generator n hardware accelerator */ 533 u8 res_014[0x0c]; 534 } clkcsr[4]; 535 u8 res_040[0x780]; /* 0x100 */ 536 struct { 537 u32 pllcngsr; 538 u8 res_804[0x1c]; 539 } pllcgsr[2]; 540 u8 res_840[0x1c0]; 541 u32 clkpcsr; /* 0xa00 Platform clock domain control/status */ 542 u8 res_a04[0x1fc]; 543 u32 pllpgsr; /* 0xc00 Platform PLL General Status */ 544 u8 res_c04[0x1c]; 545 u32 plldgsr; /* 0xc20 DDR PLL General Status */ 546 u8 res_c24[0x3dc]; 547 }; 548 549 /* System Counter */ 550 struct sctr_regs { 551 u32 cntcr; 552 u32 cntsr; 553 u32 cntcv1; 554 u32 cntcv2; 555 u32 resv1[4]; 556 u32 cntfid0; 557 u32 cntfid1; 558 u32 resv2[1002]; 559 u32 counterid[12]; 560 }; 561 562 #define SRDS_MAX_LANES 4 563 struct ccsr_serdes { 564 struct { 565 u32 rstctl; /* Reset Control Register */ 566 #define SRDS_RSTCTL_RST 0x80000000 567 #define SRDS_RSTCTL_RSTDONE 0x40000000 568 #define SRDS_RSTCTL_RSTERR 0x20000000 569 #define SRDS_RSTCTL_SWRST 0x10000000 570 #define SRDS_RSTCTL_SDEN 0x00000020 571 #define SRDS_RSTCTL_SDRST_B 0x00000040 572 #define SRDS_RSTCTL_PLLRST_B 0x00000080 573 u32 pllcr0; /* PLL Control Register 0 */ 574 #define SRDS_PLLCR0_POFF 0x80000000 575 #define SRDS_PLLCR0_RFCK_SEL_MASK 0x70000000 576 #define SRDS_PLLCR0_RFCK_SEL_100 0x00000000 577 #define SRDS_PLLCR0_RFCK_SEL_125 0x10000000 578 #define SRDS_PLLCR0_RFCK_SEL_156_25 0x20000000 579 #define SRDS_PLLCR0_RFCK_SEL_150 0x30000000 580 #define SRDS_PLLCR0_RFCK_SEL_161_13 0x40000000 581 #define SRDS_PLLCR0_RFCK_SEL_122_88 0x50000000 582 #define SRDS_PLLCR0_PLL_LCK 0x00800000 583 #define SRDS_PLLCR0_FRATE_SEL_MASK 0x000f0000 584 #define SRDS_PLLCR0_FRATE_SEL_5 0x00000000 585 #define SRDS_PLLCR0_FRATE_SEL_3_75 0x00050000 586 #define SRDS_PLLCR0_FRATE_SEL_5_15 0x00060000 587 #define SRDS_PLLCR0_FRATE_SEL_4 0x00070000 588 #define SRDS_PLLCR0_FRATE_SEL_3_12 0x00090000 589 #define SRDS_PLLCR0_FRATE_SEL_3 0x000a0000 590 u32 pllcr1; /* PLL Control Register 1 */ 591 #define SRDS_PLLCR1_PLL_BWSEL 0x08000000 592 u32 res_0c; /* 0x00c */ 593 u32 pllcr3; 594 u32 pllcr4; 595 u32 pllcr5; /* 0x018 SerDes PLL1 Control 5 */ 596 u8 res_1c[0x20-0x1c]; 597 } bank[2]; 598 u8 res_40[0x90-0x40]; 599 u32 srdstcalcr; /* 0x90 TX Calibration Control */ 600 u8 res_94[0xa0-0x94]; 601 u32 srdsrcalcr; /* 0xa0 RX Calibration Control */ 602 u8 res_a4[0xb0-0xa4]; 603 u32 srdsgr0; /* 0xb0 General Register 0 */ 604 u8 res_b4[0x100-0xb4]; 605 struct { 606 u32 lnpssr0; /* 0x100, 0x120, 0x140, 0x160 */ 607 u8 res_104[0x120-0x104]; 608 } lnpssr[4]; /* Lane A, B, C, D */ 609 u8 res_180[0x200-0x180]; 610 u32 srdspccr0; /* 0x200 Protocol Configuration 0 */ 611 u32 srdspccr1; /* 0x204 Protocol Configuration 1 */ 612 u32 srdspccr2; /* 0x208 Protocol Configuration 2 */ 613 u32 srdspccr3; /* 0x20c Protocol Configuration 3 */ 614 u32 srdspccr4; /* 0x210 Protocol Configuration 4 */ 615 u32 srdspccr5; /* 0x214 Protocol Configuration 5 */ 616 u32 srdspccr6; /* 0x218 Protocol Configuration 6 */ 617 u32 srdspccr7; /* 0x21c Protocol Configuration 7 */ 618 u32 srdspccr8; /* 0x220 Protocol Configuration 8 */ 619 u32 srdspccr9; /* 0x224 Protocol Configuration 9 */ 620 u32 srdspccra; /* 0x228 Protocol Configuration A */ 621 u32 srdspccrb; /* 0x22c Protocol Configuration B */ 622 u8 res_230[0x800-0x230]; 623 struct { 624 u32 gcr0; /* 0x800 General Control Register 0 */ 625 u32 gcr1; /* 0x804 General Control Register 1 */ 626 u32 gcr2; /* 0x808 General Control Register 2 */ 627 u32 sscr0; 628 u32 recr0; /* 0x810 Receive Equalization Control */ 629 u32 recr1; 630 u32 tecr0; /* 0x818 Transmit Equalization Control */ 631 u32 sscr1; 632 u32 ttlcr0; /* 0x820 Transition Tracking Loop Ctrl 0 */ 633 u8 res_824[0x83c-0x824]; 634 u32 tcsr3; 635 } lane[4]; /* Lane A, B, C, D */ 636 u8 res_900[0x1000-0x900]; /* from 0x900 to 0xfff */ 637 struct { 638 u32 srdspexcr0; /* 0x1000, 0x1040, 0x1080 */ 639 u8 res_1004[0x1040-0x1004]; 640 } pcie[3]; 641 u8 res_10c0[0x1800-0x10c0]; 642 struct { 643 u8 res_1800[0x1804-0x1800]; 644 u32 srdssgmiicr1; /* 0x1804 SGMII Protocol Control 1 */ 645 u8 res_1808[0x180c-0x1808]; 646 u32 srdssgmiicr3; /* 0x180c SGMII Protocol Control 3 */ 647 } sgmii[4]; /* Lane A, B, C, D */ 648 u8 res_1840[0x1880-0x1840]; 649 struct { 650 u8 res_1880[0x1884-0x1880]; 651 u32 srdsqsgmiicr1; /* 0x1884 QSGMII Protocol Control 1 */ 652 u8 res_1888[0x188c-0x1888]; 653 u32 srdsqsgmiicr3; /* 0x188c QSGMII Protocol Control 3 */ 654 } qsgmii[2]; /* Lane A, B */ 655 u8 res_18a0[0x1980-0x18a0]; 656 struct { 657 u8 res_1980[0x1984-0x1980]; 658 u32 srdsxficr1; /* 0x1984 XFI Protocol Control 1 */ 659 u8 res_1988[0x198c-0x1988]; 660 u32 srdsxficr3; /* 0x198c XFI Protocol Control 3 */ 661 } xfi[2]; /* Lane A, B */ 662 u8 res_19a0[0x2000-0x19a0]; /* from 0x19a0 to 0x1fff */ 663 }; 664 665 struct ccsr_gpio { 666 u32 gpdir; 667 u32 gpodr; 668 u32 gpdat; 669 u32 gpier; 670 u32 gpimr; 671 u32 gpicr; 672 u32 gpibe; 673 }; 674 675 /* MMU 500 */ 676 #define SMMU_SCR0 (SMMU_BASE + 0x0) 677 #define SMMU_SCR1 (SMMU_BASE + 0x4) 678 #define SMMU_SCR2 (SMMU_BASE + 0x8) 679 #define SMMU_SACR (SMMU_BASE + 0x10) 680 #define SMMU_IDR0 (SMMU_BASE + 0x20) 681 #define SMMU_IDR1 (SMMU_BASE + 0x24) 682 683 #define SMMU_NSCR0 (SMMU_BASE + 0x400) 684 #define SMMU_NSCR2 (SMMU_BASE + 0x408) 685 #define SMMU_NSACR (SMMU_BASE + 0x410) 686 687 #define SCR0_CLIENTPD_MASK 0x00000001 688 #define SCR0_USFCFG_MASK 0x00000400 689 690 #ifdef CONFIG_TFABOOT 691 #define RCW_SRC_MASK (0xFF800000) 692 #define RCW_SRC_BIT 23 693 694 /* RCW SRC NAND */ 695 #define RCW_SRC_NAND_MASK (0x100) 696 #define RCW_SRC_NAND_VAL (0x100) 697 #define NAND_RESERVED_MASK (0xFC) 698 #define NAND_RESERVED_1 (0x0) 699 #define NAND_RESERVED_2 (0x80) 700 701 /* RCW SRC NOR */ 702 #define RCW_SRC_NOR_MASK (0x1F0) 703 #define NOR_8B_VAL (0x10) 704 #define NOR_16B_VAL (0x20) 705 #define SD_VAL (0x40) 706 #define QSPI_VAL1 (0x44) 707 #define QSPI_VAL2 (0x45) 708 #endif 709 710 uint get_svr(void); 711 712 #endif /* __ARCH_FSL_LSCH2_IMMAP_H__*/ 713