1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * (C) Copyright 2010-2015
4 * NVIDIA Corporation <www.nvidia.com>
5 */
6
7 /* Tegra114 Clock control functions */
8
9 #include <common.h>
10 #include <init.h>
11 #include <log.h>
12 #include <asm/io.h>
13 #include <asm/arch/clock.h>
14 #include <asm/arch/sysctr.h>
15 #include <asm/arch/tegra.h>
16 #include <asm/arch-tegra/clk_rst.h>
17 #include <asm/arch-tegra/timer.h>
18 #include <div64.h>
19 #include <fdtdec.h>
20 #include <linux/delay.h>
21
22 /*
23 * Clock types that we can use as a source. The Tegra114 has muxes for the
24 * peripheral clocks, and in most cases there are four options for the clock
25 * source. This gives us a clock 'type' and exploits what commonality exists
26 * in the device.
27 *
28 * Letters are obvious, except for T which means CLK_M, and S which means the
29 * clock derived from 32KHz. Beware that CLK_M (also called OSC in the
30 * datasheet) and PLL_M are different things. The former is the basic
31 * clock supplied to the SOC from an external oscillator. The latter is the
32 * memory clock PLL.
33 *
34 * See definitions in clock_id in the header file.
35 */
36 enum clock_type_id {
37 CLOCK_TYPE_AXPT, /* PLL_A, PLL_X, PLL_P, CLK_M */
38 CLOCK_TYPE_MCPA, /* and so on */
39 CLOCK_TYPE_MCPT,
40 CLOCK_TYPE_PCM,
41 CLOCK_TYPE_PCMT,
42 CLOCK_TYPE_PCMT16,
43 CLOCK_TYPE_PDCT,
44 CLOCK_TYPE_ACPT,
45 CLOCK_TYPE_ASPTE,
46 CLOCK_TYPE_PMDACD2T,
47 CLOCK_TYPE_PCST,
48
49 CLOCK_TYPE_COUNT,
50 CLOCK_TYPE_NONE = -1, /* invalid clock type */
51 };
52
53 enum {
54 CLOCK_MAX_MUX = 8 /* number of source options for each clock */
55 };
56
57 /*
58 * Clock source mux for each clock type. This just converts our enum into
59 * a list of mux sources for use by the code.
60 *
61 * Note:
62 * The extra column in each clock source array is used to store the mask
63 * bits in its register for the source.
64 */
65 #define CLK(x) CLOCK_ID_ ## x
66 static enum clock_id clock_source[CLOCK_TYPE_COUNT][CLOCK_MAX_MUX+1] = {
67 { CLK(AUDIO), CLK(XCPU), CLK(PERIPH), CLK(OSC),
68 CLK(NONE), CLK(NONE), CLK(NONE), CLK(NONE),
69 MASK_BITS_31_30},
70 { CLK(MEMORY), CLK(CGENERAL), CLK(PERIPH), CLK(AUDIO),
71 CLK(NONE), CLK(NONE), CLK(NONE), CLK(NONE),
72 MASK_BITS_31_30},
73 { CLK(MEMORY), CLK(CGENERAL), CLK(PERIPH), CLK(OSC),
74 CLK(NONE), CLK(NONE), CLK(NONE), CLK(NONE),
75 MASK_BITS_31_30},
76 { CLK(PERIPH), CLK(CGENERAL), CLK(MEMORY), CLK(NONE),
77 CLK(NONE), CLK(NONE), CLK(NONE), CLK(NONE),
78 MASK_BITS_31_30},
79 { CLK(PERIPH), CLK(CGENERAL), CLK(MEMORY), CLK(OSC),
80 CLK(NONE), CLK(NONE), CLK(NONE), CLK(NONE),
81 MASK_BITS_31_30},
82 { CLK(PERIPH), CLK(CGENERAL), CLK(MEMORY), CLK(OSC),
83 CLK(NONE), CLK(NONE), CLK(NONE), CLK(NONE),
84 MASK_BITS_31_30},
85 { CLK(PERIPH), CLK(DISPLAY), CLK(CGENERAL), CLK(OSC),
86 CLK(NONE), CLK(NONE), CLK(NONE), CLK(NONE),
87 MASK_BITS_31_30},
88 { CLK(AUDIO), CLK(CGENERAL), CLK(PERIPH), CLK(OSC),
89 CLK(NONE), CLK(NONE), CLK(NONE), CLK(NONE),
90 MASK_BITS_31_30},
91 { CLK(AUDIO), CLK(SFROM32KHZ), CLK(PERIPH), CLK(OSC),
92 CLK(EPCI), CLK(NONE), CLK(NONE), CLK(NONE),
93 MASK_BITS_31_29},
94 { CLK(PERIPH), CLK(MEMORY), CLK(DISPLAY), CLK(AUDIO),
95 CLK(CGENERAL), CLK(DISPLAY2), CLK(OSC), CLK(NONE),
96 MASK_BITS_31_29},
97 { CLK(PERIPH), CLK(CGENERAL), CLK(SFROM32KHZ), CLK(OSC),
98 CLK(NONE), CLK(NONE), CLK(NONE), CLK(NONE),
99 MASK_BITS_31_28}
100 };
101
102 /*
103 * Clock type for each peripheral clock source. We put the name in each
104 * record just so it is easy to match things up
105 */
106 #define TYPE(name, type) type
107 static enum clock_type_id clock_periph_type[PERIPHC_COUNT] = {
108 /* 0x00 */
109 TYPE(PERIPHC_I2S1, CLOCK_TYPE_AXPT),
110 TYPE(PERIPHC_I2S2, CLOCK_TYPE_AXPT),
111 TYPE(PERIPHC_SPDIF_OUT, CLOCK_TYPE_AXPT),
112 TYPE(PERIPHC_SPDIF_IN, CLOCK_TYPE_PCM),
113 TYPE(PERIPHC_PWM, CLOCK_TYPE_PCST), /* only PWM uses b29:28 */
114 TYPE(PERIPHC_NONE, CLOCK_TYPE_NONE),
115 TYPE(PERIPHC_SBC2, CLOCK_TYPE_PCMT),
116 TYPE(PERIPHC_SBC3, CLOCK_TYPE_PCMT),
117
118 /* 0x08 */
119 TYPE(PERIPHC_NONE, CLOCK_TYPE_NONE),
120 TYPE(PERIPHC_I2C1, CLOCK_TYPE_PCMT16),
121 TYPE(PERIPHC_I2C5, CLOCK_TYPE_PCMT16),
122 TYPE(PERIPHC_NONE, CLOCK_TYPE_NONE),
123 TYPE(PERIPHC_NONE, CLOCK_TYPE_NONE),
124 TYPE(PERIPHC_SBC1, CLOCK_TYPE_PCMT),
125 TYPE(PERIPHC_DISP1, CLOCK_TYPE_PMDACD2T),
126 TYPE(PERIPHC_DISP2, CLOCK_TYPE_PMDACD2T),
127
128 /* 0x10 */
129 TYPE(PERIPHC_CVE, CLOCK_TYPE_PDCT),
130 TYPE(PERIPHC_NONE, CLOCK_TYPE_NONE),
131 TYPE(PERIPHC_VI, CLOCK_TYPE_MCPA),
132 TYPE(PERIPHC_NONE, CLOCK_TYPE_NONE),
133 TYPE(PERIPHC_SDMMC1, CLOCK_TYPE_PCMT),
134 TYPE(PERIPHC_SDMMC2, CLOCK_TYPE_PCMT),
135 TYPE(PERIPHC_G3D, CLOCK_TYPE_MCPA),
136 TYPE(PERIPHC_G2D, CLOCK_TYPE_MCPA),
137
138 /* 0x18 */
139 TYPE(PERIPHC_NDFLASH, CLOCK_TYPE_PCMT),
140 TYPE(PERIPHC_SDMMC4, CLOCK_TYPE_PCMT),
141 TYPE(PERIPHC_VFIR, CLOCK_TYPE_PCMT),
142 TYPE(PERIPHC_EPP, CLOCK_TYPE_MCPA),
143 TYPE(PERIPHC_MPE, CLOCK_TYPE_MCPA),
144 TYPE(PERIPHC_MIPI, CLOCK_TYPE_PCMT), /* MIPI base-band HSI */
145 TYPE(PERIPHC_UART1, CLOCK_TYPE_PCMT),
146 TYPE(PERIPHC_UART2, CLOCK_TYPE_PCMT),
147
148 /* 0x20 */
149 TYPE(PERIPHC_HOST1X, CLOCK_TYPE_MCPA),
150 TYPE(PERIPHC_NONE, CLOCK_TYPE_NONE),
151 TYPE(PERIPHC_TVO, CLOCK_TYPE_PDCT),
152 TYPE(PERIPHC_HDMI, CLOCK_TYPE_PMDACD2T),
153 TYPE(PERIPHC_NONE, CLOCK_TYPE_NONE),
154 TYPE(PERIPHC_TVDAC, CLOCK_TYPE_PDCT),
155 TYPE(PERIPHC_I2C2, CLOCK_TYPE_PCMT16),
156 TYPE(PERIPHC_EMC, CLOCK_TYPE_MCPT),
157
158 /* 0x28 */
159 TYPE(PERIPHC_UART3, CLOCK_TYPE_PCMT),
160 TYPE(PERIPHC_NONE, CLOCK_TYPE_NONE),
161 TYPE(PERIPHC_VI, CLOCK_TYPE_MCPA),
162 TYPE(PERIPHC_NONE, CLOCK_TYPE_NONE),
163 TYPE(PERIPHC_NONE, CLOCK_TYPE_NONE),
164 TYPE(PERIPHC_SBC4, CLOCK_TYPE_PCMT),
165 TYPE(PERIPHC_I2C3, CLOCK_TYPE_PCMT16),
166 TYPE(PERIPHC_SDMMC3, CLOCK_TYPE_PCMT),
167
168 /* 0x30 */
169 TYPE(PERIPHC_UART4, CLOCK_TYPE_PCMT),
170 TYPE(PERIPHC_UART5, CLOCK_TYPE_PCMT),
171 TYPE(PERIPHC_VDE, CLOCK_TYPE_PCMT),
172 TYPE(PERIPHC_OWR, CLOCK_TYPE_PCMT),
173 TYPE(PERIPHC_NOR, CLOCK_TYPE_PCMT),
174 TYPE(PERIPHC_CSITE, CLOCK_TYPE_PCMT),
175 TYPE(PERIPHC_I2S0, CLOCK_TYPE_AXPT),
176 TYPE(PERIPHC_NONE, CLOCK_TYPE_NONE),
177
178 /* 0x38h */ /* Jumps to reg offset 0x3B0h */
179 TYPE(PERIPHC_G3D2, CLOCK_TYPE_MCPA),
180 TYPE(PERIPHC_MSELECT, CLOCK_TYPE_PCMT),
181 TYPE(PERIPHC_TSENSOR, CLOCK_TYPE_PCST), /* s/b PCTS */
182 TYPE(PERIPHC_I2S3, CLOCK_TYPE_AXPT),
183 TYPE(PERIPHC_I2S4, CLOCK_TYPE_AXPT),
184 TYPE(PERIPHC_I2C4, CLOCK_TYPE_PCMT16),
185 TYPE(PERIPHC_SBC5, CLOCK_TYPE_PCMT),
186 TYPE(PERIPHC_SBC6, CLOCK_TYPE_PCMT),
187
188 /* 0x40 */
189 TYPE(PERIPHC_AUDIO, CLOCK_TYPE_ACPT),
190 TYPE(PERIPHC_NONE, CLOCK_TYPE_NONE),
191 TYPE(PERIPHC_DAM0, CLOCK_TYPE_ACPT),
192 TYPE(PERIPHC_DAM1, CLOCK_TYPE_ACPT),
193 TYPE(PERIPHC_DAM2, CLOCK_TYPE_ACPT),
194 TYPE(PERIPHC_HDA2CODEC2X, CLOCK_TYPE_PCMT),
195 TYPE(PERIPHC_ACTMON, CLOCK_TYPE_PCST), /* MASK 31:30 */
196 TYPE(PERIPHC_EXTPERIPH1, CLOCK_TYPE_ASPTE),
197
198 /* 0x48 */
199 TYPE(PERIPHC_EXTPERIPH2, CLOCK_TYPE_ASPTE),
200 TYPE(PERIPHC_EXTPERIPH3, CLOCK_TYPE_ASPTE),
201 TYPE(PERIPHC_NANDSPEED, CLOCK_TYPE_PCMT),
202 TYPE(PERIPHC_I2CSLOW, CLOCK_TYPE_PCST), /* MASK 31:30 */
203 TYPE(PERIPHC_SYS, CLOCK_TYPE_NONE),
204 TYPE(PERIPHC_SPEEDO, CLOCK_TYPE_PCMT),
205 TYPE(PERIPHC_NONE, CLOCK_TYPE_NONE),
206 TYPE(PERIPHC_NONE, CLOCK_TYPE_NONE),
207
208 /* 0x50 */
209 TYPE(PERIPHC_NONE, CLOCK_TYPE_NONE),
210 TYPE(PERIPHC_NONE, CLOCK_TYPE_NONE),
211 TYPE(PERIPHC_NONE, CLOCK_TYPE_NONE),
212 TYPE(PERIPHC_NONE, CLOCK_TYPE_NONE),
213 TYPE(PERIPHC_SATAOOB, CLOCK_TYPE_PCMT), /* offset 0x420h */
214 TYPE(PERIPHC_SATA, CLOCK_TYPE_PCMT),
215 TYPE(PERIPHC_HDA, CLOCK_TYPE_PCMT),
216 };
217
218 /*
219 * This array translates a periph_id to a periphc_internal_id
220 *
221 * Not present/matched up:
222 * uint vi_sensor; _VI_SENSOR_0, 0x1A8
223 * SPDIF - which is both 0x08 and 0x0c
224 *
225 */
226 #define NONE(name) (-1)
227 #define OFFSET(name, value) PERIPHC_ ## name
228 static s8 periph_id_to_internal_id[PERIPH_ID_COUNT] = {
229 /* Low word: 31:0 */
230 NONE(CPU),
231 NONE(COP),
232 NONE(TRIGSYS),
233 NONE(RESERVED3),
234 NONE(RTC),
235 NONE(TMR),
236 PERIPHC_UART1,
237 PERIPHC_UART2, /* and vfir 0x68 */
238
239 /* 8 */
240 NONE(GPIO),
241 PERIPHC_SDMMC2,
242 NONE(SPDIF), /* 0x08 and 0x0c, unclear which to use */
243 PERIPHC_I2S1,
244 PERIPHC_I2C1,
245 PERIPHC_NDFLASH,
246 PERIPHC_SDMMC1,
247 PERIPHC_SDMMC4,
248
249 /* 16 */
250 NONE(RESERVED16),
251 PERIPHC_PWM,
252 PERIPHC_I2S2,
253 PERIPHC_EPP,
254 PERIPHC_VI,
255 PERIPHC_G2D,
256 NONE(USBD),
257 NONE(ISP),
258
259 /* 24 */
260 PERIPHC_G3D,
261 NONE(RESERVED25),
262 PERIPHC_DISP2,
263 PERIPHC_DISP1,
264 PERIPHC_HOST1X,
265 NONE(VCP),
266 PERIPHC_I2S0,
267 NONE(CACHE2),
268
269 /* Middle word: 63:32 */
270 NONE(MEM),
271 NONE(AHBDMA),
272 NONE(APBDMA),
273 NONE(RESERVED35),
274 NONE(RESERVED36),
275 NONE(STAT_MON),
276 NONE(RESERVED38),
277 NONE(RESERVED39),
278
279 /* 40 */
280 NONE(KFUSE),
281 NONE(SBC1), /* SBC1, 0x34, is this SPI1? */
282 PERIPHC_NOR,
283 NONE(RESERVED43),
284 PERIPHC_SBC2,
285 NONE(RESERVED45),
286 PERIPHC_SBC3,
287 PERIPHC_I2C5,
288
289 /* 48 */
290 NONE(DSI),
291 PERIPHC_TVO, /* also CVE 0x40 */
292 PERIPHC_MIPI,
293 PERIPHC_HDMI,
294 NONE(CSI),
295 PERIPHC_TVDAC,
296 PERIPHC_I2C2,
297 PERIPHC_UART3,
298
299 /* 56 */
300 NONE(RESERVED56),
301 PERIPHC_EMC,
302 NONE(USB2),
303 NONE(USB3),
304 PERIPHC_MPE,
305 PERIPHC_VDE,
306 NONE(BSEA),
307 NONE(BSEV),
308
309 /* Upper word 95:64 */
310 PERIPHC_SPEEDO,
311 PERIPHC_UART4,
312 PERIPHC_UART5,
313 PERIPHC_I2C3,
314 PERIPHC_SBC4,
315 PERIPHC_SDMMC3,
316 NONE(PCIE),
317 PERIPHC_OWR,
318
319 /* 72 */
320 NONE(AFI),
321 PERIPHC_CSITE,
322 NONE(PCIEXCLK),
323 NONE(AVPUCQ),
324 NONE(RESERVED76),
325 NONE(RESERVED77),
326 NONE(RESERVED78),
327 NONE(DTV),
328
329 /* 80 */
330 PERIPHC_NANDSPEED,
331 PERIPHC_I2CSLOW,
332 NONE(DSIB),
333 NONE(RESERVED83),
334 NONE(IRAMA),
335 NONE(IRAMB),
336 NONE(IRAMC),
337 NONE(IRAMD),
338
339 /* 88 */
340 NONE(CRAM2),
341 NONE(RESERVED89),
342 NONE(MDOUBLER),
343 NONE(RESERVED91),
344 NONE(SUSOUT),
345 NONE(RESERVED93),
346 NONE(RESERVED94),
347 NONE(RESERVED95),
348
349 /* V word: 31:0 */
350 NONE(CPUG),
351 NONE(CPULP),
352 PERIPHC_G3D2,
353 PERIPHC_MSELECT,
354 PERIPHC_TSENSOR,
355 PERIPHC_I2S3,
356 PERIPHC_I2S4,
357 PERIPHC_I2C4,
358
359 /* 08 */
360 PERIPHC_SBC5,
361 PERIPHC_SBC6,
362 PERIPHC_AUDIO,
363 NONE(APBIF),
364 PERIPHC_DAM0,
365 PERIPHC_DAM1,
366 PERIPHC_DAM2,
367 PERIPHC_HDA2CODEC2X,
368
369 /* 16 */
370 NONE(ATOMICS),
371 NONE(RESERVED17),
372 NONE(RESERVED18),
373 NONE(RESERVED19),
374 NONE(RESERVED20),
375 NONE(RESERVED21),
376 NONE(RESERVED22),
377 PERIPHC_ACTMON,
378
379 /* 24 */
380 NONE(RESERVED24),
381 NONE(RESERVED25),
382 NONE(RESERVED26),
383 NONE(RESERVED27),
384 PERIPHC_SATA,
385 PERIPHC_HDA,
386 NONE(RESERVED30),
387 NONE(RESERVED31),
388
389 /* W word: 31:0 */
390 NONE(HDA2HDMICODEC),
391 NONE(RESERVED1_SATACOLD),
392 NONE(RESERVED2_PCIERX0),
393 NONE(RESERVED3_PCIERX1),
394 NONE(RESERVED4_PCIERX2),
395 NONE(RESERVED5_PCIERX3),
396 NONE(RESERVED6_PCIERX4),
397 NONE(RESERVED7_PCIERX5),
398
399 /* 40 */
400 NONE(CEC),
401 NONE(PCIE2_IOBIST),
402 NONE(EMC_IOBIST),
403 NONE(HDMI_IOBIST),
404 NONE(SATA_IOBIST),
405 NONE(MIPI_IOBIST),
406 NONE(EMC1_IOBIST),
407 NONE(XUSB),
408
409 /* 48 */
410 NONE(CILAB),
411 NONE(CILCD),
412 NONE(CILE),
413 NONE(DSIA_LP),
414 NONE(DSIB_LP),
415 NONE(RESERVED21_ENTROPY),
416 NONE(RESERVED22_W),
417 NONE(RESERVED23_W),
418
419 /* 56 */
420 NONE(RESERVED24_W),
421 NONE(AMX0),
422 NONE(ADX0),
423 NONE(DVFS),
424 NONE(XUSB_SS),
425 NONE(EMC_DLL),
426 NONE(MC1),
427 NONE(EMC1),
428 };
429
430 /*
431 * PLL divider shift/mask tables for all PLL IDs.
432 */
433 struct clk_pll_info tegra_pll_info_table[CLOCK_ID_PLL_COUNT] = {
434 /*
435 * T114: some deviations from T2x/T30.
436 * NOTE: If kcp_mask/kvco_mask == 0, they're not used in that PLL (PLLX, etc.)
437 * If lock_ena or lock_det are >31, they're not used in that PLL.
438 */
439
440 { .m_shift = 0, .m_mask = 0xFF, .n_shift = 8, .n_mask = 0xFF, .p_shift = 20, .p_mask = 0x0F,
441 .lock_ena = 24, .lock_det = 27, .kcp_shift = 28, .kcp_mask = 3, .kvco_shift = 27, .kvco_mask = 1 }, /* PLLC */
442 { .m_shift = 0, .m_mask = 0xFF, .n_shift = 8, .n_mask = 0xFF, .p_shift = 0, .p_mask = 0,
443 .lock_ena = 0, .lock_det = 27, .kcp_shift = 1, .kcp_mask = 3, .kvco_shift = 0, .kvco_mask = 1 }, /* PLLM */
444 { .m_shift = 0, .m_mask = 0x1F, .n_shift = 8, .n_mask = 0x3FF, .p_shift = 20, .p_mask = 0x07,
445 .lock_ena = 18, .lock_det = 27, .kcp_shift = 8, .kcp_mask = 0xF, .kvco_shift = 4, .kvco_mask = 0xF }, /* PLLP */
446 { .m_shift = 0, .m_mask = 0x1F, .n_shift = 8, .n_mask = 0x3FF, .p_shift = 20, .p_mask = 0x07,
447 .lock_ena = 18, .lock_det = 27, .kcp_shift = 8, .kcp_mask = 0xF, .kvco_shift = 4, .kvco_mask = 0xF }, /* PLLA */
448 { .m_shift = 0, .m_mask = 0x1F, .n_shift = 8, .n_mask = 0x3FF, .p_shift = 20, .p_mask = 0x01,
449 .lock_ena = 22, .lock_det = 27, .kcp_shift = 8, .kcp_mask = 0xF, .kvco_shift = 4, .kvco_mask = 0xF }, /* PLLU */
450 { .m_shift = 0, .m_mask = 0x1F, .n_shift = 8, .n_mask = 0x3FF, .p_shift = 20, .p_mask = 0x07,
451 .lock_ena = 22, .lock_det = 27, .kcp_shift = 8, .kcp_mask = 0xF, .kvco_shift = 4, .kvco_mask = 0xF }, /* PLLD */
452 { .m_shift = 0, .m_mask = 0xFF, .n_shift = 8, .n_mask = 0xFF, .p_shift = 20, .p_mask = 0x0F,
453 .lock_ena = 18, .lock_det = 27, .kcp_shift = 0, .kcp_mask = 0, .kvco_shift = 0, .kvco_mask = 0 }, /* PLLX */
454 { .m_shift = 0, .m_mask = 0xFF, .n_shift = 8, .n_mask = 0xFF, .p_shift = 0, .p_mask = 0,
455 .lock_ena = 9, .lock_det = 11, .kcp_shift = 6, .kcp_mask = 3, .kvco_shift = 0, .kvco_mask = 1 }, /* PLLE */
456 { .m_shift = 0, .m_mask = 0x0F, .n_shift = 8, .n_mask = 0x3FF, .p_shift = 20, .p_mask = 0x07,
457 .lock_ena = 18, .lock_det = 27, .kcp_shift = 8, .kcp_mask = 0xF, .kvco_shift = 4, .kvco_mask = 0xF }, /* PLLS (RESERVED) */
458 };
459
460 /*
461 * Get the oscillator frequency, from the corresponding hardware configuration
462 * field. Note that T30/T114 support 3 new higher freqs, but we map back
463 * to the old T20 freqs. Support for the higher oscillators is TBD.
464 */
clock_get_osc_freq(void)465 enum clock_osc_freq clock_get_osc_freq(void)
466 {
467 struct clk_rst_ctlr *clkrst =
468 (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
469 u32 reg;
470
471 reg = readl(&clkrst->crc_osc_ctrl);
472 reg = (reg & OSC_FREQ_MASK) >> OSC_FREQ_SHIFT;
473
474 if (reg & 1) /* one of the newer freqs */
475 printf("Warning: OSC_FREQ is unsupported! (%d)\n", reg);
476
477 return reg >> 2; /* Map to most common (T20) freqs */
478 }
479
480 /* Returns a pointer to the clock source register for a peripheral */
get_periph_source_reg(enum periph_id periph_id)481 u32 *get_periph_source_reg(enum periph_id periph_id)
482 {
483 struct clk_rst_ctlr *clkrst =
484 (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
485 enum periphc_internal_id internal_id;
486
487 /* Coresight is a special case */
488 if (periph_id == PERIPH_ID_CSI)
489 return &clkrst->crc_clk_src[PERIPH_ID_CSI+1];
490
491 assert(periph_id >= PERIPH_ID_FIRST && periph_id < PERIPH_ID_COUNT);
492 internal_id = periph_id_to_internal_id[periph_id];
493 assert(internal_id != -1);
494 if (internal_id >= PERIPHC_VW_FIRST) {
495 internal_id -= PERIPHC_VW_FIRST;
496 return &clkrst->crc_clk_src_vw[internal_id];
497 } else
498 return &clkrst->crc_clk_src[internal_id];
499 }
500
get_periph_clock_info(enum periph_id periph_id,int * mux_bits,int * divider_bits,int * type)501 int get_periph_clock_info(enum periph_id periph_id, int *mux_bits,
502 int *divider_bits, int *type)
503 {
504 enum periphc_internal_id internal_id;
505
506 if (!clock_periph_id_isvalid(periph_id))
507 return -1;
508
509 internal_id = periph_id_to_internal_id[periph_id];
510 if (!periphc_internal_id_isvalid(internal_id))
511 return -1;
512
513 *type = clock_periph_type[internal_id];
514 if (!clock_type_id_isvalid(*type))
515 return -1;
516
517 *mux_bits = clock_source[*type][CLOCK_MAX_MUX];
518
519 if (*type == CLOCK_TYPE_PCMT16)
520 *divider_bits = 16;
521 else
522 *divider_bits = 8;
523
524 return 0;
525 }
526
get_periph_clock_id(enum periph_id periph_id,int source)527 enum clock_id get_periph_clock_id(enum periph_id periph_id, int source)
528 {
529 enum periphc_internal_id internal_id;
530 int type;
531
532 if (!clock_periph_id_isvalid(periph_id))
533 return CLOCK_ID_NONE;
534
535 internal_id = periph_id_to_internal_id[periph_id];
536 if (!periphc_internal_id_isvalid(internal_id))
537 return CLOCK_ID_NONE;
538
539 type = clock_periph_type[internal_id];
540 if (!clock_type_id_isvalid(type))
541 return CLOCK_ID_NONE;
542
543 return clock_source[type][source];
544 }
545
546 /**
547 * Given a peripheral ID and the required source clock, this returns which
548 * value should be programmed into the source mux for that peripheral.
549 *
550 * There is special code here to handle the one source type with 5 sources.
551 *
552 * @param periph_id peripheral to start
553 * @param source PLL id of required parent clock
554 * @param mux_bits Set to number of bits in mux register: 2 or 4
555 * @param divider_bits Set to number of divider bits (8 or 16)
556 * @return mux value (0-4, or -1 if not found)
557 */
get_periph_clock_source(enum periph_id periph_id,enum clock_id parent,int * mux_bits,int * divider_bits)558 int get_periph_clock_source(enum periph_id periph_id,
559 enum clock_id parent, int *mux_bits, int *divider_bits)
560 {
561 enum clock_type_id type;
562 int mux, err;
563
564 err = get_periph_clock_info(periph_id, mux_bits, divider_bits, &type);
565 assert(!err);
566
567 for (mux = 0; mux < CLOCK_MAX_MUX; mux++)
568 if (clock_source[type][mux] == parent)
569 return mux;
570
571 /* if we get here, either us or the caller has made a mistake */
572 printf("Caller requested bad clock: periph=%d, parent=%d\n", periph_id,
573 parent);
574 return -1;
575 }
576
clock_set_enable(enum periph_id periph_id,int enable)577 void clock_set_enable(enum periph_id periph_id, int enable)
578 {
579 struct clk_rst_ctlr *clkrst =
580 (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
581 u32 *clk;
582 u32 reg;
583
584 /* Enable/disable the clock to this peripheral */
585 assert(clock_periph_id_isvalid(periph_id));
586 if ((int)periph_id < (int)PERIPH_ID_VW_FIRST)
587 clk = &clkrst->crc_clk_out_enb[PERIPH_REG(periph_id)];
588 else
589 clk = &clkrst->crc_clk_out_enb_vw[PERIPH_REG(periph_id)];
590 reg = readl(clk);
591 if (enable)
592 reg |= PERIPH_MASK(periph_id);
593 else
594 reg &= ~PERIPH_MASK(periph_id);
595 writel(reg, clk);
596 }
597
reset_set_enable(enum periph_id periph_id,int enable)598 void reset_set_enable(enum periph_id periph_id, int enable)
599 {
600 struct clk_rst_ctlr *clkrst =
601 (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
602 u32 *reset;
603 u32 reg;
604
605 /* Enable/disable reset to the peripheral */
606 assert(clock_periph_id_isvalid(periph_id));
607 if (periph_id < PERIPH_ID_VW_FIRST)
608 reset = &clkrst->crc_rst_dev[PERIPH_REG(periph_id)];
609 else
610 reset = &clkrst->crc_rst_dev_vw[PERIPH_REG(periph_id)];
611 reg = readl(reset);
612 if (enable)
613 reg |= PERIPH_MASK(periph_id);
614 else
615 reg &= ~PERIPH_MASK(periph_id);
616 writel(reg, reset);
617 }
618
619 #if CONFIG_IS_ENABLED(OF_CONTROL)
620 /*
621 * Convert a device tree clock ID to our peripheral ID. They are mostly
622 * the same but we are very cautious so we check that a valid clock ID is
623 * provided.
624 *
625 * @param clk_id Clock ID according to tegra114 device tree binding
626 * @return peripheral ID, or PERIPH_ID_NONE if the clock ID is invalid
627 */
clk_id_to_periph_id(int clk_id)628 enum periph_id clk_id_to_periph_id(int clk_id)
629 {
630 if (clk_id > PERIPH_ID_COUNT)
631 return PERIPH_ID_NONE;
632
633 switch (clk_id) {
634 case PERIPH_ID_RESERVED3:
635 case PERIPH_ID_RESERVED16:
636 case PERIPH_ID_RESERVED24:
637 case PERIPH_ID_RESERVED35:
638 case PERIPH_ID_RESERVED43:
639 case PERIPH_ID_RESERVED45:
640 case PERIPH_ID_RESERVED56:
641 case PERIPH_ID_RESERVED76:
642 case PERIPH_ID_RESERVED77:
643 case PERIPH_ID_RESERVED78:
644 case PERIPH_ID_RESERVED83:
645 case PERIPH_ID_RESERVED89:
646 case PERIPH_ID_RESERVED91:
647 case PERIPH_ID_RESERVED93:
648 case PERIPH_ID_RESERVED94:
649 case PERIPH_ID_RESERVED95:
650 return PERIPH_ID_NONE;
651 default:
652 return clk_id;
653 }
654 }
655 #endif /* CONFIG_IS_ENABLED(OF_CONTROL) */
656
clock_early_init(void)657 void clock_early_init(void)
658 {
659 struct clk_rst_ctlr *clkrst =
660 (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
661 struct clk_pll_info *pllinfo;
662 u32 data;
663
664 tegra30_set_up_pllp();
665
666 /* clear IDDQ before accessing any other PLLC registers */
667 pllinfo = &tegra_pll_info_table[CLOCK_ID_CGENERAL];
668 clrbits_le32(&clkrst->crc_pll[CLOCK_ID_CGENERAL].pll_misc, PLLC_IDDQ);
669 udelay(2);
670
671 /*
672 * PLLC output frequency set to 600Mhz
673 * PLLD output frequency set to 925Mhz
674 */
675 switch (clock_get_osc_freq()) {
676 case CLOCK_OSC_FREQ_12_0: /* OSC is 12Mhz */
677 clock_set_rate(CLOCK_ID_CGENERAL, 600, 12, 0, 8);
678 clock_set_rate(CLOCK_ID_DISPLAY, 925, 12, 0, 12);
679 break;
680
681 case CLOCK_OSC_FREQ_26_0: /* OSC is 26Mhz */
682 clock_set_rate(CLOCK_ID_CGENERAL, 600, 26, 0, 8);
683 clock_set_rate(CLOCK_ID_DISPLAY, 925, 26, 0, 12);
684 break;
685
686 case CLOCK_OSC_FREQ_13_0: /* OSC is 13Mhz */
687 clock_set_rate(CLOCK_ID_CGENERAL, 600, 13, 0, 8);
688 clock_set_rate(CLOCK_ID_DISPLAY, 925, 13, 0, 12);
689 break;
690 case CLOCK_OSC_FREQ_19_2:
691 default:
692 /*
693 * These are not supported. It is too early to print a
694 * message and the UART likely won't work anyway due to the
695 * oscillator being wrong.
696 */
697 break;
698 }
699
700 /* PLLC_MISC2: Set dynramp_stepA/B. MISC2 maps to pll_out[1] */
701 writel(0x00561600, &clkrst->crc_pll[CLOCK_ID_CGENERAL].pll_out[1]);
702
703 /* PLLC_MISC: Set LOCK_ENABLE */
704 pllinfo = &tegra_pll_info_table[CLOCK_ID_CGENERAL];
705 setbits_le32(&clkrst->crc_pll[CLOCK_ID_CGENERAL].pll_misc, (1 << pllinfo->lock_ena));
706 udelay(2);
707
708 /* PLLD_MISC: Set CLKENABLE, CPCON 12, LFCON 1, and enable lock */
709 pllinfo = &tegra_pll_info_table[CLOCK_ID_DISPLAY];
710 data = (12 << pllinfo->kcp_shift) | (1 << pllinfo->kvco_shift);
711 data |= (1 << PLLD_CLKENABLE) | (1 << pllinfo->lock_ena);
712 writel(data, &clkrst->crc_pll[CLOCK_ID_DISPLAY].pll_misc);
713 udelay(2);
714 }
715
arch_timer_init(void)716 void arch_timer_init(void)
717 {
718 struct sysctr_ctlr *sysctr = (struct sysctr_ctlr *)NV_PA_TSC_BASE;
719 u32 freq, val;
720
721 freq = clock_get_rate(CLOCK_ID_CLK_M);
722 debug("%s: clk_m freq is %dHz [0x%08X]\n", __func__, freq, freq);
723
724 /* ARM CNTFRQ */
725 asm("mcr p15, 0, %0, c14, c0, 0\n" : : "r" (freq));
726
727 /* Only T114 has the System Counter regs */
728 debug("%s: setting CNTFID0 to 0x%08X\n", __func__, freq);
729 writel(freq, &sysctr->cntfid0);
730
731 val = readl(&sysctr->cntcr);
732 val |= TSC_CNTCR_ENABLE | TSC_CNTCR_HDBG;
733 writel(val, &sysctr->cntcr);
734 debug("%s: TSC CNTCR = 0x%08X\n", __func__, val);
735 }
736
737 struct periph_clk_init periph_clk_init_table[] = {
738 { PERIPH_ID_SBC1, CLOCK_ID_PERIPH },
739 { PERIPH_ID_SBC2, CLOCK_ID_PERIPH },
740 { PERIPH_ID_SBC3, CLOCK_ID_PERIPH },
741 { PERIPH_ID_SBC4, CLOCK_ID_PERIPH },
742 { PERIPH_ID_SBC5, CLOCK_ID_PERIPH },
743 { PERIPH_ID_SBC6, CLOCK_ID_PERIPH },
744 { PERIPH_ID_HOST1X, CLOCK_ID_PERIPH },
745 { PERIPH_ID_DISP1, CLOCK_ID_CGENERAL },
746 { PERIPH_ID_NDFLASH, CLOCK_ID_PERIPH },
747 { PERIPH_ID_SDMMC1, CLOCK_ID_PERIPH },
748 { PERIPH_ID_SDMMC2, CLOCK_ID_PERIPH },
749 { PERIPH_ID_SDMMC3, CLOCK_ID_PERIPH },
750 { PERIPH_ID_SDMMC4, CLOCK_ID_PERIPH },
751 { PERIPH_ID_PWM, CLOCK_ID_SFROM32KHZ },
752 { PERIPH_ID_I2C1, CLOCK_ID_PERIPH },
753 { PERIPH_ID_I2C2, CLOCK_ID_PERIPH },
754 { PERIPH_ID_I2C3, CLOCK_ID_PERIPH },
755 { PERIPH_ID_I2C4, CLOCK_ID_PERIPH },
756 { PERIPH_ID_I2C5, CLOCK_ID_PERIPH },
757 { -1, },
758 };
759