1/* SPDX-License-Identifier: GPL-2.0+ */
2/*
3 * Copyright (C) 2016 Intel Corp.
4 * (Written by Lance Zhao <lijian.zhao@intel.com> for Intel Corp.)
5 */
6
7#ifndef _SOC_INT_DEFINE_ASL_
8#define _SOC_INT_DEFINE_ASL_
9
10#define SDCARD_INT	3	/* Need to be shared by PMC and SCC only*/
11#define UART0_INT	4	/* Need to be shared by PMC and SCC only*/
12#define UART1_INT	5	/* Need to be shared by PMC and SCC only*/
13#define UART2_INT	6	/* Need to be shared by PMC and SCC only*/
14#define UART3_INT	7	/* Need to be shared by PMC and SCC only*/
15#define XDCI_INT	13	/* Need to be shared by PMC and SCC only*/
16#define GPIO_BANK_INT	14
17#define NPK_INT		16
18#define PIRQA_INT	16
19#define PIRQB_INT	17
20#define PIRQC_INT	18
21#define SATA_INT	19
22#define GEN_INT		19
23#define PIRQD_INT	19
24#define XHCI_INT	17	/* Need to be shared by PMC and SCC only*/
25#define SMBUS_INT	20	/* PIRQE */
26#define CSE_INT		20	/* PIRQE */
27#define IUNIT_INT	21	/* PIRQF */
28#define PIRQF_INT	21
29#define PIRQG_INT	22
30#define PUNIT_INT	24
31#define AUDIO_INT	25
32#define ISH_INT		26
33#define I2C0_INT	27
34#define I2C1_INT	28
35#define I2C2_INT	29
36#define I2C3_INT	30
37#define I2C4_INT	31
38#define I2C5_INT	32
39#define I2C6_INT	33
40#define I2C7_INT	34
41#define SPI0_INT	35
42#define SPI1_INT	36
43#define SPI2_INT	37
44#define UFS_INT		38
45#define EMMC_INT	39
46#define PMC_INT		40
47#define SDIO_INT	42
48#define CNVI_INT	44
49
50#endif	/* _SOC_INT_DEFINE_ASL_ */
51