1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Copyright (C) 2018 SolidRun ltd
4 */
5
6#include "armada-8040.dtsi"
7
8/ {
9	model = "ClearFog-GT-8K";
10	compatible = "solidrun,clearfog-gt-8k",
11		     "marvell,armada8040";
12
13	chosen {
14		stdout-path = "serial0:115200n8";
15	};
16
17	aliases {
18		i2c0 = &cp0_i2c0;
19		i2c1 = &cp0_i2c1;
20		spi0 = &cp1_spi1;
21	};
22
23	memory@00000000 {
24		device_type = "memory";
25		reg = <0x0 0x0 0x0 0x80000000>;
26	};
27
28	simple-bus {
29		compatible = "simple-bus";
30
31		reg_usb3h0_vbus: usb3-vbus0 {
32			compatible = "regulator-fixed";
33			pinctrl-names = "default";
34			pinctrl-0 = <&cp0_xhci_vbus_pins>;
35			regulator-name = "reg-usb3h0-vbus";
36			regulator-min-microvolt = <5000000>;
37			regulator-max-microvolt = <5000000>;
38			startup-delay-us = <300000>;
39			shutdown-delay-us = <500000>;
40			regulator-force-boot-off;
41			gpio = <&cp0_gpio1 15 GPIO_ACTIVE_LOW>; /* GPIO[47] */
42		};
43	};
44};
45
46&uart0 {
47	status = "okay";
48};
49
50&ap_pinctl {
51	/*
52	 * MPP Bus:
53	 * eMMC [0-10]
54	 * UART0 [11,19]
55	 */
56		  /* 0 1 2 3 4 5 6 7 8 9 */
57	pin-func = < 1 1 1 1 1 1 1 1 1 1
58		     1 3 0 0 0 0 0 0 0 3 >;
59};
60
61/* on-board eMMC */
62&ap_sdhci0 {
63	pinctrl-names = "default";
64	pinctrl-0 = <&ap_emmc_pins>;
65	bus-width = <8>;
66	status = "okay";
67};
68
69&cp0_pinctl {
70	/*
71	 * MPP Bus:
72	 * [0-31] = 0xff: Keep default CP0_shared_pins:
73	 * [11] CLKOUT_MPP_11 (out)
74	 * [23] LINK_RD_IN_CP2CP (in)
75	 * [25] CLKOUT_MPP_25 (out)
76	 * [29] AVS_FB_IN_CP2CP (in)
77	 * [32, 33, 34] pci0/1/2 reset
78	 * [35-38] CP0 I2C1 and I2C0
79	 * [39] GPIO reset button
80	 * [40,41] LED0 and LED1
81	 * [43] 1512 phy reset
82	 * [47] USB VBUS EN (active low)
83	 * [48] FAN PWM
84	 * [49] SFP+ present signal
85	 * [50] TPM interrupt
86	 * [51] WLAN0 disable
87	 * [52] WLAN1 disable
88	 * [53] LTE disable
89	 * [54] NFC reset
90	 * [55] Micro SD card detect
91	 * [56-61] Micro SD
92	 */
93		/*   0    1    2    3    4    5    6    7    8    9 */
94	pin-func = < 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff
95		     0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff
96		     0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff
97		     0xff 0    0    0    0    2    2    2    2    0
98		     0    0    0    0    0    0    0    0    0    0
99		     0    0    0    0    0    0    0xe  0xe  0xe  0xe
100		     0xe  0xe  0 >;
101
102	cp0_pcie_reset_pins: cp0-pcie-reset-pins {
103		marvell,pins = < 32 >;
104		marvell,function = <0>;
105	};
106
107	cp0_xhci_vbus_pins: cp0-xhci-vbus-pins {
108		marvell,pins = < 47 >;
109		marvell,function = <0>;
110	};
111
112	cp1_1g_phy_reset: cp1-1g-phy-reset {
113		marvell,pins = < 43 >;
114		marvell,function = <0>;
115	};
116};
117
118/* uSD slot */
119&cp0_sdhci0 {
120	pinctrl-names = "default";
121	pinctrl-0 = <&cp0_sdhci_pins>;
122	bus-width = <4>;
123	status = "okay";
124};
125
126&cp0_pcie0 {
127	num-lanes = <1>;
128	pinctrl-names = "default";
129	pinctrl-0 = <&cp0_pcie_reset_pins>;
130	marvell,reset-gpio = <&cp0_gpio1 0 GPIO_ACTIVE_LOW>;
131	status = "okay";
132};
133
134&cp0_i2c0 {
135	pinctrl-names = "default";
136	pinctrl-0 = <&cp0_i2c0_pins>;
137	status = "okay";
138	clock-frequency = <100000>;
139};
140
141&cp0_i2c1 {
142	pinctrl-names = "default";
143	pinctrl-0 = <&cp0_i2c1_pins>;
144	status = "okay";
145	clock-frequency = <100000>;
146};
147
148&cp0_sata0 {
149	status = "okay";
150};
151
152&cp0_comphy {
153	/*
154	 * CP0 Serdes Configuration:
155	 * Lane 0: PCIe0 (x1)
156	 * Lane 1: Not connected
157	 * Lane 2: SFI0 (10G)
158	 * Lane 3: Not connected
159	 * Lane 4: USB 3.0 host port1 (can be PCIe)
160	 * Lane 5: Not connected
161	 */
162	phy0 {
163		phy-type = <COMPHY_TYPE_PEX0>;
164	};
165	phy1 {
166		phy-type = <COMPHY_TYPE_UNCONNECTED>;
167	};
168	phy2 {
169		phy-type = <COMPHY_TYPE_SFI0>;
170	};
171	phy3 {
172		phy-type = <COMPHY_TYPE_UNCONNECTED>;
173	};
174	phy4 {
175		phy-type = <COMPHY_TYPE_USB3_HOST1>;
176	};
177	phy5 {
178		phy-type = <COMPHY_TYPE_UNCONNECTED>;
179	};
180};
181
182&cp0_ethernet {
183        pinctrl-names = "default";
184        status = "okay";
185};
186
187/* 10G SFI SFP */
188&cp0_eth0 {
189        status = "okay";
190        phy-mode = "sfi";
191};
192
193&cp1_sata0 {
194	status = "okay";
195};
196
197&cp1_usb3_0 {
198	vbus-supply = <&reg_usb3h0_vbus>;
199	status = "okay";
200};
201
202&cp1_utmi0 {
203	status = "okay";
204};
205
206&cp1_pinctl {
207	/*
208	 * MPP Bus:
209	 * [0-5] TDM
210	 * [6]   VHV Enable
211	 * [7]   CP1 SPI0 CSn1 (FXS)
212	 * [8]   CP1 SPI0 CSn0 (TPM)
213	 * [9.11]CP1 SPI0 MOSI/MISO/CLK
214	 * [13]  CP1 SPI1 MISO (TDM and SPI ROM shared)
215	 * [14]  CP1 SPI1 CS0n (64Mb SPI ROM)
216	 * [15]  CP1 SPI1 MOSI (TDM and SPI ROM shared)
217	 * [16]  CP1 SPI1 CLK (TDM and SPI ROM shared)
218	 * [24]  Topaz switch reset
219	 * [26]  Buzzer
220	 * [27]  CP1 SMI MDIO
221	 * [28]  CP1 SMI MDC
222	 * [29]  CP0 10G SFP TX Disable
223	 * [30]  WPS button
224	 * [31]  Front panel button
225	 * [32-62] = 0xff: Keep default CP1_shared_pins:
226	 */
227		/*   0    1    2    3    4    5    6    7    8    9 */
228	pin-func = < 0x4  0x4  0x4  0x4  0x4  0x4  0x0  0x4  0x4  0x4
229		     0x4  0x4  0x0  0x3  0x3  0x3  0x3  0xff 0xff 0xff
230		     0xff 0xff 0xff 0xff 0x0  0xff 0x0  0x8  0x8  0x0
231		     0x0  0x0  0x0  0xff 0xff 0xff 0xff 0xff 0xff 0xff
232		     0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff
233		     0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff
234		     0xff 0xff 0xff>;
235};
236
237&cp1_spi1 {
238	pinctrl-names = "default";
239	pinctrl-0 = <&cp1_spi1_pins>;
240	status = "okay";
241
242	spi-flash@0 {
243		compatible = "jedec,spi-nor";
244		reg = <0>;
245		spi-max-frequency = <10000000>;
246
247		partitions {
248			compatible = "fixed-partitions";
249			#address-cells = <1>;
250			#size-cells = <1>;
251
252			partition@0 {
253				label = "U-Boot";
254				reg = <0 0x200000>;
255			};
256			partition@200000 {
257				label = "Filesystem";
258				reg = <0x200000 0xce0000>;
259			};
260		};
261	};
262};
263
264&cp1_comphy {
265	/*
266	 * CP1 Serdes Configuration:
267	 * Lane 0: SATA 1 (RX swapped). Can be PCIe0
268	 * Lane 1: Not used
269	 * Lane 2: USB HOST 0
270	 * Lane 3: SGMII1 - Connected to 1512 port
271	 * Lane 4: Not used
272	 * Lane 5: SGMII2 - Connected to Topaz switch
273	 */
274	phy0 {
275		phy-type = <COMPHY_TYPE_SATA1>;
276		phy-invert = <COMPHY_POLARITY_RXD_INVERT>;
277	};
278	phy1 {
279		phy-type = <COMPHY_TYPE_UNCONNECTED>;
280	};
281	phy2 {
282		phy-type = <COMPHY_TYPE_USB3_HOST0>;
283	};
284	phy3 {
285		phy-type = <COMPHY_TYPE_SGMII1>;
286		phy-speed = <COMPHY_SPEED_1_25G>;
287	};
288	phy4 {
289		phy-type = <COMPHY_TYPE_UNCONNECTED>;
290	};
291	phy5 {
292		phy-type = <COMPHY_TYPE_SGMII2>;
293		phy-speed = <COMPHY_SPEED_3_125G>;
294	};
295};
296
297&cp1_mdio {
298	phy0: ethernet-phy@0 {
299		reg = <0>;
300	};
301};
302
303&cp1_ethernet {
304	pinctrl-names = "default";
305	pinctrl-0 = <&cp1_1g_phy_reset>;
306	status = "okay";
307};
308
309/* 1G SGMII */
310&cp1_eth1 {
311	status = "okay";
312	phy-mode = "sgmii";
313	phy = <&phy0>;
314	phy-reset-gpios = <&cp0_gpio1 11 GPIO_ACTIVE_LOW>;
315};
316
317/* 2.5G to Topaz switch */
318&cp1_eth2 {
319	status = "okay";
320	phy-mode = "sgmii";
321	phy-speed = <2500>;
322	phy-reset-gpios = <&cp1_gpio0 24 GPIO_ACTIVE_LOW>;
323};
324