1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Copyright (c) 2021 Linumiz
4 * Author: Navin Sankar Velliangiri <navin@linumiz.com>
5 */
6
7#include <dt-bindings/gpio/gpio.h>
8#include <dt-bindings/interrupt-controller/irq.h>
9#include <dt-bindings/pwm/pwm.h>
10
11/ {
12	model = "Seeed NPi-iMX6ULL Dev Board";
13	compatible = "fsl,imx6ull";
14
15	chosen {
16		stdout-path = &uart1;
17	};
18
19	leds {
20		compatible = "gpio-leds";
21
22		user-led {
23			label = "User";
24			pinctrl-names = "default";
25			pinctrl-0 = <&pinctrl_gpios>;
26			gpios = <&gpio5 3 GPIO_ACTIVE_HIGH>;
27			linux,default-trigger = "heartbeat";
28		};
29	};
30};
31
32&gpmi {
33	pinctrl-names = "default";
34	pinctrl-0 = <&pinctrl_gpmi_nand>;
35	nand-on-flash-bbt;
36	status = "disabled";
37};
38
39&uart1 {
40	pinctrl-name = "default";
41	pinctrl-0 = <&pinctrl_uart1>;
42	status = "okay";
43};
44
45&usdhc1 {
46	pinctrl-names = "default", "state_100mhz", "state_200mhz";
47	pinctrl-0 = <&pinctrl_usdhc1>;
48	pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
49	pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
50	cd-gpios = <&gpio1 19 GPIO_ACTIVE_LOW>;
51	no-1-8-v;
52	keep-power-in-suspend;
53	wakeup-source;
54	status = "okay";
55};
56
57&usdhc2 {
58	pinctrl-names = "default";
59	pinctrl-0 = <&pinctrl_usdhc2>;
60	pinctrl-1 = <&pinctrl_usdhc2_100mhz>;
61	pinctrl-2 = <&pinctrl_usdhc2_200mhz>;
62	bus-width = <8>;
63	non-removable;
64	keep-power-in-suspend;
65};
66
67&fec1 {
68	pinctrl-names = "default";
69	pinctrl-0 = <&pinctrl_enet1>;
70	phy-mode = "rmii";
71	phy-handle = <&ethphy0>;
72	status = "okay";
73};
74
75&fec2 {
76	pinctrl-names = "default";
77	pinctrl-0 = <&pinctrl_enet2>;
78	phy-mode = "rmii";
79	phy-handle = <&ethphy1>;
80	status = "okay";
81
82	mdio {
83		#address-cells = <1>;
84		#size-cells = <0>;
85
86		ethphy0: ethernet-phy@2 {
87			compatible = "ethernet-phy-ieee802.3-c22";
88			reg = <2>;
89			micrel,led-mode = <1>;
90			clocks = <&clks IMX6UL_CLK_ENET_REF>;
91			clock-names = "rmii-ref";
92		};
93
94		ethphy1: ethernet-phy@1 {
95			compatible = "ethernet-phy-ieee802.3-c22";
96			reg = <1>;
97			micrel,led-mode = <1>;
98			clocks = <&clks IMX6UL_CLK_ENET2_REF>;
99			clock-names = "rmii-ref";
100		};
101	};
102};
103
104&usbotg1 {
105	pinctrl-names = "default";
106	pinctrl-0 = <&pinctrl_usb_otg1_id>;
107	dr_mode = "otg";
108	srp-disable;
109	hnp-disable;
110	adp-disable;
111	status = "okay";
112};
113
114&usbotg2 {
115	dr_mode = "host";
116	disable-over-current;
117	status = "okay";
118};
119
120&iomuxc {
121	pinctrl-names = "default";
122	pinctrl-0 = <&pinctrl_gpios>;
123
124	pinctrl_uart1: uart1grp {
125		fsl,pin = <
126			MX6UL_PAD_UART1_TX_DATA__UART1_DCE_TX	0x1b0b1
127			MX6UL_PAD_UART1_RX_DATA__UART1_DCE_RX	0x1b0b1
128		>;
129	};
130
131	pinctrl_usb_otg1_id: usbotg1idgrp {
132		fsl,pin = <
133			MX6UL_PAD_GPIO1_IO00__ANATOP_OTG1_ID	0x17059
134		>;
135	};
136
137	pinctrl_gpmi_nand: gpminandgrp {
138		fsl,pins = <
139			MX6UL_PAD_NAND_DQS__RAWNAND_DQS		0x0b0b1
140			MX6UL_PAD_NAND_CLE__RAWNAND_CLE		0x0b0b1
141			MX6UL_PAD_NAND_ALE__RAWNAND_ALE		0x0b0b1
142			MX6UL_PAD_NAND_WP_B__RAWNAND_WP_B	0x0b0b1
143			MX6UL_PAD_NAND_READY_B__RAWNAND_READY_B	0x0b000
144			MX6UL_PAD_NAND_CE0_B__RAWNAND_CE0_B	0x0b0b1
145			MX6UL_PAD_NAND_CE1_B__RAWNAND_CE1_B	0x0b0b1
146			MX6UL_PAD_NAND_RE_B__RAWNAND_RE_B	0x0b0b1
147			MX6UL_PAD_NAND_WE_B__RAWNAND_WE_B	0x0b0b1
148			MX6UL_PAD_NAND_DATA00__RAWNAND_DATA00	0x0b0b1
149			MX6UL_PAD_NAND_DATA01__RAWNAND_DATA01	0x0b0b1
150			MX6UL_PAD_NAND_DATA02__RAWNAND_DATA02	0x0b0b1
151			MX6UL_PAD_NAND_DATA03__RAWNAND_DATA03	0x0b0b1
152			MX6UL_PAD_NAND_DATA04__RAWNAND_DATA04	0x0b0b1
153			MX6UL_PAD_NAND_DATA05__RAWNAND_DATA05	0x0b0b1
154			MX6UL_PAD_NAND_DATA06__RAWNAND_DATA06   0x0b0b1
155			MX6UL_PAD_NAND_DATA07__RAWNAND_DATA07	0x0b0b1
156		>;
157	};
158
159	pinctrl_usdhc1: usdhc1grp {
160		fsl,pins = <
161			MX6UL_PAD_SD1_CMD__USDHC1_CMD		0x17059
162			MX6UL_PAD_SD1_CLK__USDHC1_CLK		0x10059
163			MX6UL_PAD_SD1_DATA0__USDHC1_DATA0	0x17059
164			MX6UL_PAD_SD1_DATA1__USDHC1_DATA1	0x17059
165			MX6UL_PAD_SD1_DATA2__USDHC1_DATA2	0x17059
166			MX6UL_PAD_SD1_DATA3__USDHC1_DATA3	0x17059
167			MX6UL_PAD_UART1_RTS_B__GPIO1_IO19	0x17059
168		>;
169	};
170
171	pinctrl_usdhc1_100mhz: usdhc1grp100mhz {
172		fsl,pins = <
173			MX6UL_PAD_SD1_CMD__USDHC1_CMD		0x170b9
174			MX6UL_PAD_SD1_CLK__USDHC1_CLK		0x100b9
175			MX6UL_PAD_SD1_DATA0__USDHC1_DATA0	0x170b9
176			MX6UL_PAD_SD1_DATA1__USDHC1_DATA1	0x170b9
177			MX6UL_PAD_SD1_DATA2__USDHC1_DATA2	0x170b9
178			MX6UL_PAD_SD1_DATA3__USDHC1_DATA3	0x170b9
179		>;
180	};
181
182	pinctrl_usdhc1_200mhz: usdhc1grp200mhz {
183		fsl,pins = <
184			MX6UL_PAD_SD1_CMD__USDHC1_CMD		0x170f9
185			MX6UL_PAD_SD1_CLK__USDHC1_CLK		0x100f9
186			MX6UL_PAD_SD1_DATA0__USDHC1_DATA0	0x170f9
187			MX6UL_PAD_SD1_DATA1__USDHC1_DATA1	0x170f9
188			MX6UL_PAD_SD1_DATA2__USDHC1_DATA2	0x170f9
189			MX6UL_PAD_SD1_DATA3__USDHC1_DATA3	0x170f9
190		>;
191	};
192
193	pinctrl_usdhc2: usdhc2grp {
194		fsl,pins = <
195			MX6UL_PAD_NAND_RE_B__USDHC2_CLK		0x10069
196			MX6UL_PAD_NAND_WE_B__USDHC2_CMD		0x17059
197			MX6UL_PAD_NAND_DATA00__USDHC2_DATA0	0x17059
198			MX6UL_PAD_NAND_DATA01__USDHC2_DATA1	0x17059
199			MX6UL_PAD_NAND_DATA02__USDHC2_DATA2	0x17059
200			MX6UL_PAD_NAND_DATA03__USDHC2_DATA3	0x17059
201			MX6UL_PAD_NAND_DATA04__USDHC2_DATA4	0x17059
202			MX6UL_PAD_NAND_DATA05__USDHC2_DATA5	0x17059
203			MX6UL_PAD_NAND_DATA06__USDHC2_DATA6	0x17059
204			MX6UL_PAD_NAND_DATA07__USDHC2_DATA7	0x17059
205		>;
206	};
207
208	pinctrl_usdhc2_100mhz: usdhc2grp100mhz {
209		fsl,pins = <
210			MX6UL_PAD_NAND_RE_B__USDHC2_CLK		0x100b9
211			MX6UL_PAD_NAND_WE_B__USDHC2_CMD		0x170b9
212			MX6UL_PAD_NAND_DATA00__USDHC2_DATA0	0x170b9
213			MX6UL_PAD_NAND_DATA01__USDHC2_DATA1	0x170b9
214			MX6UL_PAD_NAND_DATA02__USDHC2_DATA2	0x170b9
215			MX6UL_PAD_NAND_DATA03__USDHC2_DATA3	0x170b9
216			MX6UL_PAD_NAND_DATA04__USDHC2_DATA4	0x170b9
217			MX6UL_PAD_NAND_DATA05__USDHC2_DATA5	0x170b9
218			MX6UL_PAD_NAND_DATA06__USDHC2_DATA6	0x170b9
219			MX6UL_PAD_NAND_DATA07__USDHC2_DATA7	0x170b9
220		>;
221	};
222
223	pinctrl_usdhc2_200mhz: usdhc2grp200mhz {
224		fsl,pins = <
225			MX6UL_PAD_NAND_RE_B__USDHC2_CLK		0x100f9
226			MX6UL_PAD_NAND_WE_B__USDHC2_CMD		0x170f9
227			MX6UL_PAD_NAND_DATA00__USDHC2_DATA0	0x170f9
228			MX6UL_PAD_NAND_DATA01__USDHC2_DATA1	0x170f9
229			MX6UL_PAD_NAND_DATA02__USDHC2_DATA2	0x170f9
230			MX6UL_PAD_NAND_DATA03__USDHC2_DATA3	0x170f9
231			MX6UL_PAD_NAND_DATA04__USDHC2_DATA4	0x170f9
232			MX6UL_PAD_NAND_DATA05__USDHC2_DATA5	0x170f9
233			MX6UL_PAD_NAND_DATA06__USDHC2_DATA6	0x170f9
234			MX6UL_PAD_NAND_DATA07__USDHC2_DATA7	0x170f9
235		>;
236	};
237
238	pinctrl_enet1: enet1grp {
239		fsl,pins = <
240			MX6UL_PAD_ENET1_RX_EN__ENET1_RX_EN      0x1b0b0
241			MX6UL_PAD_ENET1_RX_ER__ENET1_RX_ER      0x1b0b0
242			MX6UL_PAD_ENET1_RX_DATA0__ENET1_RDATA00 0x1b0b0
243			MX6UL_PAD_ENET1_RX_DATA1__ENET1_RDATA01 0x1b0b0
244			MX6UL_PAD_ENET1_TX_EN__ENET1_TX_EN      0x1b0b0
245			MX6UL_PAD_ENET1_TX_DATA0__ENET1_TDATA00 0x1b0b0
246			MX6UL_PAD_ENET1_TX_DATA1__ENET1_TDATA01 0x1b0b0
247			MX6UL_PAD_ENET1_TX_CLK__ENET1_REF_CLK1  0x4001b031
248		>;
249	};
250
251	pinctrl_enet2: enet2grp {
252		fsl,pins = <
253			MX6UL_PAD_GPIO1_IO07__ENET2_MDC         0x1b0b0
254			MX6UL_PAD_GPIO1_IO06__ENET2_MDIO        0x1b0b0
255			MX6UL_PAD_ENET2_RX_EN__ENET2_RX_EN      0x1b0b0
256			MX6UL_PAD_ENET2_RX_ER__ENET2_RX_ER      0x1b0b0
257			MX6UL_PAD_ENET2_RX_DATA0__ENET2_RDATA00 0x1b0b0
258			MX6UL_PAD_ENET2_RX_DATA1__ENET2_RDATA01 0x1b0b0
259			MX6UL_PAD_ENET2_TX_EN__ENET2_TX_EN      0x1b0b0
260			MX6UL_PAD_ENET2_TX_DATA0__ENET2_TDATA00 0x1b0b0
261			MX6UL_PAD_ENET2_TX_DATA1__ENET2_TDATA01 0x1b0b0
262			MX6UL_PAD_ENET2_TX_CLK__ENET2_REF_CLK2  0x4001b031
263		>;
264	};
265
266	pinctrl_gpios: gpiosgrp {
267		fsl,pins = <
268			MX6UL_PAD_SNVS_TAMPER3__GPIO5_IO03	0x0b0b0
269		>;
270	};
271};
272