1// SPDX-License-Identifier: GPL-2.0+
2/*
3 * Copyright 2021 Gateworks Corporation
4 */
5
6/dts-v1/;
7
8#include "imx8mm.dtsi"
9
10/ {
11	model = "Gateworks Venice i.MX8MM board";
12	compatible = "gw,imx8mm-venice", "fsl,imx8mm";
13
14	chosen {
15		stdout-path = &uart2;
16	};
17
18	memory@40000000 {
19		device_type = "memory";
20		reg = <0x0 0x40000000 0 0x80000000>;
21	};
22};
23
24&i2c1 {
25	clock-frequency = <100000>;
26	pinctrl-names = "default";
27	pinctrl-0 = <&pinctrl_i2c1>;
28	status = "okay";
29
30	eeprom@51 {
31		compatible = "atmel,24c02";
32		reg = <0x51>;
33		pagesize = <16>;
34	};
35};
36
37&i2c2 {
38	clock-frequency = <400000>;
39	pinctrl-names = "default";
40	pinctrl-0 = <&pinctrl_i2c2>;
41	status = "okay";
42
43	eeprom@52 {
44		compatible = "atmel,24c32";
45		reg = <0x52>;
46		pagesize = <32>;
47	};
48};
49
50/* console */
51&uart2 {
52	pinctrl-names = "default";
53	pinctrl-0 = <&pinctrl_uart2>;
54	status = "okay";
55};
56
57/* eMMC */
58&usdhc3 {
59	assigned-clocks = <&clk IMX8MM_CLK_USDHC3_ROOT>;
60	assigned-clock-rates = <400000000>;
61	pinctrl-names = "default", "state_100mhz", "state_200mhz";
62	pinctrl-0 = <&pinctrl_usdhc3>;
63	pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
64	pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
65	bus-width = <8>;
66	non-removable;
67	status = "okay";
68};
69
70&wdog1 {
71	pinctrl-names = "default";
72	pinctrl-0 = <&pinctrl_wdog>;
73	fsl,ext-reset-output;
74	status = "okay";
75};
76
77&iomuxc {
78	pinctrl_i2c1: i2c1grp {
79		fsl,pins = <
80			MX8MM_IOMUXC_I2C1_SCL_I2C1_SCL		0x400001c3
81			MX8MM_IOMUXC_I2C1_SDA_I2C1_SDA		0x400001c3
82		>;
83	};
84
85	pinctrl_i2c2: i2c2grp {
86		fsl,pins = <
87			MX8MM_IOMUXC_I2C2_SCL_I2C2_SCL		0x400001c3
88			MX8MM_IOMUXC_I2C2_SDA_I2C2_SDA		0x400001c3
89		>;
90	};
91
92	pinctrl_uart2: uart2grp {
93		fsl,pins = <
94			MX8MM_IOMUXC_UART2_RXD_UART2_DCE_RX	0x140
95			MX8MM_IOMUXC_UART2_TXD_UART2_DCE_TX	0x140
96		>;
97	};
98
99	pinctrl_usdhc3: usdhc3grp {
100		fsl,pins = <
101			MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK	0x190
102			MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD	0x1d0
103			MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0	0x1d0
104			MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1	0x1d0
105			MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2	0x1d0
106			MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3	0x1d0
107			MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4	0x1d0
108			MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5	0x1d0
109			MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6	0x1d0
110			MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7	0x1d0
111			MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE	0x190
112		>;
113	};
114
115	pinctrl_usdhc3_100mhz: usdhc3grp100mhz {
116		fsl,pins = <
117			MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK	0x194
118			MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD	0x1d4
119			MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0	0x1d4
120			MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1	0x1d4
121			MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2	0x1d4
122			MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3	0x1d4
123			MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4	0x1d4
124			MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5	0x1d4
125			MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6	0x1d4
126			MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7	0x1d4
127			MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE	0x194
128		>;
129	};
130
131	pinctrl_usdhc3_200mhz: usdhc3grp200mhz {
132		fsl,pins = <
133			MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK	0x196
134			MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD	0x1d6
135			MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0	0x1d6
136			MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1	0x1d6
137			MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2	0x1d6
138			MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3	0x1d6
139			MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4	0x1d6
140			MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5	0x1d6
141			MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6	0x1d6
142			MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7	0x1d6
143			MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE	0x196
144		>;
145	};
146
147	pinctrl_wdog: wdoggrp {
148		fsl,pins = <
149			MX8MM_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B	0xc6
150		>;
151	};
152};
153