1// SPDX-License-Identifier: GPL-2.0 2/* 3 * Copyright (C) 2019 Texas Instruments Incorporated - http://www.ti.com/ 4 */ 5 6/dts-v1/; 7 8#include "k3-j721e-som-p0.dtsi" 9#include "k3-j721e-ddr-evm-lp4-4266.dtsi" 10#include "k3-j721e-ddr.dtsi" 11 12/ { 13 aliases { 14 remoteproc0 = &sysctrler; 15 remoteproc1 = &a72_0; 16 remoteproc2 = &main_r5fss0_core0; 17 remoteproc3 = &main_r5fss0_core1; 18 }; 19 20 chosen { 21 stdout-path = "serial2:115200n8"; 22 tick-timer = &timer1; 23 }; 24 25 a72_0: a72@0 { 26 compatible = "ti,am654-rproc"; 27 reg = <0x0 0x00a90000 0x0 0x10>; 28 power-domains = <&k3_pds 61 TI_SCI_PD_EXCLUSIVE>, 29 <&k3_pds 202 TI_SCI_PD_EXCLUSIVE>; 30 resets = <&k3_reset 202 0>; 31 clocks = <&k3_clks 61 1>; 32 assigned-clocks = <&k3_clks 202 2>, <&k3_clks 61 1>; 33 assigned-clock-rates = <2000000000>, <200000000>; 34 ti,sci = <&dmsc>; 35 ti,sci-proc-id = <32>; 36 ti,sci-host-id = <10>; 37 u-boot,dm-spl; 38 }; 39 40 clk_200mhz: dummy_clock_200mhz { 41 compatible = "fixed-clock"; 42 #clock-cells = <0>; 43 clock-frequency = <200000000>; 44 u-boot,dm-spl; 45 }; 46 47 clk_19_2mhz: dummy_clock_19_2mhz { 48 compatible = "fixed-clock"; 49 #clock-cells = <0>; 50 clock-frequency = <19200000>; 51 u-boot,dm-spl; 52 }; 53}; 54 55&cbass_mcu_wakeup { 56 mcu_secproxy: secproxy@28380000 { 57 u-boot,dm-spl; 58 compatible = "ti,am654-secure-proxy"; 59 reg = <0x0 0x2a380000 0x0 0x80000>, 60 <0x0 0x2a400000 0x0 0x80000>, 61 <0x0 0x2a480000 0x0 0x80000>; 62 reg-names = "rt", "scfg", "target_data"; 63 #mbox-cells = <1>; 64 }; 65 66 sysctrler: sysctrler { 67 u-boot,dm-spl; 68 compatible = "ti,am654-system-controller"; 69 mboxes= <&mcu_secproxy 4>, <&mcu_secproxy 5>; 70 mbox-names = "tx", "rx"; 71 }; 72 73 wkup_vtm0: wkup_vtm@42040000 { 74 compatible = "ti,am654-vtm", "ti,j721e-avs"; 75 reg = <0x0 0x42040000 0x0 0x330>; 76 power-domains = <&k3_pds 154 TI_SCI_PD_EXCLUSIVE>; 77 #thermal-sensor-cells = <1>; 78 }; 79}; 80 81&cbass_main { 82 main_esm: esm@700000 { 83 compatible = "ti,j721e-esm"; 84 reg = <0x0 0x700000 0x0 0x1000>; 85 ti,esm-pins = <344>, <345>; 86 u-boot,dm-spl; 87 }; 88}; 89 90&dmsc { 91 mboxes= <&mcu_secproxy 8>, <&mcu_secproxy 6>, <&mcu_secproxy 5>; 92 mbox-names = "tx", "rx", "notify"; 93 ti,host-id = <4>; 94 ti,secure-host; 95}; 96 97&wkup_pmx0 { 98 wkup_uart0_pins_default: wkup_uart0_pins_default { 99 u-boot,dm-spl; 100 pinctrl-single,pins = < 101 J721E_WKUP_IOPAD(0xa0, PIN_INPUT, 0) /* (J29) WKUP_UART0_RXD */ 102 J721E_WKUP_IOPAD(0xa4, PIN_OUTPUT, 0) /* (J28) WKUP_UART0_TXD */ 103 >; 104 }; 105 106 mcu_uart0_pins_default: mcu_uart0_pins_default { 107 u-boot,dm-spl; 108 pinctrl-single,pins = < 109 J721E_WKUP_IOPAD(0xe8, PIN_INPUT, 0) /* (H29) WKUP_GPIO0_14.MCU_UART0_CTSn */ 110 J721E_WKUP_IOPAD(0xec, PIN_OUTPUT, 0) /* (J27) WKUP_GPIO0_15.MCU_UART0_RTSn */ 111 J721E_WKUP_IOPAD(0xe4, PIN_INPUT, 0) /* (H28) WKUP_GPIO0_13.MCU_UART0_RXD */ 112 J721E_WKUP_IOPAD(0xe0, PIN_OUTPUT, 0) /* (G29) WKUP_GPIO0_12.MCU_UART0_TXD */ 113 >; 114 }; 115 116 wkup_i2c0_pins_default: wkup-i2c0-pins-default { 117 pinctrl-single,pins = < 118 J721E_WKUP_IOPAD(0xf8, PIN_INPUT_PULLUP, 0) /* (J25) WKUP_I2C0_SCL */ 119 J721E_WKUP_IOPAD(0xfc, PIN_INPUT_PULLUP, 0) /* (H24) WKUP_I2C0_SDA */ 120 >; 121 }; 122 123 mcu_fss0_ospi0_pins_default: mcu-fss0-ospi0-pins-default { 124 pinctrl-single,pins = < 125 J721E_WKUP_IOPAD(0x0000, PIN_OUTPUT, 0) /* MCU_OSPI0_CLK */ 126 J721E_WKUP_IOPAD(0x0008, PIN_INPUT, 0) /* MCU_OSPI0_DQS */ 127 J721E_WKUP_IOPAD(0x000c, PIN_INPUT, 0) /* MCU_OSPI0_D0 */ 128 J721E_WKUP_IOPAD(0x0010, PIN_INPUT, 0) /* MCU_OSPI0_D1 */ 129 J721E_WKUP_IOPAD(0x0014, PIN_INPUT, 0) /* MCU_OSPI0_D2 */ 130 J721E_WKUP_IOPAD(0x0018, PIN_INPUT, 0) /* MCU_OSPI0_D3 */ 131 J721E_WKUP_IOPAD(0x001c, PIN_INPUT, 0) /* MCU_OSPI0_D4 */ 132 J721E_WKUP_IOPAD(0x0020, PIN_INPUT, 0) /* MCU_OSPI0_D5 */ 133 J721E_WKUP_IOPAD(0x0024, PIN_INPUT, 0) /* MCU_OSPI0_D6 */ 134 J721E_WKUP_IOPAD(0x0028, PIN_INPUT, 0) /* MCU_OSPI0_D7 */ 135 J721E_WKUP_IOPAD(0x002c, PIN_OUTPUT, 0) /* MCU_OSPI0_CSn0 */ 136 >; 137 }; 138 139 mcu_fss0_ospi1_pins_default: mcu-fss0-ospi1-pins-default { 140 u-boot,dm-spl; 141 pinctrl-single,pins = < 142 J721E_WKUP_IOPAD(0x34, PIN_OUTPUT, 0) /* (F22) MCU_OSPI1_CLK */ 143 J721E_WKUP_IOPAD(0x50, PIN_OUTPUT, 0) /* (C22) MCU_OSPI1_CSn0 */ 144 J721E_WKUP_IOPAD(0x40, PIN_INPUT, 0) /* (D22) MCU_OSPI1_D0 */ 145 J721E_WKUP_IOPAD(0x44, PIN_INPUT, 0) /* (G22) MCU_OSPI1_D1 */ 146 J721E_WKUP_IOPAD(0x48, PIN_INPUT, 0) /* (D23) MCU_OSPI1_D2 */ 147 J721E_WKUP_IOPAD(0x4c, PIN_INPUT, 0) /* (C23) MCU_OSPI1_D3 */ 148 J721E_WKUP_IOPAD(0x3c, PIN_INPUT, 0) /* (B23) MCU_OSPI1_DQS */ 149 J721E_WKUP_IOPAD(0x38, PIN_INPUT, 0) /* (A23) MCU_OSPI1_LBCLKO */ 150 >; 151 }; 152}; 153 154&main_pmx0 { 155 main_uart0_pins_default: main_uart0_pins_default { 156 u-boot,dm-spl; 157 pinctrl-single,pins = < 158 J721E_IOPAD(0x1d4, PIN_INPUT, 1) /* (Y3) SPI1_CS0.UART0_CTSn */ 159 J721E_IOPAD(0x1c0, PIN_OUTPUT, 1) /* (AA2) SPI0_CS0.UART0_RTSn */ 160 J721E_IOPAD(0x1e8, PIN_INPUT, 0) /* (AB2) UART0_RXD */ 161 J721E_IOPAD(0x1ec, PIN_OUTPUT, 0) /* (AB3) UART0_TXD */ 162 >; 163 }; 164 165 main_usbss0_pins_default: main_usbss0_pins_default { 166 pinctrl-single,pins = < 167 J721E_IOPAD(0x290, PIN_OUTPUT, 0) /* (U6) USB0_DRVVBUS */ 168 J721E_IOPAD(0x210, PIN_INPUT, 7) /* (W3) MCAN1_RX.GPIO1_3 */ 169 >; 170 }; 171 172 main_mmc1_pins_default: main_mmc1_pins_default { 173 pinctrl-single,pins = < 174 J721E_IOPAD(0x254, PIN_INPUT, 0) /* (R29) MMC1_CMD */ 175 J721E_IOPAD(0x250, PIN_INPUT, 0) /* (P25) MMC1_CLK */ 176 J721E_IOPAD(0x2ac, PIN_INPUT, 0) /* (P25) MMC1_CLKLB */ 177 J721E_IOPAD(0x24c, PIN_INPUT, 0) /* (R24) MMC1_DAT0 */ 178 J721E_IOPAD(0x248, PIN_INPUT, 0) /* (P24) MMC1_DAT1 */ 179 J721E_IOPAD(0x244, PIN_INPUT, 0) /* (R25) MMC1_DAT2 */ 180 J721E_IOPAD(0x240, PIN_INPUT, 0) /* (R26) MMC1_DAT3 */ 181 J721E_IOPAD(0x258, PIN_INPUT, 0) /* (P23) MMC1_SDCD */ 182 J721E_IOPAD(0x25c, PIN_INPUT, 0) /* (R28) MMC1_SDWP */ 183 >; 184 }; 185 186 main_i2c0_pins_default: main-i2c0-pins-default { 187 pinctrl-single,pins = < 188 J721E_IOPAD(0x220, PIN_INPUT_PULLUP, 0) /* (AC5) I2C0_SCL */ 189 J721E_IOPAD(0x224, PIN_INPUT_PULLUP, 0) /* (AA5) I2C0_SDA */ 190 >; 191 }; 192}; 193 194&wkup_uart0 { 195 u-boot,dm-spl; 196 pinctrl-names = "default"; 197 pinctrl-0 = <&wkup_uart0_pins_default>; 198 status = "okay"; 199}; 200 201&mcu_uart0 { 202 /delete-property/ power-domains; 203 /delete-property/ clocks; 204 /delete-property/ clock-names; 205 pinctrl-names = "default"; 206 pinctrl-0 = <&mcu_uart0_pins_default>; 207 status = "okay"; 208 clock-frequency = <48000000>; 209}; 210 211&main_uart0 { 212 pinctrl-names = "default"; 213 pinctrl-0 = <&main_uart0_pins_default>; 214 status = "okay"; 215 power-domains = <&k3_pds 146 TI_SCI_PD_SHARED>; 216}; 217 218&main_sdhci0 { 219 /delete-property/ power-domains; 220 /delete-property/ assigned-clocks; 221 /delete-property/ assigned-clock-parents; 222 clock-names = "clk_xin"; 223 clocks = <&clk_200mhz>; 224 ti,driver-strength-ohm = <50>; 225 non-removable; 226 bus-width = <8>; 227}; 228 229&main_sdhci1 { 230 /delete-property/ power-domains; 231 /delete-property/ assigned-clocks; 232 /delete-property/ assigned-clock-parents; 233 pinctrl-names = "default"; 234 pinctrl-0 = <&main_mmc1_pins_default>; 235 clock-names = "clk_xin"; 236 clocks = <&clk_200mhz>; 237 ti,driver-strength-ohm = <50>; 238}; 239 240&wkup_i2c0 { 241 u-boot,dm-spl; 242 tps659413a: tps659413a@48 { 243 reg = <0x48>; 244 compatible = "ti,tps659413"; 245 u-boot,dm-spl; 246 pinctrl-names = "default"; 247 pinctrl-0 = <&wkup_i2c0_pins_default>; 248 clock-frequency = <400000>; 249 250 regulators: regulators { 251 u-boot,dm-spl; 252 buck12_reg: buck12 { 253 /*VDD_MPU*/ 254 regulator-name = "buck12"; 255 regulator-min-microvolt = <800000>; 256 regulator-max-microvolt = <1250000>; 257 regulator-always-on; 258 regulator-boot-on; 259 u-boot,dm-spl; 260 }; 261 }; 262 }; 263}; 264 265&wkup_vtm0 { 266 vdd-supply-2 = <&buck12_reg>; 267 u-boot,dm-spl; 268}; 269 270&usbss0 { 271 /delete-property/ power-domains; 272 /delete-property/ assigned-clocks; 273 /delete-property/ assigned-clock-parents; 274 clocks = <&clk_19_2mhz>; 275 clock-names = "usb2_refclk"; 276 pinctrl-names = "default"; 277 pinctrl-0 = <&main_usbss0_pins_default>; 278 ti,vbus-divider; 279}; 280 281&main_i2c0 { 282 pinctrl-names = "default"; 283 pinctrl-0 = <&main_i2c0_pins_default>; 284 clock-frequency = <400000>; 285 286 exp1: gpio@20 { 287 compatible = "ti,tca6416"; 288 reg = <0x20>; 289 gpio-controller; 290 #gpio-cells = <2>; 291 }; 292 293 exp2: gpio@22 { 294 compatible = "ti,tca6424"; 295 reg = <0x22>; 296 gpio-controller; 297 #gpio-cells = <2>; 298 }; 299}; 300 301&ospi0 { 302 pinctrl-names = "default"; 303 pinctrl-0 = <&mcu_fss0_ospi0_pins_default>; 304 305 reg = <0x0 0x47040000 0x0 0x100>, 306 <0x0 0x50000000 0x0 0x8000000>; 307 308 flash@0{ 309 compatible = "jedec,spi-nor"; 310 reg = <0x0>; 311 spi-tx-bus-width = <1>; 312 spi-rx-bus-width = <8>; 313 spi-max-frequency = <50000000>; 314 cdns,tshsl-ns = <60>; 315 cdns,tsd2d-ns = <60>; 316 cdns,tchsh-ns = <60>; 317 cdns,tslch-ns = <60>; 318 cdns,read-delay = <0>; 319 #address-cells = <1>; 320 #size-cells = <1>; 321 }; 322}; 323 324&ospi1 { 325 pinctrl-names = "default"; 326 pinctrl-0 = <&mcu_fss0_ospi1_pins_default>; 327 u-boot,dm-spl; 328 329 reg = <0x0 0x47050000 0x0 0x100>, 330 <0x0 0x58000000 0x0 0x8000000>; 331 332 flash@0{ 333 compatible = "jedec,spi-nor"; 334 reg = <0x0>; 335 spi-tx-bus-width = <1>; 336 spi-rx-bus-width = <4>; 337 spi-max-frequency = <40000000>; 338 cdns,tshsl-ns = <60>; 339 cdns,tsd2d-ns = <60>; 340 cdns,tchsh-ns = <60>; 341 cdns,tslch-ns = <60>; 342 cdns,read-delay = <2>; 343 #address-cells = <1>; 344 #size-cells = <1>; 345 u-boot,dm-spl; 346 }; 347}; 348