1// SPDX-License-Identifier: GPL-2.0+ 2/* 3 * dts file for Xilinx ZynqMP ZCU104 4 * 5 * (C) Copyright 2017 - 2020, Xilinx, Inc. 6 * 7 * Michal Simek <michal.simek@xilinx.com> 8 */ 9 10/dts-v1/; 11 12#include "zynqmp.dtsi" 13#include "zynqmp-clk-ccf.dtsi" 14#include <dt-bindings/gpio/gpio.h> 15#include <dt-bindings/pinctrl/pinctrl-zynqmp.h> 16#include <dt-bindings/phy/phy.h> 17 18/ { 19 model = "ZynqMP ZCU104 RevA"; 20 compatible = "xlnx,zynqmp-zcu104-revA", "xlnx,zynqmp-zcu104", "xlnx,zynqmp"; 21 22 aliases { 23 ethernet0 = &gem3; 24 gpio0 = &gpio; 25 i2c0 = &i2c1; 26 mmc0 = &sdhci1; 27 rtc0 = &rtc; 28 serial0 = &uart0; 29 serial1 = &uart1; 30 serial2 = &dcc; 31 spi0 = &qspi; 32 usb0 = &usb0; 33 }; 34 35 chosen { 36 bootargs = "earlycon"; 37 stdout-path = "serial0:115200n8"; 38 }; 39 40 memory@0 { 41 device_type = "memory"; 42 reg = <0x0 0x0 0x0 0x80000000>; 43 }; 44 45 clock_8t49n287_5: clk125 { 46 compatible = "fixed-clock"; 47 #clock-cells = <0>; 48 clock-frequency = <125000000>; 49 }; 50 51 clock_8t49n287_2: clk26 { 52 compatible = "fixed-clock"; 53 #clock-cells = <0>; 54 clock-frequency = <26000000>; 55 }; 56 57 clock_8t49n287_3: clk27 { 58 compatible = "fixed-clock"; 59 #clock-cells = <0>; 60 clock-frequency = <27000000>; 61 }; 62}; 63 64&can1 { 65 status = "okay"; 66 pinctrl-names = "default"; 67 pinctrl-0 = <&pinctrl_can1_default>; 68}; 69 70&dcc { 71 status = "okay"; 72}; 73 74&fpd_dma_chan1 { 75 status = "okay"; 76}; 77 78&fpd_dma_chan2 { 79 status = "okay"; 80}; 81 82&fpd_dma_chan3 { 83 status = "okay"; 84}; 85 86&fpd_dma_chan4 { 87 status = "okay"; 88}; 89 90&fpd_dma_chan5 { 91 status = "okay"; 92}; 93 94&fpd_dma_chan6 { 95 status = "okay"; 96}; 97 98&fpd_dma_chan7 { 99 status = "okay"; 100}; 101 102&fpd_dma_chan8 { 103 status = "okay"; 104}; 105 106&gem3 { 107 status = "okay"; 108 phy-handle = <&phy0>; 109 phy-mode = "rgmii-id"; 110 pinctrl-names = "default"; 111 pinctrl-0 = <&pinctrl_gem3_default>; 112 phy0: ethernet-phy@c { 113 reg = <0xc>; 114 ti,rx-internal-delay = <0x8>; 115 ti,tx-internal-delay = <0xa>; 116 ti,fifo-depth = <0x1>; 117 ti,dp83867-rxctrl-strap-quirk; 118 }; 119}; 120 121&gpio { 122 status = "okay"; 123}; 124 125&gpu { 126 status = "okay"; 127}; 128 129&i2c1 { 130 status = "okay"; 131 clock-frequency = <400000>; 132 pinctrl-names = "default", "gpio"; 133 pinctrl-0 = <&pinctrl_i2c1_default>; 134 pinctrl-1 = <&pinctrl_i2c1_gpio>; 135 scl-gpios = <&gpio 16 GPIO_ACTIVE_HIGH>; 136 sda-gpios = <&gpio 17 GPIO_ACTIVE_HIGH>; 137 138 /* Another connection to this bus via PL i2c via PCA9306 - u45 */ 139 i2c-mux@74 { /* u34 */ 140 compatible = "nxp,pca9548"; 141 #address-cells = <1>; 142 #size-cells = <0>; 143 reg = <0x74>; 144 i2c@0 { 145 #address-cells = <1>; 146 #size-cells = <0>; 147 reg = <0>; 148 /* 149 * IIC_EEPROM 1kB memory which uses 256B blocks 150 * where every block has different address. 151 * 0 - 256B address 0x54 152 * 256B - 512B address 0x55 153 * 512B - 768B address 0x56 154 * 768B - 1024B address 0x57 155 */ 156 eeprom: eeprom@54 { /* u23 */ 157 compatible = "atmel,24c08"; 158 reg = <0x54>; 159 #address-cells = <1>; 160 #size-cells = <1>; 161 }; 162 }; 163 164 i2c@1 { 165 #address-cells = <1>; 166 #size-cells = <0>; 167 reg = <1>; 168 clock_8t49n287: clock-generator@6c { /* 8T49N287 - u182 */ 169 compatible = "idt,8t49n287"; 170 reg = <0x6c>; 171 }; 172 }; 173 174 i2c@2 { 175 #address-cells = <1>; 176 #size-cells = <0>; 177 reg = <2>; 178 irps5401_43: irps5401@43 { /* IRPS5401 - u175 */ 179 compatible = "infineon,irps5401"; 180 reg = <0x43>; /* pmbus / i2c 0x13 */ 181 }; 182 irps5401_44: irps5401@44 { /* IRPS5401 - u180 */ 183 compatible = "infineon,irps5401"; 184 reg = <0x44>; /* pmbus / i2c 0x14 */ 185 }; 186 }; 187 188 i2c@4 { 189 #address-cells = <1>; 190 #size-cells = <0>; 191 reg = <4>; 192 tca6416_u97: gpio@20 { 193 compatible = "ti,tca6416"; 194 reg = <0x20>; 195 gpio-controller; 196 #gpio-cells = <2>; 197 /* 198 * IRQ not connected 199 * Lines: 200 * 0 - IRPS5401_ALERT_B 201 * 1 - HDMI_8T49N241_INT_ALM 202 * 2 - MAX6643_OT_B 203 * 3 - MAX6643_FANFAIL_B 204 * 5 - IIC_MUX_RESET_B 205 * 6 - GEM3_EXP_RESET_B 206 * 7 - FMC_LPC_PRSNT_M2C_B 207 * 4, 10 - 17 - not connected 208 */ 209 }; 210 }; 211 212 i2c@5 { 213 #address-cells = <1>; 214 #size-cells = <0>; 215 reg = <5>; 216 }; 217 218 i2c@7 { 219 #address-cells = <1>; 220 #size-cells = <0>; 221 reg = <7>; 222 }; 223 224 /* 3, 6 not connected */ 225 }; 226}; 227 228&pinctrl0 { 229 status = "okay"; 230 231 pinctrl_can1_default: can1-default { 232 mux { 233 function = "can1"; 234 groups = "can1_6_grp"; 235 }; 236 237 conf { 238 groups = "can1_6_grp"; 239 slew-rate = <SLEW_RATE_SLOW>; 240 power-source = <IO_STANDARD_LVCMOS18>; 241 drive-strength = <12>; 242 }; 243 244 conf-rx { 245 pins = "MIO25"; 246 bias-high-impedance; 247 }; 248 249 conf-tx { 250 pins = "MIO24"; 251 bias-disable; 252 }; 253 }; 254 255 pinctrl_i2c1_default: i2c1-default { 256 mux { 257 groups = "i2c1_4_grp"; 258 function = "i2c1"; 259 }; 260 261 conf { 262 groups = "i2c1_4_grp"; 263 bias-pull-up; 264 slew-rate = <SLEW_RATE_SLOW>; 265 power-source = <IO_STANDARD_LVCMOS18>; 266 drive-strength = <12>; 267 }; 268 }; 269 270 pinctrl_i2c1_gpio: i2c1-gpio { 271 mux { 272 groups = "gpio0_16_grp", "gpio0_17_grp"; 273 function = "gpio0"; 274 }; 275 276 conf { 277 groups = "gpio0_16_grp", "gpio0_17_grp"; 278 slew-rate = <SLEW_RATE_SLOW>; 279 power-source = <IO_STANDARD_LVCMOS18>; 280 drive-strength = <12>; 281 }; 282 }; 283 284 pinctrl_gem3_default: gem3-default { 285 mux { 286 function = "ethernet3"; 287 groups = "ethernet3_0_grp"; 288 }; 289 290 conf { 291 groups = "ethernet3_0_grp"; 292 slew-rate = <SLEW_RATE_SLOW>; 293 power-source = <IO_STANDARD_LVCMOS18>; 294 drive-strength = <12>; 295 }; 296 297 conf-rx { 298 pins = "MIO70", "MIO71", "MIO72", "MIO73", "MIO74", 299 "MIO75"; 300 bias-high-impedance; 301 low-power-disable; 302 }; 303 304 conf-tx { 305 pins = "MIO64", "MIO65", "MIO66", "MIO67", "MIO68", 306 "MIO69"; 307 bias-disable; 308 low-power-enable; 309 }; 310 311 mux-mdio { 312 function = "mdio3"; 313 groups = "mdio3_0_grp"; 314 }; 315 316 conf-mdio { 317 groups = "mdio3_0_grp"; 318 slew-rate = <SLEW_RATE_SLOW>; 319 power-source = <IO_STANDARD_LVCMOS18>; 320 bias-disable; 321 }; 322 }; 323 324 pinctrl_sdhci1_default: sdhci1-default { 325 mux { 326 groups = "sdio1_0_grp"; 327 function = "sdio1"; 328 }; 329 330 conf { 331 groups = "sdio1_0_grp"; 332 slew-rate = <SLEW_RATE_SLOW>; 333 power-source = <IO_STANDARD_LVCMOS18>; 334 bias-disable; 335 drive-strength = <12>; 336 }; 337 338 mux-cd { 339 groups = "sdio1_cd_0_grp"; 340 function = "sdio1_cd"; 341 }; 342 343 conf-cd { 344 groups = "sdio1_cd_0_grp"; 345 bias-high-impedance; 346 bias-pull-up; 347 slew-rate = <SLEW_RATE_SLOW>; 348 power-source = <IO_STANDARD_LVCMOS18>; 349 }; 350 }; 351 352 pinctrl_uart0_default: uart0-default { 353 mux { 354 groups = "uart0_4_grp"; 355 function = "uart0"; 356 }; 357 358 conf { 359 groups = "uart0_4_grp"; 360 slew-rate = <SLEW_RATE_SLOW>; 361 power-source = <IO_STANDARD_LVCMOS18>; 362 drive-strength = <12>; 363 }; 364 365 conf-rx { 366 pins = "MIO18"; 367 bias-high-impedance; 368 }; 369 370 conf-tx { 371 pins = "MIO19"; 372 bias-disable; 373 }; 374 }; 375 376 pinctrl_uart1_default: uart1-default { 377 mux { 378 groups = "uart1_5_grp"; 379 function = "uart1"; 380 }; 381 382 conf { 383 groups = "uart1_5_grp"; 384 slew-rate = <SLEW_RATE_SLOW>; 385 power-source = <IO_STANDARD_LVCMOS18>; 386 drive-strength = <12>; 387 }; 388 389 conf-rx { 390 pins = "MIO21"; 391 bias-high-impedance; 392 }; 393 394 conf-tx { 395 pins = "MIO20"; 396 bias-disable; 397 }; 398 }; 399 400 pinctrl_usb0_default: usb0-default { 401 mux { 402 groups = "usb0_0_grp"; 403 function = "usb0"; 404 }; 405 406 conf { 407 groups = "usb0_0_grp"; 408 slew-rate = <SLEW_RATE_SLOW>; 409 power-source = <IO_STANDARD_LVCMOS18>; 410 drive-strength = <12>; 411 }; 412 413 conf-rx { 414 pins = "MIO52", "MIO53", "MIO55"; 415 bias-high-impedance; 416 }; 417 418 conf-tx { 419 pins = "MIO54", "MIO56", "MIO57", "MIO58", "MIO59", 420 "MIO60", "MIO61", "MIO62", "MIO63"; 421 bias-disable; 422 }; 423 }; 424}; 425 426&qspi { 427 status = "okay"; 428 flash@0 { 429 compatible = "m25p80", "jedec,spi-nor"; /* n25q512a 128MiB */ 430 #address-cells = <1>; 431 #size-cells = <1>; 432 reg = <0x0>; 433 spi-tx-bus-width = <1>; 434 spi-rx-bus-width = <4>; 435 spi-max-frequency = <108000000>; /* Based on DC1 spec */ 436 partition@0 { /* for testing purpose */ 437 label = "qspi-fsbl-uboot"; 438 reg = <0x0 0x100000>; 439 }; 440 partition@100000 { /* for testing purpose */ 441 label = "qspi-linux"; 442 reg = <0x100000 0x500000>; 443 }; 444 partition@600000 { /* for testing purpose */ 445 label = "qspi-device-tree"; 446 reg = <0x600000 0x20000>; 447 }; 448 partition@620000 { /* for testing purpose */ 449 label = "qspi-rootfs"; 450 reg = <0x620000 0x5E0000>; 451 }; 452 }; 453}; 454 455&psgtr { 456 status = "okay"; 457 /* nc, sata, usb3, dp */ 458 clocks = <&clock_8t49n287_5>, <&clock_8t49n287_2>, <&clock_8t49n287_3>; 459 clock-names = "ref1", "ref2", "ref3"; 460}; 461 462&rtc { 463 status = "okay"; 464}; 465 466&sata { 467 status = "okay"; 468 /* SATA OOB timing settings */ 469 ceva,p0-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>; 470 ceva,p0-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>; 471 ceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>; 472 ceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>; 473 ceva,p1-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>; 474 ceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>; 475 ceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>; 476 ceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>; 477 phy-names = "sata-phy"; 478 phys = <&psgtr 3 PHY_TYPE_SATA 1 1>; 479}; 480 481/* SD1 with level shifter */ 482&sdhci1 { 483 status = "okay"; 484 no-1-8-v; 485 pinctrl-names = "default"; 486 pinctrl-0 = <&pinctrl_sdhci1_default>; 487 xlnx,mio-bank = <1>; 488 disable-wp; 489}; 490 491&uart0 { 492 status = "okay"; 493 pinctrl-names = "default"; 494 pinctrl-0 = <&pinctrl_uart0_default>; 495}; 496 497&uart1 { 498 status = "okay"; 499 pinctrl-names = "default"; 500 pinctrl-0 = <&pinctrl_uart1_default>; 501}; 502 503/* ULPI SMSC USB3320 */ 504&usb0 { 505 status = "okay"; 506 pinctrl-names = "default"; 507 pinctrl-0 = <&pinctrl_usb0_default>; 508}; 509 510&dwc3_0 { 511 status = "okay"; 512 dr_mode = "host"; 513 snps,usb3_lpm_capable; 514 phy-names = "usb3-phy"; 515 phys = <&psgtr 2 PHY_TYPE_USB3 0 2>; 516 maximum-speed = "super-speed"; 517}; 518 519&watchdog0 { 520 status = "okay"; 521}; 522 523&xilinx_ams { 524 status = "okay"; 525}; 526 527&ams_ps { 528 status = "okay"; 529}; 530 531&ams_pl { 532 status = "okay"; 533}; 534 535&zynqmp_dpdma { 536 status = "okay"; 537}; 538 539&zynqmp_dpsub { 540 status = "okay"; 541 phy-names = "dp-phy0", "dp-phy1"; 542 phys = <&psgtr 1 PHY_TYPE_DP 0 3>, 543 <&psgtr 0 PHY_TYPE_DP 1 3>; 544}; 545