1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * (C) Copyright 2018 Rockchip Electronics Co., Ltd. 4 */ 5 #ifndef _ASM_ARCH_CRU_RK3308_H 6 #define _ASM_ARCH_CRU_RK3308_H 7 8 #define MHz 1000000 9 #define OSC_HZ (24 * MHz) 10 11 #define APLL_HZ (816 * MHz) 12 13 #define CORE_ACLK_HZ 408000000 14 #define CORE_DBG_HZ 204000000 15 16 #define BUS_ACLK_HZ 200000000 17 #define BUS_HCLK_HZ 100000000 18 #define BUS_PCLK_HZ 100000000 19 20 #define PERI_ACLK_HZ 200000000 21 #define PERI_HCLK_HZ 100000000 22 #define PERI_PCLK_HZ 100000000 23 24 #define AUDIO_HCLK_HZ 100000000 25 #define AUDIO_PCLK_HZ 100000000 26 27 #define RK3308_PLL_CON(x) ((x) * 0x4) 28 #define RK3308_MODE_CON 0xa0 29 30 /* RK3308 pll id */ 31 enum rk3308_pll_id { 32 APLL, 33 DPLL, 34 VPLL0, 35 VPLL1, 36 PLL_COUNT, 37 }; 38 39 struct rk3308_clk_info { 40 unsigned long id; 41 char *name; 42 }; 43 44 /* Private data for the clock driver - used by rockchip_get_cru() */ 45 struct rk3308_clk_priv { 46 struct rk3308_cru *cru; 47 ulong armclk_hz; 48 ulong dpll_hz; 49 ulong vpll0_hz; 50 ulong vpll1_hz; 51 }; 52 53 struct rk3308_cru { 54 struct rk3308_pll { 55 unsigned int con0; 56 unsigned int con1; 57 unsigned int con2; 58 unsigned int con3; 59 unsigned int con4; 60 unsigned int reserved0[3]; 61 } pll[4]; 62 unsigned int reserved1[8]; 63 unsigned int mode; 64 unsigned int misc; 65 unsigned int reserved2[2]; 66 unsigned int glb_cnt_th; 67 unsigned int glb_rst_st; 68 unsigned int glb_srst_fst; 69 unsigned int glb_srst_snd; 70 unsigned int glb_rst_con; 71 unsigned int pll_lock; 72 unsigned int reserved3[6]; 73 unsigned int hwffc_con0; 74 unsigned int reserved4; 75 unsigned int hwffc_th; 76 unsigned int hwffc_intst; 77 unsigned int apll_con0_s; 78 unsigned int apll_con1_s; 79 unsigned int clksel_con0_s; 80 unsigned int reserved5; 81 unsigned int clksel_con[74]; 82 unsigned int reserved6[54]; 83 unsigned int clkgate_con[15]; 84 unsigned int reserved7[(0x380 - 0x338) / 4 - 1]; 85 unsigned int ssgtbl[32]; 86 unsigned int softrst_con[10]; 87 unsigned int reserved8[(0x480 - 0x424) / 4 - 1]; 88 unsigned int sdmmc_con[2]; 89 unsigned int sdio_con[2]; 90 unsigned int emmc_con[2]; 91 }; 92 93 enum { 94 /* PLLCON0*/ 95 PLL_BP_SHIFT = 15, 96 PLL_POSTDIV1_SHIFT = 12, 97 PLL_POSTDIV1_MASK = 7 << PLL_POSTDIV1_SHIFT, 98 PLL_FBDIV_SHIFT = 0, 99 PLL_FBDIV_MASK = 0xfff, 100 101 /* PLLCON1 */ 102 PLL_PDSEL_SHIFT = 15, 103 PLL_PD1_SHIFT = 14, 104 PLL_PD_SHIFT = 13, 105 PLL_PD_MASK = 1 << PLL_PD_SHIFT, 106 PLL_DSMPD_SHIFT = 12, 107 PLL_DSMPD_MASK = 1 << PLL_DSMPD_SHIFT, 108 PLL_LOCK_STATUS_SHIFT = 10, 109 PLL_LOCK_STATUS_MASK = 1 << PLL_LOCK_STATUS_SHIFT, 110 PLL_POSTDIV2_SHIFT = 6, 111 PLL_POSTDIV2_MASK = 7 << PLL_POSTDIV2_SHIFT, 112 PLL_REFDIV_SHIFT = 0, 113 PLL_REFDIV_MASK = 0x3f, 114 115 /* PLLCON2 */ 116 PLL_FOUT4PHASEPD_SHIFT = 27, 117 PLL_FOUTVCOPD_SHIFT = 26, 118 PLL_FOUTPOSTDIVPD_SHIFT = 25, 119 PLL_DACPD_SHIFT = 24, 120 PLL_FRAC_DIV = 0xffffff, 121 122 /* CRU_MODE */ 123 PLLMUX_FROM_XIN24M = 0, 124 PLLMUX_FROM_PLL, 125 PLLMUX_FROM_RTC32K, 126 USBPHY480M_MODE_SHIFT = 8, 127 USBPHY480M_MODE_MASK = 3 << USBPHY480M_MODE_SHIFT, 128 VPLL1_MODE_SHIFT = 6, 129 VPLL1_MODE_MASK = 3 << VPLL1_MODE_SHIFT, 130 VPLL0_MODE_SHIFT = 4, 131 VPLL0_MODE_MASK = 3 << VPLL0_MODE_SHIFT, 132 DPLL_MODE_SHIFT = 2, 133 DPLL_MODE_MASK = 3 << DPLL_MODE_SHIFT, 134 APLL_MODE_SHIFT = 0, 135 APLL_MODE_MASK = 3 << APLL_MODE_SHIFT, 136 137 /* CRU_CLK_SEL0_CON */ 138 CORE_ACLK_DIV_SHIFT = 12, 139 CORE_ACLK_DIV_MASK = 0x7 << CORE_ACLK_DIV_SHIFT, 140 CORE_DBG_DIV_SHIFT = 8, 141 CORE_DBG_DIV_MASK = 0xf << CORE_DBG_DIV_SHIFT, 142 CORE_CLK_PLL_SEL_SHIFT = 6, 143 CORE_CLK_PLL_SEL_MASK = 0x3 << CORE_CLK_PLL_SEL_SHIFT, 144 CORE_CLK_PLL_SEL_APLL = 0, 145 CORE_CLK_PLL_SEL_VPLL0, 146 CORE_CLK_PLL_SEL_VPLL1, 147 CORE_DIV_CON_SHIFT = 0, 148 CORE_DIV_CON_MASK = 0x0f << CORE_DIV_CON_SHIFT, 149 150 /* CRU_CLK_SEL5_CON */ 151 BUS_PLL_SEL_SHIFT = 6, 152 BUS_PLL_SEL_MASK = 0x3 << BUS_PLL_SEL_SHIFT, 153 BUS_PLL_SEL_DPLL = 0, 154 BUS_PLL_SEL_VPLL0, 155 BUS_PLL_SEL_VPLL1, 156 BUS_ACLK_DIV_SHIFT = 0, 157 BUS_ACLK_DIV_MASK = 0x1f << BUS_ACLK_DIV_SHIFT, 158 159 /* CRU_CLK_SEL6_CON */ 160 BUS_PCLK_DIV_SHIFT = 8, 161 BUS_PCLK_DIV_MASK = 0x1f << BUS_PCLK_DIV_SHIFT, 162 BUS_HCLK_DIV_SHIFT = 0, 163 BUS_HCLK_DIV_MASK = 0x1f << BUS_HCLK_DIV_SHIFT, 164 165 /* CRU_CLK_SEL7_CON */ 166 CRYPTO_APK_SEL_SHIFT = 14, 167 CRYPTO_APK_PLL_SEL_MASK = 3 << CRYPTO_APK_SEL_SHIFT, 168 CRYPTO_PLL_SEL_DPLL = 0, 169 CRYPTO_PLL_SEL_VPLL0, 170 CRYPTO_PLL_SEL_VPLL1 = 0, 171 CRYPTO_APK_DIV_SHIFT = 8, 172 CRYPTO_APK_DIV_MASK = 0x1f << CRYPTO_APK_DIV_SHIFT, 173 CRYPTO_PLL_SEL_SHIFT = 6, 174 CRYPTO_PLL_SEL_MASK = 3 << CRYPTO_PLL_SEL_SHIFT, 175 CRYPTO_DIV_SHIFT = 0, 176 CRYPTO_DIV_MASK = 0x1f << CRYPTO_DIV_SHIFT, 177 178 /* CRU_CLK_SEL8_CON */ 179 DCLK_VOP_SEL_SHIFT = 14, 180 DCLK_VOP_SEL_MASK = 0x3 << DCLK_VOP_SEL_SHIFT, 181 DCLK_VOP_SEL_DIVOUT = 0, 182 DCLK_VOP_SEL_FRACOUT, 183 DCLK_VOP_SEL_24M, 184 DCLK_VOP_PLL_SEL_SHIFT = 10, 185 DCLK_VOP_PLL_SEL_MASK = 0x3 << DCLK_VOP_PLL_SEL_SHIFT, 186 DCLK_VOP_PLL_SEL_DPLL = 0, 187 DCLK_VOP_PLL_SEL_VPLL0, 188 DCLK_VOP_PLL_SEL_VPLL1, 189 DCLK_VOP_DIV_SHIFT = 0, 190 DCLK_VOP_DIV_MASK = 0xff, 191 192 /* CRU_CLK_SEL25_CON */ 193 /* CRU_CLK_SEL26_CON */ 194 /* CRU_CLK_SEL27_CON */ 195 /* CRU_CLK_SEL28_CON */ 196 CLK_I2C_PLL_SEL_SHIFT = 14, 197 CLK_I2C_PLL_SEL_MASK = 0x3 << CLK_I2C_PLL_SEL_SHIFT, 198 CLK_I2C_PLL_SEL_DPLL = 0, 199 CLK_I2C_PLL_SEL_VPLL0, 200 CLK_I2C_PLL_SEL_24M, 201 CLK_I2C_DIV_CON_SHIFT = 0, 202 CLK_I2C_DIV_CON_MASK = 0x7f << CLK_I2C_DIV_CON_SHIFT, 203 204 /* CRU_CLK_SEL29_CON */ 205 CLK_PWM_PLL_SEL_SHIFT = 14, 206 CLK_PWM_PLL_SEL_MASK = 0x3 << CLK_PWM_PLL_SEL_SHIFT, 207 CLK_PWM_PLL_SEL_DPLL = 0, 208 CLK_PWM_PLL_SEL_VPLL0, 209 CLK_PWM_PLL_SEL_24M, 210 CLK_PWM_DIV_CON_SHIFT = 0, 211 CLK_PWM_DIV_CON_MASK = 0x7f << CLK_PWM_DIV_CON_SHIFT, 212 213 /* CRU_CLK_SEL30_CON */ 214 /* CRU_CLK_SEL31_CON */ 215 /* CRU_CLK_SEL32_CON */ 216 CLK_SPI_PLL_SEL_SHIFT = 14, 217 CLK_SPI_PLL_SEL_MASK = 0x3 << CLK_SPI_PLL_SEL_SHIFT, 218 CLK_SPI_PLL_SEL_DPLL = 0, 219 CLK_SPI_PLL_SEL_VPLL0, 220 CLK_SPI_PLL_SEL_24M, 221 CLK_SPI_DIV_CON_SHIFT = 0, 222 CLK_SPI_DIV_CON_MASK = 0x7f << CLK_SPI_DIV_CON_SHIFT, 223 224 /* CRU_CLK_SEL34_CON */ 225 CLK_SARADC_DIV_CON_SHIFT = 0, 226 CLK_SARADC_DIV_CON_MASK = 0x7ff << CLK_SARADC_DIV_CON_SHIFT, 227 228 /* CRU_CLK_SEL36_CON */ 229 PERI_PLL_SEL_SHIFT = 6, 230 PERI_PLL_SEL_MASK = 0x3 << PERI_PLL_SEL_SHIFT, 231 PERI_PLL_DPLL = 0, 232 PERI_PLL_VPLL0, 233 PERI_PLL_VPLL1, 234 PERI_ACLK_DIV_SHIFT = 0, 235 PERI_ACLK_DIV_MASK = 0x1f << PERI_ACLK_DIV_SHIFT, 236 237 /* CRU_CLK_SEL37_CON */ 238 PERI_PCLK_DIV_SHIFT = 8, 239 PERI_PCLK_DIV_MASK = 0x1f << PERI_PCLK_DIV_SHIFT, 240 PERI_HCLK_DIV_SHIFT = 0, 241 PERI_HCLK_DIV_MASK = 0x1f << PERI_HCLK_DIV_SHIFT, 242 243 /* CRU_CLKSEL41_CON */ 244 EMMC_CLK_SEL_SHIFT = 15, 245 EMMC_CLK_SEL_MASK = 1 << EMMC_CLK_SEL_SHIFT, 246 EMMC_CLK_SEL_EMMC = 0, 247 EMMC_CLK_SEL_EMMC_DIV50, 248 EMMC_PLL_SHIFT = 8, 249 EMMC_PLL_MASK = 0x3 << EMMC_PLL_SHIFT, 250 EMMC_SEL_DPLL = 0, 251 EMMC_SEL_VPLL0, 252 EMMC_SEL_VPLL1, 253 EMMC_SEL_24M, 254 EMMC_DIV_SHIFT = 0, 255 EMMC_DIV_MASK = 0xff << EMMC_DIV_SHIFT, 256 257 /* CRU_CLKSEL43_CON */ 258 MAC_CLK_SPEED_SEL_SHIFT = 15, 259 MAC_CLK_SPEED_SEL_MASK = 1 << MAC_CLK_SPEED_SEL_SHIFT, 260 MAC_CLK_SPEED_SEL_10M = 0, 261 MAC_CLK_SPEED_SEL_100M, 262 MAC_CLK_SOURCE_SEL_SHIFT = 14, 263 MAC_CLK_SOURCE_SEL_MASK = 1 << MAC_CLK_SOURCE_SEL_SHIFT, 264 MAC_CLK_SOURCE_SEL_INTERNAL = 0, 265 MAC_CLK_SOURCE_SEL_EXTERNAL, 266 MAC_PLL_SHIFT = 6, 267 MAC_PLL_MASK = 0x3 << MAC_PLL_SHIFT, 268 MAC_SEL_DPLL = 0, 269 MAC_SEL_VPLL0, 270 MAC_SEL_VPLL1, 271 MAC_DIV_SHIFT = 0, 272 MAC_DIV_MASK = 0x1f << MAC_DIV_SHIFT, 273 274 /* CRU_CLK_SEL45_CON */ 275 AUDIO_PCLK_DIV_SHIFT = 8, 276 AUDIO_PCLK_DIV_MASK = 0x1f << AUDIO_PCLK_DIV_SHIFT, 277 AUDIO_PLL_SEL_SHIFT = 6, 278 AUDIO_PLL_SEL_MASK = 0x3 << AUDIO_PLL_SEL_SHIFT, 279 AUDIO_PLL_VPLL0 = 0, 280 AUDIO_PLL_VPLL1, 281 AUDIO_PLL_24M, 282 AUDIO_HCLK_DIV_SHIFT = 0, 283 AUDIO_HCLK_DIV_MASK = 0x1f << AUDIO_HCLK_DIV_SHIFT, 284 }; 285 286 check_member(rk3308_cru, emmc_con[1], 0x494); 287 288 #endif 289