1 /* SPDX-License-Identifier: GPL-2.0+ */
2 /*
3 * Copyright(C) 2020
4 * Author(s): Giulio Benetti <giulio.benetti@benettiengineering.com>
5 */
6
7 #include <common.h>
8 #include <clk.h>
9 #include <clk-uclass.h>
10 #include <dm.h>
11 #include <asm/arch/clock.h>
12 #include <asm/arch/imx-regs.h>
13 #include <dt-bindings/clock/imxrt1020-clock.h>
14
15 #include "clk.h"
16
imxrt1020_clk_get_rate(struct clk * clk)17 static ulong imxrt1020_clk_get_rate(struct clk *clk)
18 {
19 struct clk *c;
20 int ret;
21
22 debug("%s(#%lu)\n", __func__, clk->id);
23
24 ret = clk_get_by_id(clk->id, &c);
25 if (ret)
26 return ret;
27
28 return clk_get_rate(c);
29 }
30
imxrt1020_clk_set_rate(struct clk * clk,unsigned long rate)31 static ulong imxrt1020_clk_set_rate(struct clk *clk, unsigned long rate)
32 {
33 struct clk *c;
34 int ret;
35
36 debug("%s(#%lu), rate: %lu\n", __func__, clk->id, rate);
37
38 ret = clk_get_by_id(clk->id, &c);
39 if (ret)
40 return ret;
41
42 return clk_set_rate(c, rate);
43 }
44
__imxrt1020_clk_enable(struct clk * clk,bool enable)45 static int __imxrt1020_clk_enable(struct clk *clk, bool enable)
46 {
47 struct clk *c;
48 int ret;
49
50 debug("%s(#%lu) en: %d\n", __func__, clk->id, enable);
51
52 ret = clk_get_by_id(clk->id, &c);
53 if (ret)
54 return ret;
55
56 if (enable)
57 ret = clk_enable(c);
58 else
59 ret = clk_disable(c);
60
61 return ret;
62 }
63
imxrt1020_clk_disable(struct clk * clk)64 static int imxrt1020_clk_disable(struct clk *clk)
65 {
66 return __imxrt1020_clk_enable(clk, 0);
67 }
68
imxrt1020_clk_enable(struct clk * clk)69 static int imxrt1020_clk_enable(struct clk *clk)
70 {
71 return __imxrt1020_clk_enable(clk, 1);
72 }
73
74 static struct clk_ops imxrt1020_clk_ops = {
75 .set_rate = imxrt1020_clk_set_rate,
76 .get_rate = imxrt1020_clk_get_rate,
77 .enable = imxrt1020_clk_enable,
78 .disable = imxrt1020_clk_disable,
79 };
80
81 static const char * const pll2_bypass_sels[] = {"pll2_sys", "osc", };
82 static const char * const pll3_bypass_sels[] = {"pll3_usb_otg", "osc", };
83
84 static const char *const pre_periph_sels[] = { "pll2_sys", "pll2_pfd3_297m", "pll3_pfd3_454_74m", "arm_podf", };
85 static const char *const periph_sels[] = { "pre_periph_sel", "todo", };
86 static const char *const usdhc_sels[] = { "pll2_pfd2_396m", "pll2_pfd0_352m", };
87 static const char *const lpuart_sels[] = { "pll3_80m", "osc", };
88 static const char *const semc_alt_sels[] = { "pll2_pfd2_396m", "pll3_pfd1_664_62m", };
89 static const char *const semc_sels[] = { "periph_sel", "semc_alt_sel", };
90
imxrt1020_clk_probe(struct udevice * dev)91 static int imxrt1020_clk_probe(struct udevice *dev)
92 {
93 void *base;
94
95 /* Anatop clocks */
96 base = (void *)ANATOP_BASE_ADDR;
97
98 clk_dm(IMXRT1020_CLK_PLL2_SYS,
99 imx_clk_pllv3(IMX_PLLV3_GENERIC, "pll2_sys", "osc",
100 base + 0x30, 0x1));
101 clk_dm(IMXRT1020_CLK_PLL3_USB_OTG,
102 imx_clk_pllv3(IMX_PLLV3_USB, "pll3_usb_otg", "osc",
103 base + 0x10, 0x1));
104
105 /* PLL bypass out */
106 clk_dm(IMXRT1020_CLK_PLL2_BYPASS,
107 imx_clk_mux_flags("pll2_bypass", base + 0x30, 16, 1,
108 pll2_bypass_sels,
109 ARRAY_SIZE(pll2_bypass_sels),
110 CLK_SET_RATE_PARENT));
111 clk_dm(IMXRT1020_CLK_PLL3_BYPASS,
112 imx_clk_mux_flags("pll3_bypass", base + 0x10, 16, 1,
113 pll3_bypass_sels,
114 ARRAY_SIZE(pll3_bypass_sels),
115 CLK_SET_RATE_PARENT));
116
117 clk_dm(IMXRT1020_CLK_PLL3_80M,
118 imx_clk_fixed_factor("pll3_80m", "pll3_usb_otg", 1, 6));
119
120 clk_dm(IMXRT1020_CLK_PLL2_PFD0_352M,
121 imx_clk_pfd("pll2_pfd0_352m", "pll2_sys", base + 0x100, 0));
122 clk_dm(IMXRT1020_CLK_PLL2_PFD1_594M,
123 imx_clk_pfd("pll2_pfd1_594m", "pll2_sys", base + 0x100, 1));
124 clk_dm(IMXRT1020_CLK_PLL2_PFD2_396M,
125 imx_clk_pfd("pll2_pfd2_396m", "pll2_sys", base + 0x100, 2));
126 clk_dm(IMXRT1020_CLK_PLL2_PFD3_297M,
127 imx_clk_pfd("pll2_pfd3_297m", "pll2_sys", base + 0x100, 3));
128 clk_dm(IMXRT1020_CLK_PLL3_PFD1_664_62M,
129 imx_clk_pfd("pll3_pfd1_664_62m", "pll3_usb_otg", base + 0xf0, 1));
130 clk_dm(IMXRT1020_CLK_PLL3_PFD3_454_74M,
131 imx_clk_pfd("pll3_pfd3_454_74m", "pll3_usb_otg", base + 0xf0, 3));
132
133 /* CCM clocks */
134 base = dev_read_addr_ptr(dev);
135 if (base == (void *)FDT_ADDR_T_NONE)
136 return -EINVAL;
137
138 clk_dm(IMXRT1020_CLK_PRE_PERIPH_SEL,
139 imx_clk_mux("pre_periph_sel", base + 0x18, 18, 2,
140 pre_periph_sels, ARRAY_SIZE(pre_periph_sels)));
141 clk_dm(IMXRT1020_CLK_PERIPH_SEL,
142 imx_clk_mux("periph_sel", base + 0x14, 25, 1,
143 periph_sels, ARRAY_SIZE(periph_sels)));
144 clk_dm(IMXRT1020_CLK_USDHC1_SEL,
145 imx_clk_mux("usdhc1_sel", base + 0x1c, 16, 1,
146 usdhc_sels, ARRAY_SIZE(usdhc_sels)));
147 clk_dm(IMXRT1020_CLK_USDHC2_SEL,
148 imx_clk_mux("usdhc2_sel", base + 0x1c, 17, 1,
149 usdhc_sels, ARRAY_SIZE(usdhc_sels)));
150 clk_dm(IMXRT1020_CLK_LPUART_SEL,
151 imx_clk_mux("lpuart_sel", base + 0x24, 6, 1,
152 lpuart_sels, ARRAY_SIZE(lpuart_sels)));
153 clk_dm(IMXRT1020_CLK_SEMC_ALT_SEL,
154 imx_clk_mux("semc_alt_sel", base + 0x14, 7, 1,
155 semc_alt_sels, ARRAY_SIZE(semc_alt_sels)));
156 clk_dm(IMXRT1020_CLK_SEMC_SEL,
157 imx_clk_mux("semc_sel", base + 0x14, 6, 1,
158 semc_sels, ARRAY_SIZE(semc_sels)));
159
160 clk_dm(IMXRT1020_CLK_AHB_PODF,
161 imx_clk_divider("ahb_podf", "periph_sel",
162 base + 0x14, 10, 3));
163 clk_dm(IMXRT1020_CLK_USDHC1_PODF,
164 imx_clk_divider("usdhc1_podf", "usdhc1_sel",
165 base + 0x24, 11, 3));
166 clk_dm(IMXRT1020_CLK_USDHC2_PODF,
167 imx_clk_divider("usdhc2_podf", "usdhc2_sel",
168 base + 0x24, 16, 3));
169 clk_dm(IMXRT1020_CLK_LPUART_PODF,
170 imx_clk_divider("lpuart_podf", "lpuart_sel",
171 base + 0x24, 0, 6));
172 clk_dm(IMXRT1020_CLK_SEMC_PODF,
173 imx_clk_divider("semc_podf", "semc_sel",
174 base + 0x14, 16, 3));
175
176 clk_dm(IMXRT1020_CLK_USDHC1,
177 imx_clk_gate2("usdhc1", "usdhc1_podf", base + 0x80, 2));
178 clk_dm(IMXRT1020_CLK_USDHC2,
179 imx_clk_gate2("usdhc2", "usdhc2_podf", base + 0x80, 4));
180 clk_dm(IMXRT1020_CLK_LPUART1,
181 imx_clk_gate2("lpuart1", "lpuart_podf", base + 0x7c, 24));
182 clk_dm(IMXRT1020_CLK_SEMC,
183 imx_clk_gate2("semc", "semc_podf", base + 0x74, 4));
184
185 #ifdef CONFIG_SPL_BUILD
186 struct clk *clk, *clk1;
187
188 clk_get_by_id(IMXRT1020_CLK_SEMC_SEL, &clk1);
189 clk_get_by_id(IMXRT1020_CLK_SEMC_ALT_SEL, &clk);
190 clk_set_parent(clk1, clk);
191
192 /* Configure PLL3_USB_OTG to 480MHz */
193 clk_get_by_id(IMXRT1020_CLK_PLL3_USB_OTG, &clk);
194 clk_enable(clk);
195 clk_set_rate(clk, 480000000UL);
196
197 clk_get_by_id(IMXRT1020_CLK_PLL3_BYPASS, &clk1);
198 clk_set_parent(clk1, clk);
199
200 clk_get_by_id(IMXRT1020_CLK_PLL2_PFD3_297M, &clk);
201 clk_set_rate(clk, 297000000UL);
202
203 clk_get_by_id(IMXRT1020_CLK_PLL2_SYS, &clk);
204 clk_enable(clk);
205 clk_set_rate(clk, 528000000UL);
206
207 clk_get_by_id(IMXRT1020_CLK_PLL2_BYPASS, &clk1);
208 clk_set_parent(clk1, clk);
209
210 #endif
211
212 return 0;
213 }
214
215 static const struct udevice_id imxrt1020_clk_ids[] = {
216 { .compatible = "fsl,imxrt1020-ccm" },
217 { },
218 };
219
220 U_BOOT_DRIVER(imxrt1020_clk) = {
221 .name = "clk_imxrt1020",
222 .id = UCLASS_CLK,
223 .of_match = imxrt1020_clk_ids,
224 .ops = &imxrt1020_clk_ops,
225 .probe = imxrt1020_clk_probe,
226 .flags = DM_FLAG_PRE_RELOC,
227 };
228