1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Copyright 2016 Freescale Semiconductor, Inc.
4 */
5 #include <common.h>
6 #include <phy.h>
7 #include <fm_eth.h>
8 #include <asm/io.h>
9 #include <asm/arch/fsl_serdes.h>
10
11 #define FSL_CHASSIS2_RCWSR13_EC1 0xe0000000 /* bits 416..418 */
12 #define FSL_CHASSIS2_RCWSR13_EC1_DTSEC3_RGMII 0x00000000
13 #define FSL_CHASSIS2_RCWSR13_EC1_GPIO 0x20000000
14 #define FSL_CHASSIS2_RCWSR13_EC1_FTM 0xa0000000
15 #define FSL_CHASSIS2_RCWSR13_EC2 0x1c000000 /* bits 419..421 */
16 #define FSL_CHASSIS2_RCWSR13_EC2_DTSEC4_RGMII 0x00000000
17 #define FSL_CHASSIS2_RCWSR13_EC2_GPIO 0x04000000
18 #define FSL_CHASSIS2_RCWSR13_EC2_1588 0x08000000
19 #define FSL_CHASSIS2_RCWSR13_EC2_FTM 0x14000000
20
21 u32 port_to_devdisr[] = {
22 [FM1_DTSEC1] = FSL_CHASSIS2_DEVDISR2_DTSEC1_1,
23 [FM1_DTSEC2] = FSL_CHASSIS2_DEVDISR2_DTSEC1_2,
24 [FM1_DTSEC3] = FSL_CHASSIS2_DEVDISR2_DTSEC1_3,
25 [FM1_DTSEC4] = FSL_CHASSIS2_DEVDISR2_DTSEC1_4,
26 [FM1_DTSEC5] = FSL_CHASSIS2_DEVDISR2_DTSEC1_5,
27 [FM1_DTSEC6] = FSL_CHASSIS2_DEVDISR2_DTSEC1_6,
28 [FM1_DTSEC9] = FSL_CHASSIS2_DEVDISR2_DTSEC1_9,
29 [FM1_DTSEC10] = FSL_CHASSIS2_DEVDISR2_DTSEC1_10,
30 [FM1_10GEC1] = FSL_CHASSIS2_DEVDISR2_10GEC1_1,
31 [FM1_10GEC2] = FSL_CHASSIS2_DEVDISR2_10GEC1_2,
32 [FM1_10GEC3] = FSL_CHASSIS2_DEVDISR2_10GEC1_3,
33 [FM1_10GEC4] = FSL_CHASSIS2_DEVDISR2_10GEC1_4,
34 };
35
is_device_disabled(enum fm_port port)36 static int is_device_disabled(enum fm_port port)
37 {
38 struct ccsr_gur *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
39 u32 devdisr2 = in_be32(&gur->devdisr2);
40
41 return port_to_devdisr[port] & devdisr2;
42 }
43
fman_disable_port(enum fm_port port)44 void fman_disable_port(enum fm_port port)
45 {
46 struct ccsr_gur *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
47
48 setbits_be32(&gur->devdisr2, port_to_devdisr[port]);
49 }
50
fman_port_enet_if(enum fm_port port)51 phy_interface_t fman_port_enet_if(enum fm_port port)
52 {
53 struct ccsr_gur *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
54 u32 rcwsr13 = in_be32(&gur->rcwsr[13]);
55
56 if (is_device_disabled(port))
57 return PHY_INTERFACE_MODE_NONE;
58
59 if ((port == FM1_10GEC1) && (is_serdes_configured(XFI_FM1_MAC9)))
60 return PHY_INTERFACE_MODE_XGMII;
61
62 if ((port == FM1_DTSEC9) && (is_serdes_configured(XFI_FM1_MAC9)))
63 return PHY_INTERFACE_MODE_NONE;
64
65 if ((port == FM1_10GEC2) && (is_serdes_configured(XFI_FM1_MAC10)))
66 return PHY_INTERFACE_MODE_XGMII;
67
68 if ((port == FM1_DTSEC10) && (is_serdes_configured(XFI_FM1_MAC10)))
69 return PHY_INTERFACE_MODE_NONE;
70
71 if (port == FM1_DTSEC3)
72 if ((rcwsr13 & FSL_CHASSIS2_RCWSR13_EC1) ==
73 FSL_CHASSIS2_RCWSR13_EC1_DTSEC3_RGMII)
74 return PHY_INTERFACE_MODE_RGMII_ID;
75
76 if (port == FM1_DTSEC4)
77 if ((rcwsr13 & FSL_CHASSIS2_RCWSR13_EC2) ==
78 FSL_CHASSIS2_RCWSR13_EC2_DTSEC4_RGMII)
79 return PHY_INTERFACE_MODE_RGMII_ID;
80
81 /* handle SGMII, only MAC 2/5/6/9/10 available */
82 switch (port) {
83 case FM1_DTSEC2:
84 case FM1_DTSEC5:
85 case FM1_DTSEC6:
86 case FM1_DTSEC9:
87 case FM1_DTSEC10:
88 if (is_serdes_configured(SGMII_FM1_DTSEC2 + port - FM1_DTSEC2))
89 return PHY_INTERFACE_MODE_SGMII;
90 break;
91 default:
92 break;
93 }
94
95 /* handle 2.5G SGMII, only MAC 5/9/10 available */
96 switch (port) {
97 case FM1_DTSEC5:
98 case FM1_DTSEC9:
99 case FM1_DTSEC10:
100 if (is_serdes_configured(SGMII_2500_FM1_DTSEC5 +
101 port - FM1_DTSEC5))
102 return PHY_INTERFACE_MODE_SGMII_2500;
103 break;
104 default:
105 break;
106 }
107
108 /* handle QSGMII, only MAC 1/5/6/10 available */
109 switch (port) {
110 case FM1_DTSEC1:
111 case FM1_DTSEC5:
112 case FM1_DTSEC6:
113 case FM1_DTSEC10:
114 if (is_serdes_configured(QSGMII_FM1_A))
115 return PHY_INTERFACE_MODE_QSGMII;
116 break;
117 default:
118 break;
119 }
120
121 return PHY_INTERFACE_MODE_NONE;
122 }
123