1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Copyright (c) 2019
4 * Written by Ramon Fried <ramon.fried@gmail.com>
5 */
6
7 #include <common.h>
8 #include <dm.h>
9 #include <errno.h>
10 #include <pci_ep.h>
11 #include <asm/global_data.h>
12 #include <linux/sizes.h>
13 #include <linux/log2.h>
14 #include "pcie-cadence.h"
15
16 DECLARE_GLOBAL_DATA_PTR;
17
cdns_write_header(struct udevice * dev,uint fn,struct pci_ep_header * hdr)18 static int cdns_write_header(struct udevice *dev, uint fn,
19 struct pci_ep_header *hdr)
20 {
21 struct cdns_pcie *pcie = dev_get_priv(dev);
22
23 cdns_pcie_ep_fn_writew(pcie, fn, PCI_DEVICE_ID, hdr->deviceid);
24 cdns_pcie_ep_fn_writeb(pcie, fn, PCI_REVISION_ID, hdr->revid);
25 cdns_pcie_ep_fn_writeb(pcie, fn, PCI_CLASS_PROG,
26 hdr->progif_code);
27 cdns_pcie_ep_fn_writew(pcie, fn, PCI_CLASS_DEVICE,
28 hdr->subclass_code |
29 hdr->baseclass_code << 8);
30 cdns_pcie_ep_fn_writeb(pcie, fn, PCI_CACHE_LINE_SIZE,
31 hdr->cache_line_size);
32 cdns_pcie_ep_fn_writew(pcie, fn, PCI_SUBSYSTEM_ID,
33 hdr->subsys_id);
34 cdns_pcie_ep_fn_writeb(pcie, fn, PCI_INTERRUPT_PIN,
35 hdr->interrupt_pin);
36
37 /*
38 * Vendor ID can only be modified from function 0, all other functions
39 * use the same vendor ID as function 0.
40 */
41 if (fn == 0) {
42 /* Update the vendor IDs. */
43 u32 id = CDNS_PCIE_LM_ID_VENDOR(hdr->vendorid) |
44 CDNS_PCIE_LM_ID_SUBSYS(hdr->subsys_vendor_id);
45
46 cdns_pcie_writel(pcie, CDNS_PCIE_LM_ID, id);
47 }
48
49 return 0;
50 }
51
cdns_set_bar(struct udevice * dev,uint fn,struct pci_bar * ep_bar)52 static int cdns_set_bar(struct udevice *dev, uint fn, struct pci_bar *ep_bar)
53 {
54 struct cdns_pcie *pcie = dev_get_priv(dev);
55 dma_addr_t bar_phys = ep_bar->phys_addr;
56 enum pci_barno bar = ep_bar->barno;
57 int flags = ep_bar->flags;
58 u32 addr0, addr1, reg, cfg, b, aperture, ctrl;
59 u64 sz;
60
61 /* BAR size is 2^(aperture + 7) */
62 sz = max_t(size_t, ep_bar->size, CDNS_PCIE_EP_MIN_APERTURE);
63 /*
64 * roundup_pow_of_two() returns an unsigned long, which is not suited
65 * for 64bit values.
66 */
67 sz = 1ULL << fls64(sz - 1);
68 aperture = ilog2(sz) - 7; /* 128B -> 0, 256B -> 1, 512B -> 2, ... */
69
70 if ((flags & PCI_BASE_ADDRESS_SPACE) == PCI_BASE_ADDRESS_SPACE_IO) {
71 ctrl = CDNS_PCIE_LM_BAR_CFG_CTRL_IO_32BITS;
72 } else {
73 bool is_prefetch = !!(flags & PCI_BASE_ADDRESS_MEM_PREFETCH);
74 bool is_64bits = (sz > SZ_2G) |
75 !!(ep_bar->flags & PCI_BASE_ADDRESS_MEM_TYPE_64);
76
77 if (is_64bits && (bar & 1))
78 return -EINVAL;
79
80 if (is_64bits && !(flags & PCI_BASE_ADDRESS_MEM_TYPE_64))
81 ep_bar->flags |= PCI_BASE_ADDRESS_MEM_TYPE_64;
82
83 if (is_64bits && is_prefetch)
84 ctrl = CDNS_PCIE_LM_BAR_CFG_CTRL_PREFETCH_MEM_64BITS;
85 else if (is_prefetch)
86 ctrl = CDNS_PCIE_LM_BAR_CFG_CTRL_PREFETCH_MEM_32BITS;
87 else if (is_64bits)
88 ctrl = CDNS_PCIE_LM_BAR_CFG_CTRL_MEM_64BITS;
89 else
90 ctrl = CDNS_PCIE_LM_BAR_CFG_CTRL_MEM_32BITS;
91 }
92
93 addr0 = lower_32_bits(bar_phys);
94 addr1 = upper_32_bits(bar_phys);
95 cdns_pcie_writel(pcie, CDNS_PCIE_AT_IB_EP_FUNC_BAR_ADDR0(fn, bar),
96 addr0);
97 cdns_pcie_writel(pcie, CDNS_PCIE_AT_IB_EP_FUNC_BAR_ADDR1(fn, bar),
98 addr1);
99
100 if (bar < BAR_4) {
101 reg = CDNS_PCIE_LM_EP_FUNC_BAR_CFG0(fn);
102 b = bar;
103 } else {
104 reg = CDNS_PCIE_LM_EP_FUNC_BAR_CFG1(fn);
105 b = bar - BAR_4;
106 }
107
108 cfg = cdns_pcie_readl(pcie, reg);
109 cfg &= ~(CDNS_PCIE_LM_EP_FUNC_BAR_CFG_BAR_APERTURE_MASK(b) |
110 CDNS_PCIE_LM_EP_FUNC_BAR_CFG_BAR_CTRL_MASK(b));
111 cfg |= (CDNS_PCIE_LM_EP_FUNC_BAR_CFG_BAR_APERTURE(b, aperture) |
112 CDNS_PCIE_LM_EP_FUNC_BAR_CFG_BAR_CTRL(b, ctrl));
113 cdns_pcie_writel(pcie, reg, cfg);
114
115 return 0;
116 }
117
cdns_set_msi(struct udevice * dev,uint fn,uint mmc)118 static int cdns_set_msi(struct udevice *dev, uint fn, uint mmc)
119 {
120 struct cdns_pcie *pcie = dev_get_priv(dev);
121 u32 cap = CDNS_PCIE_EP_FUNC_MSI_CAP_OFFSET;
122
123 /*
124 * Set the Multiple Message Capable bitfield into the Message Control
125 * register.
126 */
127 u16 flags;
128
129 flags = cdns_pcie_ep_fn_readw(pcie, fn, cap + PCI_MSI_FLAGS);
130 flags = (flags & ~PCI_MSI_FLAGS_QMASK) | (mmc << 1);
131 flags |= PCI_MSI_FLAGS_64BIT;
132 flags &= ~PCI_MSI_FLAGS_MASKBIT;
133 cdns_pcie_ep_fn_writew(pcie, fn, cap + PCI_MSI_FLAGS, flags);
134
135 return 0;
136 }
137
138 static struct pci_ep_ops cdns_pci_ep_ops = {
139 .write_header = cdns_write_header,
140 .set_bar = cdns_set_bar,
141 .set_msi = cdns_set_msi,
142 };
143
cdns_pci_ep_probe(struct udevice * dev)144 static int cdns_pci_ep_probe(struct udevice *dev)
145 {
146 struct cdns_pcie *pdata = dev_get_priv(dev);
147
148 pdata->reg_base = dev_read_addr_ptr(dev);
149 if (!pdata->reg_base)
150 return -ENOMEM;
151
152 pdata->max_functions = fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev),
153 "max-functions", 1);
154 pdata->max_regions = fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev),
155 "cdns,max-outbound-regions", 8);
156
157 return 0;
158 }
159
cdns_pci_ep_remove(struct udevice * dev)160 static int cdns_pci_ep_remove(struct udevice *dev)
161 {
162 return 0;
163 }
164
165 const struct udevice_id cadence_pci_ep_of_match[] = {
166 { .compatible = "cdns,cdns-pcie-ep" },
167 { }
168 };
169
170 U_BOOT_DRIVER(cdns_pcie) = {
171 .name = "cdns,pcie-ep",
172 .id = UCLASS_PCI_EP,
173 .of_match = cadence_pci_ep_of_match,
174 .ops = &cdns_pci_ep_ops,
175 .probe = cdns_pci_ep_probe,
176 .remove = cdns_pci_ep_remove,
177 .priv_auto = sizeof(struct cdns_pcie),
178 };
179