1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * R8A77980 processor support - PFC hardware block.
4 *
5 * Copyright (C) 2018 Renesas Electronics Corp.
6 * Copyright (C) 2018 Cogent Embedded, Inc.
7 *
8 * This file is based on the drivers/pinctrl/renesas/pfc-r8a7795.c
9 *
10 * R-Car Gen3 processor support - PFC hardware block.
11 *
12 * Copyright (C) 2015 Renesas Electronics Corporation
13 */
14
15 #include <common.h>
16 #include <dm.h>
17 #include <errno.h>
18 #include <dm/pinctrl.h>
19 #include <linux/kernel.h>
20
21 #include "sh_pfc.h"
22
23 #define CPU_ALL_GP(fn, sfx) \
24 PORT_GP_CFG_22(0, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE), \
25 PORT_GP_28(1, fn, sfx), \
26 PORT_GP_CFG_30(2, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE), \
27 PORT_GP_CFG_17(3, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE), \
28 PORT_GP_25(4, fn, sfx), \
29 PORT_GP_15(5, fn, sfx)
30
31 /*
32 * F_() : just information
33 * FM() : macro for FN_xxx / xxx_MARK
34 */
35
36 /* GPSR0 */
37 #define GPSR0_21 F_(DU_EXODDF_DU_ODDF_DISP_CDE, IP2_23_20)
38 #define GPSR0_20 F_(DU_EXVSYNC_DU_VSYNC, IP2_19_16)
39 #define GPSR0_19 F_(DU_EXHSYNC_DU_HSYNC, IP2_15_12)
40 #define GPSR0_18 F_(DU_DOTCLKOUT, IP2_11_8)
41 #define GPSR0_17 F_(DU_DB7, IP2_7_4)
42 #define GPSR0_16 F_(DU_DB6, IP2_3_0)
43 #define GPSR0_15 F_(DU_DB5, IP1_31_28)
44 #define GPSR0_14 F_(DU_DB4, IP1_27_24)
45 #define GPSR0_13 F_(DU_DB3, IP1_23_20)
46 #define GPSR0_12 F_(DU_DB2, IP1_19_16)
47 #define GPSR0_11 F_(DU_DG7, IP1_15_12)
48 #define GPSR0_10 F_(DU_DG6, IP1_11_8)
49 #define GPSR0_9 F_(DU_DG5, IP1_7_4)
50 #define GPSR0_8 F_(DU_DG4, IP1_3_0)
51 #define GPSR0_7 F_(DU_DG3, IP0_31_28)
52 #define GPSR0_6 F_(DU_DG2, IP0_27_24)
53 #define GPSR0_5 F_(DU_DR7, IP0_23_20)
54 #define GPSR0_4 F_(DU_DR6, IP0_19_16)
55 #define GPSR0_3 F_(DU_DR5, IP0_15_12)
56 #define GPSR0_2 F_(DU_DR4, IP0_11_8)
57 #define GPSR0_1 F_(DU_DR3, IP0_7_4)
58 #define GPSR0_0 F_(DU_DR2, IP0_3_0)
59
60 /* GPSR1 */
61 #define GPSR1_27 F_(DIGRF_CLKOUT, IP8_31_28)
62 #define GPSR1_26 F_(DIGRF_CLKIN, IP8_27_24)
63 #define GPSR1_25 F_(CANFD_CLK_A, IP8_23_20)
64 #define GPSR1_24 F_(CANFD1_RX, IP8_19_16)
65 #define GPSR1_23 F_(CANFD1_TX, IP8_15_12)
66 #define GPSR1_22 F_(CANFD0_RX_A, IP8_11_8)
67 #define GPSR1_21 F_(CANFD0_TX_A, IP8_7_4)
68 #define GPSR1_20 F_(AVB_AVTP_CAPTURE, IP8_3_0)
69 #define GPSR1_19 F_(AVB_AVTP_MATCH, IP7_31_28)
70 #define GPSR1_18 FM(AVB_LINK)
71 #define GPSR1_17 FM(AVB_PHY_INT)
72 #define GPSR1_16 FM(AVB_MAGIC)
73 #define GPSR1_15 FM(AVB_MDC)
74 #define GPSR1_14 FM(AVB_MDIO)
75 #define GPSR1_13 FM(AVB_TXCREFCLK)
76 #define GPSR1_12 FM(AVB_TD3)
77 #define GPSR1_11 FM(AVB_TD2)
78 #define GPSR1_10 FM(AVB_TD1)
79 #define GPSR1_9 FM(AVB_TD0)
80 #define GPSR1_8 FM(AVB_TXC)
81 #define GPSR1_7 FM(AVB_TX_CTL)
82 #define GPSR1_6 FM(AVB_RD3)
83 #define GPSR1_5 FM(AVB_RD2)
84 #define GPSR1_4 FM(AVB_RD1)
85 #define GPSR1_3 FM(AVB_RD0)
86 #define GPSR1_2 FM(AVB_RXC)
87 #define GPSR1_1 FM(AVB_RX_CTL)
88 #define GPSR1_0 F_(IRQ0, IP2_27_24)
89
90 /* GPSR2 */
91 #define GPSR2_29 F_(FSO_TOE_N, IP10_19_16)
92 #define GPSR2_28 F_(FSO_CFE_1_N, IP10_15_12)
93 #define GPSR2_27 F_(FSO_CFE_0_N, IP10_11_8)
94 #define GPSR2_26 F_(SDA3, IP10_7_4)
95 #define GPSR2_25 F_(SCL3, IP10_3_0)
96 #define GPSR2_24 F_(MSIOF0_SS2, IP9_31_28)
97 #define GPSR2_23 F_(MSIOF0_SS1, IP9_27_24)
98 #define GPSR2_22 F_(MSIOF0_SYNC, IP9_23_20)
99 #define GPSR2_21 F_(MSIOF0_SCK, IP9_19_16)
100 #define GPSR2_20 F_(MSIOF0_TXD, IP9_15_12)
101 #define GPSR2_19 F_(MSIOF0_RXD, IP9_11_8)
102 #define GPSR2_18 F_(IRQ5, IP9_7_4)
103 #define GPSR2_17 F_(IRQ4, IP9_3_0)
104 #define GPSR2_16 F_(VI0_FIELD, IP4_31_28)
105 #define GPSR2_15 F_(VI0_DATA11, IP4_27_24)
106 #define GPSR2_14 F_(VI0_DATA10, IP4_23_20)
107 #define GPSR2_13 F_(VI0_DATA9, IP4_19_16)
108 #define GPSR2_12 F_(VI0_DATA8, IP4_15_12)
109 #define GPSR2_11 F_(VI0_DATA7, IP4_11_8)
110 #define GPSR2_10 F_(VI0_DATA6, IP4_7_4)
111 #define GPSR2_9 F_(VI0_DATA5, IP4_3_0)
112 #define GPSR2_8 F_(VI0_DATA4, IP3_31_28)
113 #define GPSR2_7 F_(VI0_DATA3, IP3_27_24)
114 #define GPSR2_6 F_(VI0_DATA2, IP3_23_20)
115 #define GPSR2_5 F_(VI0_DATA1, IP3_19_16)
116 #define GPSR2_4 F_(VI0_DATA0, IP3_15_12)
117 #define GPSR2_3 F_(VI0_VSYNC_N, IP3_11_8)
118 #define GPSR2_2 F_(VI0_HSYNC_N, IP3_7_4)
119 #define GPSR2_1 F_(VI0_CLKENB, IP3_3_0)
120 #define GPSR2_0 F_(VI0_CLK, IP2_31_28)
121
122 /* GPSR3 */
123 #define GPSR3_16 F_(VI1_FIELD, IP7_3_0)
124 #define GPSR3_15 F_(VI1_DATA11, IP6_31_28)
125 #define GPSR3_14 F_(VI1_DATA10, IP6_27_24)
126 #define GPSR3_13 F_(VI1_DATA9, IP6_23_20)
127 #define GPSR3_12 F_(VI1_DATA8, IP6_19_16)
128 #define GPSR3_11 F_(VI1_DATA7, IP6_15_12)
129 #define GPSR3_10 F_(VI1_DATA6, IP6_11_8)
130 #define GPSR3_9 F_(VI1_DATA5, IP6_7_4)
131 #define GPSR3_8 F_(VI1_DATA4, IP6_3_0)
132 #define GPSR3_7 F_(VI1_DATA3, IP5_31_28)
133 #define GPSR3_6 F_(VI1_DATA2, IP5_27_24)
134 #define GPSR3_5 F_(VI1_DATA1, IP5_23_20)
135 #define GPSR3_4 F_(VI1_DATA0, IP5_19_16)
136 #define GPSR3_3 F_(VI1_VSYNC_N, IP5_15_12)
137 #define GPSR3_2 F_(VI1_HSYNC_N, IP5_11_8)
138 #define GPSR3_1 F_(VI1_CLKENB, IP5_7_4)
139 #define GPSR3_0 F_(VI1_CLK, IP5_3_0)
140
141 /* GPSR4 */
142 #define GPSR4_24 FM(GETHER_LINK_A)
143 #define GPSR4_23 FM(GETHER_PHY_INT_A)
144 #define GPSR4_22 FM(GETHER_MAGIC)
145 #define GPSR4_21 FM(GETHER_MDC_A)
146 #define GPSR4_20 FM(GETHER_MDIO_A)
147 #define GPSR4_19 FM(GETHER_TXCREFCLK_MEGA)
148 #define GPSR4_18 FM(GETHER_TXCREFCLK)
149 #define GPSR4_17 FM(GETHER_TD3)
150 #define GPSR4_16 FM(GETHER_TD2)
151 #define GPSR4_15 FM(GETHER_TD1)
152 #define GPSR4_14 FM(GETHER_TD0)
153 #define GPSR4_13 FM(GETHER_TXC)
154 #define GPSR4_12 FM(GETHER_TX_CTL)
155 #define GPSR4_11 FM(GETHER_RD3)
156 #define GPSR4_10 FM(GETHER_RD2)
157 #define GPSR4_9 FM(GETHER_RD1)
158 #define GPSR4_8 FM(GETHER_RD0)
159 #define GPSR4_7 FM(GETHER_RXC)
160 #define GPSR4_6 FM(GETHER_RX_CTL)
161 #define GPSR4_5 F_(SDA2, IP7_27_24)
162 #define GPSR4_4 F_(SCL2, IP7_23_20)
163 #define GPSR4_3 F_(SDA1, IP7_19_16)
164 #define GPSR4_2 F_(SCL1, IP7_15_12)
165 #define GPSR4_1 F_(SDA0, IP7_11_8)
166 #define GPSR4_0 F_(SCL0, IP7_7_4)
167
168 /* GPSR5 */
169 #define GPSR5_14 FM(RPC_INT_N)
170 #define GPSR5_13 FM(RPC_WP_N)
171 #define GPSR5_12 FM(RPC_RESET_N)
172 #define GPSR5_11 FM(QSPI1_SSL)
173 #define GPSR5_10 FM(QSPI1_IO3)
174 #define GPSR5_9 FM(QSPI1_IO2)
175 #define GPSR5_8 FM(QSPI1_MISO_IO1)
176 #define GPSR5_7 FM(QSPI1_MOSI_IO0)
177 #define GPSR5_6 FM(QSPI1_SPCLK)
178 #define GPSR5_5 FM(QSPI0_SSL)
179 #define GPSR5_4 FM(QSPI0_IO3)
180 #define GPSR5_3 FM(QSPI0_IO2)
181 #define GPSR5_2 FM(QSPI0_MISO_IO1)
182 #define GPSR5_1 FM(QSPI0_MOSI_IO0)
183 #define GPSR5_0 FM(QSPI0_SPCLK)
184
185
186 /* IPSRx */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 - F */
187 #define IP0_3_0 FM(DU_DR2) FM(SCK4) FM(GETHER_RMII_CRS_DV) FM(A0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
188 #define IP0_7_4 FM(DU_DR3) FM(RX4) FM(GETHER_RMII_RX_ER) FM(A1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
189 #define IP0_11_8 FM(DU_DR4) FM(TX4) FM(GETHER_RMII_RXD0) FM(A2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
190 #define IP0_15_12 FM(DU_DR5) FM(CTS4_N) FM(GETHER_RMII_RXD1) FM(A3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
191 #define IP0_19_16 FM(DU_DR6) FM(RTS4_N) FM(GETHER_RMII_TXD_EN) FM(A4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
192 #define IP0_23_20 FM(DU_DR7) F_(0, 0) FM(GETHER_RMII_TXD0) FM(A5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
193 #define IP0_27_24 FM(DU_DG2) F_(0, 0) FM(GETHER_RMII_TXD1) FM(A6) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
194 #define IP0_31_28 FM(DU_DG3) FM(CPG_CPCKOUT) FM(GETHER_RMII_REFCLK) FM(A7) FM(PWMFSW0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
195 #define IP1_3_0 FM(DU_DG4) FM(SCL5) F_(0, 0) FM(A8) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
196 #define IP1_7_4 FM(DU_DG5) FM(SDA5) FM(GETHER_MDC_B) FM(A9) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
197 #define IP1_11_8 FM(DU_DG6) FM(SCIF_CLK_A) FM(GETHER_MDIO_B) FM(A10) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
198 #define IP1_15_12 FM(DU_DG7) FM(HRX0_A) F_(0, 0) FM(A11) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
199 #define IP1_19_16 FM(DU_DB2) FM(HSCK0_A) F_(0, 0) FM(A12) FM(IRQ1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
200 #define IP1_23_20 FM(DU_DB3) FM(HRTS0_N_A) F_(0, 0) FM(A13) FM(IRQ2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
201 #define IP1_27_24 FM(DU_DB4) FM(HCTS0_N_A) F_(0, 0) FM(A14) FM(IRQ3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
202 #define IP1_31_28 FM(DU_DB5) FM(HTX0_A) FM(PWM0_A) FM(A15) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
203 #define IP2_3_0 FM(DU_DB6) FM(MSIOF3_RXD) F_(0, 0) FM(A16) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
204 #define IP2_7_4 FM(DU_DB7) FM(MSIOF3_TXD) F_(0, 0) FM(A17) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
205 #define IP2_11_8 FM(DU_DOTCLKOUT) FM(MSIOF3_SS1) FM(GETHER_LINK_B) FM(A18) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
206 #define IP2_15_12 FM(DU_EXHSYNC_DU_HSYNC) FM(MSIOF3_SS2) FM(GETHER_PHY_INT_B) FM(A19) FM(FXR_TXENA_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
207 #define IP2_19_16 FM(DU_EXVSYNC_DU_VSYNC) FM(MSIOF3_SCK) F_(0, 0) F_(0, 0) FM(FXR_TXENB_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
208 #define IP2_23_20 FM(DU_EXODDF_DU_ODDF_DISP_CDE) FM(MSIOF3_SYNC) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
209 #define IP2_27_24 FM(IRQ0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
210 #define IP2_31_28 FM(VI0_CLK) FM(MSIOF2_SCK) FM(SCK3) F_(0, 0) FM(HSCK3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
211 #define IP3_3_0 FM(VI0_CLKENB) FM(MSIOF2_RXD) FM(RX3) FM(RD_WR_N) FM(HCTS3_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
212 #define IP3_7_4 FM(VI0_HSYNC_N) FM(MSIOF2_TXD) FM(TX3) F_(0, 0) FM(HRTS3_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
213 #define IP3_11_8 FM(VI0_VSYNC_N) FM(MSIOF2_SYNC) FM(CTS3_N) F_(0, 0) FM(HTX3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
214 #define IP3_15_12 FM(VI0_DATA0) FM(MSIOF2_SS1) FM(RTS3_N) F_(0, 0) FM(HRX3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
215 #define IP3_19_16 FM(VI0_DATA1) FM(MSIOF2_SS2) FM(SCK1) F_(0, 0) FM(SPEEDIN_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
216 #define IP3_23_20 FM(VI0_DATA2) FM(AVB_AVTP_PPS) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
217 #define IP3_27_24 FM(VI0_DATA3) FM(HSCK1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
218 #define IP3_31_28 FM(VI0_DATA4) FM(HRTS1_N) FM(RX1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
219 #define IP4_3_0 FM(VI0_DATA5) FM(HCTS1_N) FM(TX1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
220 #define IP4_7_4 FM(VI0_DATA6) FM(HTX1) FM(CTS1_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
221 #define IP4_11_8 FM(VI0_DATA7) FM(HRX1) FM(RTS1_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
222 #define IP4_15_12 FM(VI0_DATA8) FM(HSCK2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
223 #define IP4_19_16 FM(VI0_DATA9) FM(HCTS2_N) FM(PWM1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
224 #define IP4_23_20 FM(VI0_DATA10) FM(HRTS2_N) FM(PWM2_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
225 #define IP4_27_24 FM(VI0_DATA11) FM(HTX2) FM(PWM3_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
226 #define IP4_31_28 FM(VI0_FIELD) FM(HRX2) FM(PWM4_A) FM(CS1_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
227 #define IP5_3_0 FM(VI1_CLK) FM(MSIOF1_RXD) F_(0, 0) FM(CS0_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
228 #define IP5_7_4 FM(VI1_CLKENB) FM(MSIOF1_TXD) F_(0, 0) FM(D0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
229 #define IP5_11_8 FM(VI1_HSYNC_N) FM(MSIOF1_SCK) F_(0, 0) FM(D1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
230 #define IP5_15_12 FM(VI1_VSYNC_N) FM(MSIOF1_SYNC) F_(0, 0) FM(D2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
231 #define IP5_19_16 FM(VI1_DATA0) FM(MSIOF1_SS1) F_(0, 0) FM(D3) FM(MMC_WP) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
232 #define IP5_23_20 FM(VI1_DATA1) FM(MSIOF1_SS2) F_(0, 0) FM(D4) FM(MMC_CD) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
233 #define IP5_27_24 FM(VI1_DATA2) FM(CANFD0_TX_B) F_(0, 0) FM(D5) FM(MMC_DS) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
234 #define IP5_31_28 FM(VI1_DATA3) FM(CANFD0_RX_B) F_(0, 0) FM(D6) FM(MMC_CMD) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
235 #define IP6_3_0 FM(VI1_DATA4) FM(CANFD_CLK_B) F_(0, 0) FM(D7) FM(MMC_D0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
236 #define IP6_7_4 FM(VI1_DATA5) F_(0, 0) F_(0, 0) FM(D8) FM(MMC_D1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
237 #define IP6_11_8 FM(VI1_DATA6) F_(0, 0) F_(0, 0) FM(D9) FM(MMC_D2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
238 #define IP6_15_12 FM(VI1_DATA7) F_(0, 0) F_(0, 0) FM(D10) FM(MMC_D3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
239 #define IP6_19_16 FM(VI1_DATA8) F_(0, 0) F_(0, 0) FM(D11) FM(MMC_CLK) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
240 #define IP6_23_20 FM(VI1_DATA9) FM(TCLK1_A) F_(0, 0) FM(D12) FM(MMC_D4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
241 #define IP6_27_24 FM(VI1_DATA10) FM(TCLK2_A) F_(0, 0) FM(D13) FM(MMC_D5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
242 #define IP6_31_28 FM(VI1_DATA11) FM(SCL4) F_(0, 0) FM(D14) FM(MMC_D6) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
243 #define IP7_3_0 FM(VI1_FIELD) FM(SDA4) F_(0, 0) FM(D15) FM(MMC_D7) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
244 #define IP7_7_4 FM(SCL0) F_(0, 0) F_(0, 0) FM(CLKOUT) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
245 #define IP7_11_8 FM(SDA0) F_(0, 0) F_(0, 0) FM(BS_N) FM(SCK0) FM(HSCK0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
246 #define IP7_15_12 FM(SCL1) F_(0, 0) FM(TPU0TO2) FM(RD_N) FM(CTS0_N) FM(HCTS0_N_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
247 #define IP7_19_16 FM(SDA1) F_(0, 0) FM(TPU0TO3) FM(WE0_N) FM(RTS0_N) FM(HRTS0_N_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
248 #define IP7_23_20 FM(SCL2) F_(0, 0) F_(0, 0) FM(WE1_N) FM(RX0) FM(HRX0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
249 #define IP7_27_24 FM(SDA2) F_(0, 0) F_(0, 0) FM(EX_WAIT0) FM(TX0) FM(HTX0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
250 #define IP7_31_28 FM(AVB_AVTP_MATCH) FM(TPU0TO0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
251 #define IP8_3_0 FM(AVB_AVTP_CAPTURE) FM(TPU0TO1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
252 #define IP8_7_4 FM(CANFD0_TX_A) FM(FXR_TXDA) FM(PWM0_B) FM(DU_DISP) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
253 #define IP8_11_8 FM(CANFD0_RX_A) FM(RXDA_EXTFXR) FM(PWM1_B) FM(DU_CDE) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
254 #define IP8_15_12 FM(CANFD1_TX) FM(FXR_TXDB) FM(PWM2_B) FM(TCLK1_B) FM(TX1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
255 #define IP8_19_16 FM(CANFD1_RX) FM(RXDB_EXTFXR) FM(PWM3_B) FM(TCLK2_B) FM(RX1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
256 #define IP8_23_20 FM(CANFD_CLK_A) FM(CLK_EXTFXR) FM(PWM4_B) FM(SPEEDIN_B) FM(SCIF_CLK_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
257 #define IP8_27_24 FM(DIGRF_CLKIN) FM(DIGRF_CLKEN_IN) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
258 #define IP8_31_28 FM(DIGRF_CLKOUT) FM(DIGRF_CLKEN_OUT) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
259 #define IP9_3_0 FM(IRQ4) F_(0, 0) F_(0, 0) FM(VI0_DATA12) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
260 #define IP9_7_4 FM(IRQ5) F_(0, 0) F_(0, 0) FM(VI0_DATA13) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
261 #define IP9_11_8 FM(MSIOF0_RXD) FM(DU_DR0) F_(0, 0) FM(VI0_DATA14) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
262 #define IP9_15_12 FM(MSIOF0_TXD) FM(DU_DR1) F_(0, 0) FM(VI0_DATA15) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
263 #define IP9_19_16 FM(MSIOF0_SCK) FM(DU_DG0) F_(0, 0) FM(VI0_DATA16) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
264 #define IP9_23_20 FM(MSIOF0_SYNC) FM(DU_DG1) F_(0, 0) FM(VI0_DATA17) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
265 #define IP9_27_24 FM(MSIOF0_SS1) FM(DU_DB0) FM(TCLK3) FM(VI0_DATA18) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
266 #define IP9_31_28 FM(MSIOF0_SS2) FM(DU_DB1) FM(TCLK4) FM(VI0_DATA19) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
267 #define IP10_3_0 FM(SCL3) F_(0, 0) F_(0, 0) FM(VI0_DATA20) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
268 #define IP10_7_4 FM(SDA3) F_(0, 0) F_(0, 0) FM(VI0_DATA21) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
269 #define IP10_11_8 FM(FSO_CFE_0_N) F_(0, 0) F_(0, 0) FM(VI0_DATA22) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
270 #define IP10_15_12 FM(FSO_CFE_1_N) F_(0, 0) F_(0, 0) FM(VI0_DATA23) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
271 #define IP10_19_16 FM(FSO_TOE_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
272 #define IP10_23_20 F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
273 #define IP10_27_24 F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
274 #define IP10_31_28 F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
275
276 #define PINMUX_GPSR \
277 \
278 GPSR2_29 \
279 GPSR2_28 \
280 GPSR1_27 GPSR2_27 \
281 GPSR1_26 GPSR2_26 \
282 GPSR1_25 GPSR2_25 \
283 GPSR1_24 GPSR2_24 GPSR4_24 \
284 GPSR1_23 GPSR2_23 GPSR4_23 \
285 GPSR1_22 GPSR2_22 GPSR4_22 \
286 GPSR0_21 GPSR1_21 GPSR2_21 GPSR4_21 \
287 GPSR0_20 GPSR1_20 GPSR2_20 GPSR4_20 \
288 GPSR0_19 GPSR1_19 GPSR2_19 GPSR4_19 \
289 GPSR0_18 GPSR1_18 GPSR2_18 GPSR4_18 \
290 GPSR0_17 GPSR1_17 GPSR2_17 GPSR4_17 \
291 GPSR0_16 GPSR1_16 GPSR2_16 GPSR3_16 GPSR4_16 \
292 GPSR0_15 GPSR1_15 GPSR2_15 GPSR3_15 GPSR4_15 \
293 GPSR0_14 GPSR1_14 GPSR2_14 GPSR3_14 GPSR4_14 GPSR5_14 \
294 GPSR0_13 GPSR1_13 GPSR2_13 GPSR3_13 GPSR4_13 GPSR5_13 \
295 GPSR0_12 GPSR1_12 GPSR2_12 GPSR3_12 GPSR4_12 GPSR5_12 \
296 GPSR0_11 GPSR1_11 GPSR2_11 GPSR3_11 GPSR4_11 GPSR5_11 \
297 GPSR0_10 GPSR1_10 GPSR2_10 GPSR3_10 GPSR4_10 GPSR5_10 \
298 GPSR0_9 GPSR1_9 GPSR2_9 GPSR3_9 GPSR4_9 GPSR5_9 \
299 GPSR0_8 GPSR1_8 GPSR2_8 GPSR3_8 GPSR4_8 GPSR5_8 \
300 GPSR0_7 GPSR1_7 GPSR2_7 GPSR3_7 GPSR4_7 GPSR5_7 \
301 GPSR0_6 GPSR1_6 GPSR2_6 GPSR3_6 GPSR4_6 GPSR5_6 \
302 GPSR0_5 GPSR1_5 GPSR2_5 GPSR3_5 GPSR4_5 GPSR5_5 \
303 GPSR0_4 GPSR1_4 GPSR2_4 GPSR3_4 GPSR4_4 GPSR5_4 \
304 GPSR0_3 GPSR1_3 GPSR2_3 GPSR3_3 GPSR4_3 GPSR5_3 \
305 GPSR0_2 GPSR1_2 GPSR2_2 GPSR3_2 GPSR4_2 GPSR5_2 \
306 GPSR0_1 GPSR1_1 GPSR2_1 GPSR3_1 GPSR4_1 GPSR5_1 \
307 GPSR0_0 GPSR1_0 GPSR2_0 GPSR3_0 GPSR4_0 GPSR5_0
308
309 #define PINMUX_IPSR \
310 \
311 FM(IP0_3_0) IP0_3_0 FM(IP1_3_0) IP1_3_0 FM(IP2_3_0) IP2_3_0 FM(IP3_3_0) IP3_3_0 \
312 FM(IP0_7_4) IP0_7_4 FM(IP1_7_4) IP1_7_4 FM(IP2_7_4) IP2_7_4 FM(IP3_7_4) IP3_7_4 \
313 FM(IP0_11_8) IP0_11_8 FM(IP1_11_8) IP1_11_8 FM(IP2_11_8) IP2_11_8 FM(IP3_11_8) IP3_11_8 \
314 FM(IP0_15_12) IP0_15_12 FM(IP1_15_12) IP1_15_12 FM(IP2_15_12) IP2_15_12 FM(IP3_15_12) IP3_15_12 \
315 FM(IP0_19_16) IP0_19_16 FM(IP1_19_16) IP1_19_16 FM(IP2_19_16) IP2_19_16 FM(IP3_19_16) IP3_19_16 \
316 FM(IP0_23_20) IP0_23_20 FM(IP1_23_20) IP1_23_20 FM(IP2_23_20) IP2_23_20 FM(IP3_23_20) IP3_23_20 \
317 FM(IP0_27_24) IP0_27_24 FM(IP1_27_24) IP1_27_24 FM(IP2_27_24) IP2_27_24 FM(IP3_27_24) IP3_27_24 \
318 FM(IP0_31_28) IP0_31_28 FM(IP1_31_28) IP1_31_28 FM(IP2_31_28) IP2_31_28 FM(IP3_31_28) IP3_31_28 \
319 \
320 FM(IP4_3_0) IP4_3_0 FM(IP5_3_0) IP5_3_0 FM(IP6_3_0) IP6_3_0 FM(IP7_3_0) IP7_3_0 \
321 FM(IP4_7_4) IP4_7_4 FM(IP5_7_4) IP5_7_4 FM(IP6_7_4) IP6_7_4 FM(IP7_7_4) IP7_7_4 \
322 FM(IP4_11_8) IP4_11_8 FM(IP5_11_8) IP5_11_8 FM(IP6_11_8) IP6_11_8 FM(IP7_11_8) IP7_11_8 \
323 FM(IP4_15_12) IP4_15_12 FM(IP5_15_12) IP5_15_12 FM(IP6_15_12) IP6_15_12 FM(IP7_15_12) IP7_15_12 \
324 FM(IP4_19_16) IP4_19_16 FM(IP5_19_16) IP5_19_16 FM(IP6_19_16) IP6_19_16 FM(IP7_19_16) IP7_19_16 \
325 FM(IP4_23_20) IP4_23_20 FM(IP5_23_20) IP5_23_20 FM(IP6_23_20) IP6_23_20 FM(IP7_23_20) IP7_23_20 \
326 FM(IP4_27_24) IP4_27_24 FM(IP5_27_24) IP5_27_24 FM(IP6_27_24) IP6_27_24 FM(IP7_27_24) IP7_27_24 \
327 FM(IP4_31_28) IP4_31_28 FM(IP5_31_28) IP5_31_28 FM(IP6_31_28) IP6_31_28 FM(IP7_31_28) IP7_31_28 \
328 \
329 FM(IP8_3_0) IP8_3_0 FM(IP9_3_0) IP9_3_0 FM(IP10_3_0) IP10_3_0 \
330 FM(IP8_7_4) IP8_7_4 FM(IP9_7_4) IP9_7_4 FM(IP10_7_4) IP10_7_4 \
331 FM(IP8_11_8) IP8_11_8 FM(IP9_11_8) IP9_11_8 FM(IP10_11_8) IP10_11_8 \
332 FM(IP8_15_12) IP8_15_12 FM(IP9_15_12) IP9_15_12 FM(IP10_15_12) IP10_15_12 \
333 FM(IP8_19_16) IP8_19_16 FM(IP9_19_16) IP9_19_16 FM(IP10_19_16) IP10_19_16 \
334 FM(IP8_23_20) IP8_23_20 FM(IP9_23_20) IP9_23_20 FM(IP10_23_20) IP10_23_20 \
335 FM(IP8_27_24) IP8_27_24 FM(IP9_27_24) IP9_27_24 FM(IP10_27_24) IP10_27_24 \
336 FM(IP8_31_28) IP8_31_28 FM(IP9_31_28) IP9_31_28 FM(IP10_31_28) IP10_31_28
337
338 /* MOD_SEL0 */ /* 0 */ /* 1 */
339 #define MOD_SEL0_11 FM(SEL_CANFD0_0) FM(SEL_CANFD0_1)
340 #define MOD_SEL0_10 FM(SEL_GETHER_0) FM(SEL_GETHER_1)
341 #define MOD_SEL0_9 FM(SEL_HSCIF0_0) FM(SEL_HSCIF0_1)
342 #define MOD_SEL0_8 FM(SEL_PWM0_0) FM(SEL_PWM0_1)
343 #define MOD_SEL0_7 FM(SEL_PWM1_0) FM(SEL_PWM1_1)
344 #define MOD_SEL0_6 FM(SEL_PWM2_0) FM(SEL_PWM2_1)
345 #define MOD_SEL0_5 FM(SEL_PWM3_0) FM(SEL_PWM3_1)
346 #define MOD_SEL0_4 FM(SEL_PWM4_0) FM(SEL_PWM4_1)
347 #define MOD_SEL0_2 FM(SEL_RSP_0) FM(SEL_RSP_1)
348 #define MOD_SEL0_1 FM(SEL_SCIF1_0) FM(SEL_SCIF1_1)
349 #define MOD_SEL0_0 FM(SEL_TMU_0) FM(SEL_TMU_1)
350
351 #define PINMUX_MOD_SELS \
352 \
353 MOD_SEL0_11 \
354 MOD_SEL0_10 \
355 MOD_SEL0_9 \
356 MOD_SEL0_8 \
357 MOD_SEL0_7 \
358 MOD_SEL0_6 \
359 MOD_SEL0_5 \
360 MOD_SEL0_4 \
361 MOD_SEL0_2 \
362 MOD_SEL0_1 \
363 MOD_SEL0_0
364
365 enum {
366 PINMUX_RESERVED = 0,
367
368 PINMUX_DATA_BEGIN,
369 GP_ALL(DATA),
370 PINMUX_DATA_END,
371
372 #define F_(x, y)
373 #define FM(x) FN_##x,
374 PINMUX_FUNCTION_BEGIN,
375 GP_ALL(FN),
376 PINMUX_GPSR
377 PINMUX_IPSR
378 PINMUX_MOD_SELS
379 PINMUX_FUNCTION_END,
380 #undef F_
381 #undef FM
382
383 #define F_(x, y)
384 #define FM(x) x##_MARK,
385 PINMUX_MARK_BEGIN,
386 PINMUX_GPSR
387 PINMUX_IPSR
388 PINMUX_MOD_SELS
389 PINMUX_MARK_END,
390 #undef F_
391 #undef FM
392 };
393
394 static const u16 pinmux_data[] = {
395 PINMUX_DATA_GP_ALL(),
396
397 PINMUX_SINGLE(AVB_RX_CTL),
398 PINMUX_SINGLE(AVB_RXC),
399 PINMUX_SINGLE(AVB_RD0),
400 PINMUX_SINGLE(AVB_RD1),
401 PINMUX_SINGLE(AVB_RD2),
402 PINMUX_SINGLE(AVB_RD3),
403 PINMUX_SINGLE(AVB_TX_CTL),
404 PINMUX_SINGLE(AVB_TXC),
405 PINMUX_SINGLE(AVB_TD0),
406 PINMUX_SINGLE(AVB_TD1),
407 PINMUX_SINGLE(AVB_TD2),
408 PINMUX_SINGLE(AVB_TD3),
409 PINMUX_SINGLE(AVB_TXCREFCLK),
410 PINMUX_SINGLE(AVB_MDIO),
411 PINMUX_SINGLE(AVB_MDC),
412 PINMUX_SINGLE(AVB_MAGIC),
413 PINMUX_SINGLE(AVB_PHY_INT),
414 PINMUX_SINGLE(AVB_LINK),
415
416 PINMUX_SINGLE(GETHER_RX_CTL),
417 PINMUX_SINGLE(GETHER_RXC),
418 PINMUX_SINGLE(GETHER_RD0),
419 PINMUX_SINGLE(GETHER_RD1),
420 PINMUX_SINGLE(GETHER_RD2),
421 PINMUX_SINGLE(GETHER_RD3),
422 PINMUX_SINGLE(GETHER_TX_CTL),
423 PINMUX_SINGLE(GETHER_TXC),
424 PINMUX_SINGLE(GETHER_TD0),
425 PINMUX_SINGLE(GETHER_TD1),
426 PINMUX_SINGLE(GETHER_TD2),
427 PINMUX_SINGLE(GETHER_TD3),
428 PINMUX_SINGLE(GETHER_TXCREFCLK),
429 PINMUX_SINGLE(GETHER_TXCREFCLK_MEGA),
430 PINMUX_SINGLE(GETHER_MDIO_A),
431 PINMUX_SINGLE(GETHER_MDC_A),
432 PINMUX_SINGLE(GETHER_MAGIC),
433 PINMUX_SINGLE(GETHER_PHY_INT_A),
434 PINMUX_SINGLE(GETHER_LINK_A),
435
436 PINMUX_SINGLE(QSPI0_SPCLK),
437 PINMUX_SINGLE(QSPI0_MOSI_IO0),
438 PINMUX_SINGLE(QSPI0_MISO_IO1),
439 PINMUX_SINGLE(QSPI0_IO2),
440 PINMUX_SINGLE(QSPI0_IO3),
441 PINMUX_SINGLE(QSPI0_SSL),
442 PINMUX_SINGLE(QSPI1_SPCLK),
443 PINMUX_SINGLE(QSPI1_MOSI_IO0),
444 PINMUX_SINGLE(QSPI1_MISO_IO1),
445 PINMUX_SINGLE(QSPI1_IO2),
446 PINMUX_SINGLE(QSPI1_IO3),
447 PINMUX_SINGLE(QSPI1_SSL),
448 PINMUX_SINGLE(RPC_RESET_N),
449 PINMUX_SINGLE(RPC_WP_N),
450 PINMUX_SINGLE(RPC_INT_N),
451
452 /* IPSR0 */
453 PINMUX_IPSR_GPSR(IP0_3_0, DU_DR2),
454 PINMUX_IPSR_GPSR(IP0_3_0, SCK4),
455 PINMUX_IPSR_GPSR(IP0_3_0, GETHER_RMII_CRS_DV),
456 PINMUX_IPSR_GPSR(IP0_3_0, A0),
457
458 PINMUX_IPSR_GPSR(IP0_7_4, DU_DR3),
459 PINMUX_IPSR_GPSR(IP0_7_4, RX4),
460 PINMUX_IPSR_GPSR(IP0_7_4, GETHER_RMII_RX_ER),
461 PINMUX_IPSR_GPSR(IP0_7_4, A1),
462
463 PINMUX_IPSR_GPSR(IP0_11_8, DU_DR4),
464 PINMUX_IPSR_GPSR(IP0_11_8, TX4),
465 PINMUX_IPSR_GPSR(IP0_11_8, GETHER_RMII_RXD0),
466 PINMUX_IPSR_GPSR(IP0_11_8, A2),
467
468 PINMUX_IPSR_GPSR(IP0_15_12, DU_DR5),
469 PINMUX_IPSR_GPSR(IP0_15_12, CTS4_N),
470 PINMUX_IPSR_GPSR(IP0_15_12, GETHER_RMII_RXD1),
471 PINMUX_IPSR_GPSR(IP0_15_12, A3),
472
473 PINMUX_IPSR_GPSR(IP0_19_16, DU_DR6),
474 PINMUX_IPSR_GPSR(IP0_19_16, RTS4_N),
475 PINMUX_IPSR_GPSR(IP0_19_16, GETHER_RMII_TXD_EN),
476 PINMUX_IPSR_GPSR(IP0_19_16, A4),
477
478 PINMUX_IPSR_GPSR(IP0_23_20, DU_DR7),
479 PINMUX_IPSR_GPSR(IP0_23_20, GETHER_RMII_TXD0),
480 PINMUX_IPSR_GPSR(IP0_23_20, A5),
481
482 PINMUX_IPSR_GPSR(IP0_27_24, DU_DG2),
483 PINMUX_IPSR_GPSR(IP0_27_24, GETHER_RMII_TXD1),
484 PINMUX_IPSR_GPSR(IP0_27_24, A6),
485
486 PINMUX_IPSR_GPSR(IP0_31_28, DU_DG3),
487 PINMUX_IPSR_GPSR(IP0_31_28, CPG_CPCKOUT),
488 PINMUX_IPSR_GPSR(IP0_31_28, GETHER_RMII_REFCLK),
489 PINMUX_IPSR_GPSR(IP0_31_28, A7),
490 PINMUX_IPSR_GPSR(IP0_31_28, PWMFSW0),
491
492 /* IPSR1 */
493 PINMUX_IPSR_GPSR(IP1_3_0, DU_DG4),
494 PINMUX_IPSR_GPSR(IP1_3_0, SCL5),
495 PINMUX_IPSR_GPSR(IP1_3_0, A8),
496
497 PINMUX_IPSR_GPSR(IP1_7_4, DU_DG5),
498 PINMUX_IPSR_GPSR(IP1_7_4, SDA5),
499 PINMUX_IPSR_MSEL(IP1_7_4, GETHER_MDC_B, SEL_GETHER_1),
500 PINMUX_IPSR_GPSR(IP1_7_4, A9),
501
502 PINMUX_IPSR_GPSR(IP1_11_8, DU_DG6),
503 PINMUX_IPSR_MSEL(IP1_11_8, SCIF_CLK_A, SEL_HSCIF0_0),
504 PINMUX_IPSR_MSEL(IP1_11_8, GETHER_MDIO_B, SEL_GETHER_1),
505 PINMUX_IPSR_GPSR(IP1_11_8, A10),
506
507 PINMUX_IPSR_GPSR(IP1_15_12, DU_DG7),
508 PINMUX_IPSR_MSEL(IP1_15_12, HRX0_A, SEL_HSCIF0_0),
509 PINMUX_IPSR_GPSR(IP1_15_12, A11),
510
511 PINMUX_IPSR_GPSR(IP1_19_16, DU_DB2),
512 PINMUX_IPSR_MSEL(IP1_19_16, HSCK0_A, SEL_HSCIF0_0),
513 PINMUX_IPSR_GPSR(IP1_19_16, A12),
514 PINMUX_IPSR_GPSR(IP1_19_16, IRQ1),
515
516 PINMUX_IPSR_GPSR(IP1_23_20, DU_DB3),
517 PINMUX_IPSR_MSEL(IP1_23_20, HRTS0_N_A, SEL_HSCIF0_0),
518 PINMUX_IPSR_GPSR(IP1_23_20, A13),
519 PINMUX_IPSR_GPSR(IP1_23_20, IRQ2),
520
521 PINMUX_IPSR_GPSR(IP1_27_24, DU_DB4),
522 PINMUX_IPSR_MSEL(IP1_27_24, HCTS0_N_A, SEL_HSCIF0_0),
523 PINMUX_IPSR_GPSR(IP1_27_24, A14),
524 PINMUX_IPSR_GPSR(IP1_27_24, IRQ3),
525
526 PINMUX_IPSR_GPSR(IP1_31_28, DU_DB5),
527 PINMUX_IPSR_MSEL(IP1_31_28, HTX0_A, SEL_HSCIF0_0),
528 PINMUX_IPSR_MSEL(IP1_31_28, PWM0_A, SEL_PWM0_0),
529 PINMUX_IPSR_GPSR(IP1_31_28, A15),
530
531 /* IPSR2 */
532 PINMUX_IPSR_GPSR(IP2_3_0, DU_DB6),
533 PINMUX_IPSR_GPSR(IP2_3_0, MSIOF3_RXD),
534 PINMUX_IPSR_GPSR(IP2_3_0, A16),
535
536 PINMUX_IPSR_GPSR(IP2_7_4, DU_DB7),
537 PINMUX_IPSR_GPSR(IP2_7_4, MSIOF3_TXD),
538 PINMUX_IPSR_GPSR(IP2_7_4, A17),
539
540 PINMUX_IPSR_GPSR(IP2_11_8, DU_DOTCLKOUT),
541 PINMUX_IPSR_GPSR(IP2_11_8, MSIOF3_SS1),
542 PINMUX_IPSR_MSEL(IP2_11_8, GETHER_LINK_B, SEL_GETHER_1),
543 PINMUX_IPSR_GPSR(IP2_11_8, A18),
544
545 PINMUX_IPSR_GPSR(IP2_15_12, DU_EXHSYNC_DU_HSYNC),
546 PINMUX_IPSR_GPSR(IP2_15_12, MSIOF3_SS2),
547 PINMUX_IPSR_MSEL(IP2_15_12, GETHER_PHY_INT_B, SEL_GETHER_1),
548 PINMUX_IPSR_GPSR(IP2_15_12, A19),
549 PINMUX_IPSR_GPSR(IP2_15_12, FXR_TXENA_N),
550
551 PINMUX_IPSR_GPSR(IP2_19_16, DU_EXVSYNC_DU_VSYNC),
552 PINMUX_IPSR_GPSR(IP2_19_16, MSIOF3_SCK),
553 PINMUX_IPSR_GPSR(IP2_19_16, FXR_TXENB_N),
554
555 PINMUX_IPSR_GPSR(IP2_23_20, DU_EXODDF_DU_ODDF_DISP_CDE),
556 PINMUX_IPSR_GPSR(IP2_23_20, MSIOF3_SYNC),
557
558 PINMUX_IPSR_GPSR(IP2_27_24, IRQ0),
559
560 PINMUX_IPSR_GPSR(IP2_31_28, VI0_CLK),
561 PINMUX_IPSR_GPSR(IP2_31_28, MSIOF2_SCK),
562 PINMUX_IPSR_GPSR(IP2_31_28, SCK3),
563 PINMUX_IPSR_GPSR(IP2_31_28, HSCK3),
564
565 /* IPSR3 */
566 PINMUX_IPSR_GPSR(IP3_3_0, VI0_CLKENB),
567 PINMUX_IPSR_GPSR(IP3_3_0, MSIOF2_RXD),
568 PINMUX_IPSR_GPSR(IP3_3_0, RX3),
569 PINMUX_IPSR_GPSR(IP3_3_0, RD_WR_N),
570 PINMUX_IPSR_GPSR(IP3_3_0, HCTS3_N),
571
572 PINMUX_IPSR_GPSR(IP3_7_4, VI0_HSYNC_N),
573 PINMUX_IPSR_GPSR(IP3_7_4, MSIOF2_TXD),
574 PINMUX_IPSR_GPSR(IP3_7_4, TX3),
575 PINMUX_IPSR_GPSR(IP3_7_4, HRTS3_N),
576
577 PINMUX_IPSR_GPSR(IP3_11_8, VI0_VSYNC_N),
578 PINMUX_IPSR_GPSR(IP3_11_8, MSIOF2_SYNC),
579 PINMUX_IPSR_GPSR(IP3_11_8, CTS3_N),
580 PINMUX_IPSR_GPSR(IP3_11_8, HTX3),
581
582 PINMUX_IPSR_GPSR(IP3_15_12, VI0_DATA0),
583 PINMUX_IPSR_GPSR(IP3_15_12, MSIOF2_SS1),
584 PINMUX_IPSR_GPSR(IP3_15_12, RTS3_N),
585 PINMUX_IPSR_GPSR(IP3_15_12, HRX3),
586
587 PINMUX_IPSR_GPSR(IP3_19_16, VI0_DATA1),
588 PINMUX_IPSR_GPSR(IP3_19_16, MSIOF2_SS2),
589 PINMUX_IPSR_GPSR(IP3_19_16, SCK1),
590 PINMUX_IPSR_MSEL(IP3_19_16, SPEEDIN_A, SEL_RSP_0),
591
592 PINMUX_IPSR_GPSR(IP3_23_20, VI0_DATA2),
593 PINMUX_IPSR_GPSR(IP3_23_20, AVB_AVTP_PPS),
594
595 PINMUX_IPSR_GPSR(IP3_27_24, VI0_DATA3),
596 PINMUX_IPSR_GPSR(IP3_27_24, HSCK1),
597
598 PINMUX_IPSR_GPSR(IP3_31_28, VI0_DATA4),
599 PINMUX_IPSR_GPSR(IP3_31_28, HRTS1_N),
600 PINMUX_IPSR_MSEL(IP3_31_28, RX1_A, SEL_SCIF1_0),
601
602 /* IPSR4 */
603 PINMUX_IPSR_GPSR(IP4_3_0, VI0_DATA5),
604 PINMUX_IPSR_GPSR(IP4_3_0, HCTS1_N),
605 PINMUX_IPSR_MSEL(IP4_3_0, TX1_A, SEL_SCIF1_0),
606
607 PINMUX_IPSR_GPSR(IP4_7_4, VI0_DATA6),
608 PINMUX_IPSR_GPSR(IP4_7_4, HTX1),
609 PINMUX_IPSR_GPSR(IP4_7_4, CTS1_N),
610
611 PINMUX_IPSR_GPSR(IP4_11_8, VI0_DATA7),
612 PINMUX_IPSR_GPSR(IP4_11_8, HRX1),
613 PINMUX_IPSR_GPSR(IP4_11_8, RTS1_N),
614
615 PINMUX_IPSR_GPSR(IP4_15_12, VI0_DATA8),
616 PINMUX_IPSR_GPSR(IP4_15_12, HSCK2),
617
618 PINMUX_IPSR_GPSR(IP4_19_16, VI0_DATA9),
619 PINMUX_IPSR_GPSR(IP4_19_16, HCTS2_N),
620 PINMUX_IPSR_MSEL(IP4_19_16, PWM1_A, SEL_PWM1_0),
621
622 PINMUX_IPSR_GPSR(IP4_23_20, VI0_DATA10),
623 PINMUX_IPSR_GPSR(IP4_23_20, HRTS2_N),
624 PINMUX_IPSR_MSEL(IP4_23_20, PWM2_A, SEL_PWM2_0),
625
626 PINMUX_IPSR_GPSR(IP4_27_24, VI0_DATA11),
627 PINMUX_IPSR_GPSR(IP4_27_24, HTX2),
628 PINMUX_IPSR_MSEL(IP4_27_24, PWM3_A, SEL_PWM3_0),
629
630 PINMUX_IPSR_GPSR(IP4_31_28, VI0_FIELD),
631 PINMUX_IPSR_GPSR(IP4_31_28, HRX2),
632 PINMUX_IPSR_MSEL(IP4_31_28, PWM4_A, SEL_PWM4_0),
633 PINMUX_IPSR_GPSR(IP4_31_28, CS1_N),
634
635 /* IPSR5 */
636 PINMUX_IPSR_GPSR(IP5_3_0, VI1_CLK),
637 PINMUX_IPSR_GPSR(IP5_3_0, MSIOF1_RXD),
638 PINMUX_IPSR_GPSR(IP5_3_0, CS0_N),
639
640 PINMUX_IPSR_GPSR(IP5_7_4, VI1_CLKENB),
641 PINMUX_IPSR_GPSR(IP5_7_4, MSIOF1_TXD),
642 PINMUX_IPSR_GPSR(IP5_7_4, D0),
643
644 PINMUX_IPSR_GPSR(IP5_11_8, VI1_HSYNC_N),
645 PINMUX_IPSR_GPSR(IP5_11_8, MSIOF1_SCK),
646 PINMUX_IPSR_GPSR(IP5_11_8, D1),
647
648 PINMUX_IPSR_GPSR(IP5_15_12, VI1_VSYNC_N),
649 PINMUX_IPSR_GPSR(IP5_15_12, MSIOF1_SYNC),
650 PINMUX_IPSR_GPSR(IP5_15_12, D2),
651
652 PINMUX_IPSR_GPSR(IP5_19_16, VI1_DATA0),
653 PINMUX_IPSR_GPSR(IP5_19_16, MSIOF1_SS1),
654 PINMUX_IPSR_GPSR(IP5_19_16, D3),
655 PINMUX_IPSR_GPSR(IP5_19_16, MMC_WP),
656
657 PINMUX_IPSR_GPSR(IP5_23_20, VI1_DATA1),
658 PINMUX_IPSR_GPSR(IP5_23_20, MSIOF1_SS2),
659 PINMUX_IPSR_GPSR(IP5_23_20, D4),
660 PINMUX_IPSR_GPSR(IP5_23_20, MMC_CD),
661
662 PINMUX_IPSR_GPSR(IP5_27_24, VI1_DATA2),
663 PINMUX_IPSR_MSEL(IP5_27_24, CANFD0_TX_B, SEL_CANFD0_1),
664 PINMUX_IPSR_GPSR(IP5_27_24, D5),
665 PINMUX_IPSR_GPSR(IP5_27_24, MMC_DS),
666
667 PINMUX_IPSR_GPSR(IP5_31_28, VI1_DATA3),
668 PINMUX_IPSR_MSEL(IP5_31_28, CANFD0_RX_B, SEL_CANFD0_1),
669 PINMUX_IPSR_GPSR(IP5_31_28, D6),
670 PINMUX_IPSR_GPSR(IP5_31_28, MMC_CMD),
671
672 /* IPSR6 */
673 PINMUX_IPSR_GPSR(IP6_3_0, VI1_DATA4),
674 PINMUX_IPSR_MSEL(IP6_3_0, CANFD_CLK_B, SEL_CANFD0_1),
675 PINMUX_IPSR_GPSR(IP6_3_0, D7),
676 PINMUX_IPSR_GPSR(IP6_3_0, MMC_D0),
677
678 PINMUX_IPSR_GPSR(IP6_7_4, VI1_DATA5),
679 PINMUX_IPSR_GPSR(IP6_7_4, D8),
680 PINMUX_IPSR_GPSR(IP6_7_4, MMC_D1),
681
682 PINMUX_IPSR_GPSR(IP6_11_8, VI1_DATA6),
683 PINMUX_IPSR_GPSR(IP6_11_8, D9),
684 PINMUX_IPSR_GPSR(IP6_11_8, MMC_D2),
685
686 PINMUX_IPSR_GPSR(IP6_15_12, VI1_DATA7),
687 PINMUX_IPSR_GPSR(IP6_15_12, D10),
688 PINMUX_IPSR_GPSR(IP6_15_12, MMC_D3),
689
690 PINMUX_IPSR_GPSR(IP6_19_16, VI1_DATA8),
691 PINMUX_IPSR_GPSR(IP6_19_16, D11),
692 PINMUX_IPSR_GPSR(IP6_19_16, MMC_CLK),
693
694 PINMUX_IPSR_GPSR(IP6_23_20, VI1_DATA9),
695 PINMUX_IPSR_MSEL(IP6_23_20, TCLK1_A, SEL_TMU_0),
696 PINMUX_IPSR_GPSR(IP6_23_20, D12),
697 PINMUX_IPSR_GPSR(IP6_23_20, MMC_D4),
698
699 PINMUX_IPSR_GPSR(IP6_27_24, VI1_DATA10),
700 PINMUX_IPSR_MSEL(IP6_27_24, TCLK2_A, SEL_TMU_0),
701 PINMUX_IPSR_GPSR(IP6_27_24, D13),
702 PINMUX_IPSR_GPSR(IP6_27_24, MMC_D5),
703
704 PINMUX_IPSR_GPSR(IP6_31_28, VI1_DATA11),
705 PINMUX_IPSR_GPSR(IP6_31_28, SCL4),
706 PINMUX_IPSR_GPSR(IP6_31_28, D14),
707 PINMUX_IPSR_GPSR(IP6_31_28, MMC_D6),
708
709 /* IPSR7 */
710 PINMUX_IPSR_GPSR(IP7_3_0, VI1_FIELD),
711 PINMUX_IPSR_GPSR(IP7_3_0, SDA4),
712 PINMUX_IPSR_GPSR(IP7_3_0, D15),
713 PINMUX_IPSR_GPSR(IP7_3_0, MMC_D7),
714
715 PINMUX_IPSR_GPSR(IP7_7_4, SCL0),
716 PINMUX_IPSR_GPSR(IP7_7_4, CLKOUT),
717
718 PINMUX_IPSR_GPSR(IP7_11_8, SDA0),
719 PINMUX_IPSR_GPSR(IP7_11_8, BS_N),
720 PINMUX_IPSR_GPSR(IP7_11_8, SCK0),
721 PINMUX_IPSR_MSEL(IP7_11_8, HSCK0_B, SEL_HSCIF0_1),
722
723 PINMUX_IPSR_GPSR(IP7_15_12, SCL1),
724 PINMUX_IPSR_GPSR(IP7_15_12, TPU0TO2),
725 PINMUX_IPSR_GPSR(IP7_15_12, RD_N),
726 PINMUX_IPSR_GPSR(IP7_15_12, CTS0_N),
727 PINMUX_IPSR_GPSR(IP7_15_12, HCTS0_N_B),
728
729 PINMUX_IPSR_GPSR(IP7_19_16, SDA1),
730 PINMUX_IPSR_GPSR(IP7_19_16, TPU0TO3),
731 PINMUX_IPSR_GPSR(IP7_19_16, WE0_N),
732 PINMUX_IPSR_GPSR(IP7_19_16, RTS0_N),
733 PINMUX_IPSR_MSEL(IP1_23_20, HRTS0_N_B, SEL_HSCIF0_1),
734
735 PINMUX_IPSR_GPSR(IP7_23_20, SCL2),
736 PINMUX_IPSR_GPSR(IP7_23_20, WE1_N),
737 PINMUX_IPSR_GPSR(IP7_23_20, RX0),
738 PINMUX_IPSR_MSEL(IP7_23_20, HRX0_B, SEL_HSCIF0_1),
739
740 PINMUX_IPSR_GPSR(IP7_27_24, SDA2),
741 PINMUX_IPSR_GPSR(IP7_27_24, EX_WAIT0),
742 PINMUX_IPSR_GPSR(IP7_27_24, TX0),
743 PINMUX_IPSR_MSEL(IP7_27_24, HTX0_B, SEL_HSCIF0_1),
744
745 PINMUX_IPSR_GPSR(IP7_31_28, AVB_AVTP_MATCH),
746 PINMUX_IPSR_GPSR(IP7_31_28, TPU0TO0),
747
748 /* IPSR8 */
749 PINMUX_IPSR_GPSR(IP8_3_0, AVB_AVTP_CAPTURE),
750 PINMUX_IPSR_GPSR(IP8_3_0, TPU0TO1),
751
752 PINMUX_IPSR_MSEL(IP8_7_4, CANFD0_TX_A, SEL_CANFD0_0),
753 PINMUX_IPSR_GPSR(IP8_7_4, FXR_TXDA),
754 PINMUX_IPSR_MSEL(IP8_7_4, PWM0_B, SEL_PWM0_1),
755 PINMUX_IPSR_GPSR(IP8_7_4, DU_DISP),
756
757 PINMUX_IPSR_MSEL(IP8_11_8, CANFD0_RX_A, SEL_CANFD0_0),
758 PINMUX_IPSR_GPSR(IP8_11_8, RXDA_EXTFXR),
759 PINMUX_IPSR_MSEL(IP8_11_8, PWM1_B, SEL_PWM1_1),
760 PINMUX_IPSR_GPSR(IP8_11_8, DU_CDE),
761
762 PINMUX_IPSR_GPSR(IP8_15_12, CANFD1_TX),
763 PINMUX_IPSR_GPSR(IP8_15_12, FXR_TXDB),
764 PINMUX_IPSR_MSEL(IP8_15_12, PWM2_B, SEL_PWM2_1),
765 PINMUX_IPSR_MSEL(IP8_15_12, TCLK1_B, SEL_TMU_1),
766 PINMUX_IPSR_MSEL(IP8_15_12, TX1_B, SEL_SCIF1_1),
767
768 PINMUX_IPSR_GPSR(IP8_19_16, CANFD1_RX),
769 PINMUX_IPSR_GPSR(IP8_19_16, RXDB_EXTFXR),
770 PINMUX_IPSR_MSEL(IP8_19_16, PWM3_B, SEL_PWM3_1),
771 PINMUX_IPSR_MSEL(IP8_19_16, TCLK2_B, SEL_TMU_1),
772 PINMUX_IPSR_MSEL(IP8_19_16, RX1_B, SEL_SCIF1_1),
773
774 PINMUX_IPSR_MSEL(IP8_23_20, CANFD_CLK_A, SEL_CANFD0_0),
775 PINMUX_IPSR_GPSR(IP8_23_20, CLK_EXTFXR),
776 PINMUX_IPSR_MSEL(IP8_23_20, PWM4_B, SEL_PWM4_1),
777 PINMUX_IPSR_MSEL(IP8_23_20, SPEEDIN_B, SEL_RSP_1),
778 PINMUX_IPSR_MSEL(IP8_23_20, SCIF_CLK_B, SEL_HSCIF0_1),
779
780 PINMUX_IPSR_GPSR(IP8_27_24, DIGRF_CLKIN),
781 PINMUX_IPSR_GPSR(IP8_27_24, DIGRF_CLKEN_IN),
782
783 PINMUX_IPSR_GPSR(IP8_31_28, DIGRF_CLKOUT),
784 PINMUX_IPSR_GPSR(IP8_31_28, DIGRF_CLKEN_OUT),
785
786 /* IPSR9 */
787 PINMUX_IPSR_GPSR(IP9_3_0, IRQ4),
788 PINMUX_IPSR_GPSR(IP9_3_0, VI0_DATA12),
789
790 PINMUX_IPSR_GPSR(IP9_7_4, IRQ5),
791 PINMUX_IPSR_GPSR(IP9_7_4, VI0_DATA13),
792
793 PINMUX_IPSR_GPSR(IP9_11_8, MSIOF0_RXD),
794 PINMUX_IPSR_GPSR(IP9_11_8, DU_DR0),
795 PINMUX_IPSR_GPSR(IP9_11_8, VI0_DATA14),
796
797 PINMUX_IPSR_GPSR(IP9_15_12, MSIOF0_TXD),
798 PINMUX_IPSR_GPSR(IP9_15_12, DU_DR1),
799 PINMUX_IPSR_GPSR(IP9_15_12, VI0_DATA15),
800
801 PINMUX_IPSR_GPSR(IP9_19_16, MSIOF0_SCK),
802 PINMUX_IPSR_GPSR(IP9_19_16, DU_DG0),
803 PINMUX_IPSR_GPSR(IP9_19_16, VI0_DATA16),
804
805 PINMUX_IPSR_GPSR(IP9_23_20, MSIOF0_SYNC),
806 PINMUX_IPSR_GPSR(IP9_23_20, DU_DG1),
807 PINMUX_IPSR_GPSR(IP9_23_20, VI0_DATA17),
808
809 PINMUX_IPSR_GPSR(IP9_27_24, MSIOF0_SS1),
810 PINMUX_IPSR_GPSR(IP9_27_24, DU_DB0),
811 PINMUX_IPSR_GPSR(IP9_27_24, TCLK3),
812 PINMUX_IPSR_GPSR(IP9_27_24, VI0_DATA18),
813
814 PINMUX_IPSR_GPSR(IP9_31_28, MSIOF0_SS2),
815 PINMUX_IPSR_GPSR(IP9_31_28, DU_DB1),
816 PINMUX_IPSR_GPSR(IP9_31_28, TCLK4),
817 PINMUX_IPSR_GPSR(IP9_31_28, VI0_DATA19),
818
819 /* IPSR10 */
820 PINMUX_IPSR_GPSR(IP10_3_0, SCL3),
821 PINMUX_IPSR_GPSR(IP10_3_0, VI0_DATA20),
822
823 PINMUX_IPSR_GPSR(IP10_7_4, SDA3),
824 PINMUX_IPSR_GPSR(IP10_7_4, VI0_DATA21),
825
826 PINMUX_IPSR_GPSR(IP10_11_8, FSO_CFE_0_N),
827 PINMUX_IPSR_GPSR(IP10_11_8, VI0_DATA22),
828
829 PINMUX_IPSR_GPSR(IP10_15_12, FSO_CFE_1_N),
830 PINMUX_IPSR_GPSR(IP10_15_12, VI0_DATA23),
831
832 PINMUX_IPSR_GPSR(IP10_19_16, FSO_TOE_N),
833 };
834
835 static const struct sh_pfc_pin pinmux_pins[] = {
836 PINMUX_GPIO_GP_ALL(),
837 };
838
839 /* - AVB -------------------------------------------------------------------- */
840 static const unsigned int avb_link_pins[] = {
841 /* AVB_LINK */
842 RCAR_GP_PIN(1, 18),
843 };
844 static const unsigned int avb_link_mux[] = {
845 AVB_LINK_MARK,
846 };
847 static const unsigned int avb_magic_pins[] = {
848 /* AVB_MAGIC */
849 RCAR_GP_PIN(1, 16),
850 };
851 static const unsigned int avb_magic_mux[] = {
852 AVB_MAGIC_MARK,
853 };
854 static const unsigned int avb_phy_int_pins[] = {
855 /* AVB_PHY_INT */
856 RCAR_GP_PIN(1, 17),
857 };
858 static const unsigned int avb_phy_int_mux[] = {
859 AVB_PHY_INT_MARK,
860 };
861 static const unsigned int avb_mdio_pins[] = {
862 /* AVB_MDC, AVB_MDIO */
863 RCAR_GP_PIN(1, 15), RCAR_GP_PIN(1, 14),
864 };
865 static const unsigned int avb_mdio_mux[] = {
866 AVB_MDC_MARK, AVB_MDIO_MARK,
867 };
868 static const unsigned int avb_rgmii_pins[] = {
869 /*
870 * AVB_TX_CTL, AVB_TXC, AVB_TD0, AVB_TD1, AVB_TD2, AVB_TD3,
871 * AVB_RX_CTL, AVB_RXC, AVB_RD0, AVB_RD1, AVB_RD2, AVB_RD3,
872 */
873 RCAR_GP_PIN(1, 7), RCAR_GP_PIN(1, 8),
874 RCAR_GP_PIN(1, 9), RCAR_GP_PIN(1, 10),
875 RCAR_GP_PIN(1, 11), RCAR_GP_PIN(1, 12),
876 RCAR_GP_PIN(1, 1), RCAR_GP_PIN(1, 2),
877 RCAR_GP_PIN(1, 3), RCAR_GP_PIN(1, 4),
878 RCAR_GP_PIN(1, 5), RCAR_GP_PIN(1, 6),
879 };
880 static const unsigned int avb_rgmii_mux[] = {
881 AVB_TX_CTL_MARK, AVB_TXC_MARK,
882 AVB_TD0_MARK, AVB_TD1_MARK, AVB_TD2_MARK, AVB_TD3_MARK,
883 AVB_RX_CTL_MARK, AVB_RXC_MARK,
884 AVB_RD0_MARK, AVB_RD1_MARK, AVB_RD2_MARK, AVB_RD3_MARK,
885 };
886 static const unsigned int avb_txcrefclk_pins[] = {
887 /* AVB_TXCREFCLK */
888 RCAR_GP_PIN(1, 13),
889 };
890 static const unsigned int avb_txcrefclk_mux[] = {
891 AVB_TXCREFCLK_MARK,
892 };
893 static const unsigned int avb_avtp_pps_pins[] = {
894 /* AVB_AVTP_PPS */
895 RCAR_GP_PIN(2, 6),
896 };
897 static const unsigned int avb_avtp_pps_mux[] = {
898 AVB_AVTP_PPS_MARK,
899 };
900 static const unsigned int avb_avtp_capture_pins[] = {
901 /* AVB_AVTP_CAPTURE */
902 RCAR_GP_PIN(1, 20),
903 };
904 static const unsigned int avb_avtp_capture_mux[] = {
905 AVB_AVTP_CAPTURE_MARK,
906 };
907 static const unsigned int avb_avtp_match_pins[] = {
908 /* AVB_AVTP_MATCH */
909 RCAR_GP_PIN(1, 19),
910 };
911 static const unsigned int avb_avtp_match_mux[] = {
912 AVB_AVTP_MATCH_MARK,
913 };
914
915 /* - CANFD0 ----------------------------------------------------------------- */
916 static const unsigned int canfd0_data_a_pins[] = {
917 /* CANFD0_TX, CANFD0_RX */
918 RCAR_GP_PIN(1, 21), RCAR_GP_PIN(1, 22),
919 };
920 static const unsigned int canfd0_data_a_mux[] = {
921 CANFD0_TX_A_MARK, CANFD0_RX_A_MARK,
922 };
923 static const unsigned int canfd0_data_b_pins[] = {
924 /* CANFD0_TX, CANFD0_RX */
925 RCAR_GP_PIN(3, 6), RCAR_GP_PIN(3, 7),
926 };
927 static const unsigned int canfd0_data_b_mux[] = {
928 CANFD0_TX_B_MARK, CANFD0_RX_B_MARK,
929 };
930
931 /* - CANFD1 ----------------------------------------------------------------- */
932 static const unsigned int canfd1_data_pins[] = {
933 /* CANFD1_TX, CANFD1_RX */
934 RCAR_GP_PIN(1, 23), RCAR_GP_PIN(1, 24),
935 };
936 static const unsigned int canfd1_data_mux[] = {
937 CANFD1_TX_MARK, CANFD1_RX_MARK,
938 };
939
940 /* - CANFD Clock ------------------------------------------------------------ */
941 static const unsigned int canfd_clk_a_pins[] = {
942 /* CANFD_CLK */
943 RCAR_GP_PIN(1, 25),
944 };
945 static const unsigned int canfd_clk_a_mux[] = {
946 CANFD_CLK_A_MARK,
947 };
948 static const unsigned int canfd_clk_b_pins[] = {
949 /* CANFD_CLK */
950 RCAR_GP_PIN(3, 8),
951 };
952 static const unsigned int canfd_clk_b_mux[] = {
953 CANFD_CLK_B_MARK,
954 };
955
956 /* - DU --------------------------------------------------------------------- */
957 static const unsigned int du_rgb666_pins[] = {
958 /* DU_DR[7:2], DU_DG[7:2], DU_DB[7:2] */
959 RCAR_GP_PIN(0, 5), RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 3),
960 RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 1), RCAR_GP_PIN(0, 0),
961 RCAR_GP_PIN(0, 11), RCAR_GP_PIN(0, 10), RCAR_GP_PIN(0, 9),
962 RCAR_GP_PIN(0, 8), RCAR_GP_PIN(0, 7), RCAR_GP_PIN(0, 6),
963 RCAR_GP_PIN(0, 17), RCAR_GP_PIN(0, 16), RCAR_GP_PIN(0, 15),
964 RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 13), RCAR_GP_PIN(0, 12),
965 };
966 static const unsigned int du_rgb666_mux[] = {
967 DU_DR7_MARK, DU_DR6_MARK, DU_DR5_MARK,
968 DU_DR4_MARK, DU_DR3_MARK, DU_DR2_MARK,
969 DU_DG7_MARK, DU_DG6_MARK, DU_DG5_MARK,
970 DU_DG4_MARK, DU_DG3_MARK, DU_DG2_MARK,
971 DU_DB7_MARK, DU_DB6_MARK, DU_DB5_MARK,
972 DU_DB4_MARK, DU_DB3_MARK, DU_DB2_MARK,
973 };
974 static const unsigned int du_rgb888_pins[] = {
975 /* DU_DR[7:0], DU_DG[7:0], DU_DB[7:0] */
976 RCAR_GP_PIN(0, 5), RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 3),
977 RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 1), RCAR_GP_PIN(0, 0),
978 RCAR_GP_PIN(2, 20), RCAR_GP_PIN(2, 19),
979 RCAR_GP_PIN(0, 11), RCAR_GP_PIN(0, 10), RCAR_GP_PIN(0, 9),
980 RCAR_GP_PIN(0, 8), RCAR_GP_PIN(0, 7), RCAR_GP_PIN(0, 6),
981 RCAR_GP_PIN(2, 22), RCAR_GP_PIN(2, 21),
982 RCAR_GP_PIN(0, 17), RCAR_GP_PIN(0, 16), RCAR_GP_PIN(0, 15),
983 RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 13), RCAR_GP_PIN(0, 12),
984 RCAR_GP_PIN(2, 24), RCAR_GP_PIN(2, 23),
985 };
986 static const unsigned int du_rgb888_mux[] = {
987 DU_DR7_MARK, DU_DR6_MARK, DU_DR5_MARK,
988 DU_DR4_MARK, DU_DR3_MARK, DU_DR2_MARK,
989 DU_DR1_MARK, DU_DR0_MARK,
990 DU_DG7_MARK, DU_DG6_MARK, DU_DG5_MARK,
991 DU_DG4_MARK, DU_DG3_MARK, DU_DG2_MARK,
992 DU_DG1_MARK, DU_DG0_MARK,
993 DU_DB7_MARK, DU_DB6_MARK, DU_DB5_MARK,
994 DU_DB4_MARK, DU_DB3_MARK, DU_DB2_MARK,
995 DU_DB1_MARK, DU_DB0_MARK,
996 };
997 static const unsigned int du_clk_out_pins[] = {
998 /* DU_DOTCLKOUT */
999 RCAR_GP_PIN(0, 18),
1000 };
1001 static const unsigned int du_clk_out_mux[] = {
1002 DU_DOTCLKOUT_MARK,
1003 };
1004 static const unsigned int du_sync_pins[] = {
1005 /* DU_EXVSYNC/DU_VSYNC, DU_EXHSYNC/DU_HSYNC */
1006 RCAR_GP_PIN(0, 20), RCAR_GP_PIN(0, 19),
1007 };
1008 static const unsigned int du_sync_mux[] = {
1009 DU_EXVSYNC_DU_VSYNC_MARK, DU_EXHSYNC_DU_HSYNC_MARK,
1010 };
1011 static const unsigned int du_oddf_pins[] = {
1012 /* DU_EXODDF/DU_ODDF/DISP/CDE */
1013 RCAR_GP_PIN(0, 21),
1014 };
1015 static const unsigned int du_oddf_mux[] = {
1016 DU_EXODDF_DU_ODDF_DISP_CDE_MARK,
1017 };
1018 static const unsigned int du_cde_pins[] = {
1019 /* DU_CDE */
1020 RCAR_GP_PIN(1, 22),
1021 };
1022 static const unsigned int du_cde_mux[] = {
1023 DU_CDE_MARK,
1024 };
1025 static const unsigned int du_disp_pins[] = {
1026 /* DU_DISP */
1027 RCAR_GP_PIN(1, 21),
1028 };
1029 static const unsigned int du_disp_mux[] = {
1030 DU_DISP_MARK,
1031 };
1032
1033 /* - GETHER ----------------------------------------------------------------- */
1034 static const unsigned int gether_link_a_pins[] = {
1035 /* GETHER_LINK */
1036 RCAR_GP_PIN(4, 24),
1037 };
1038 static const unsigned int gether_link_a_mux[] = {
1039 GETHER_LINK_A_MARK,
1040 };
1041 static const unsigned int gether_phy_int_a_pins[] = {
1042 /* GETHER_PHY_INT */
1043 RCAR_GP_PIN(4, 23),
1044 };
1045 static const unsigned int gether_phy_int_a_mux[] = {
1046 GETHER_PHY_INT_A_MARK,
1047 };
1048 static const unsigned int gether_mdio_a_pins[] = {
1049 /* GETHER_MDC, GETHER_MDIO */
1050 RCAR_GP_PIN(4, 21), RCAR_GP_PIN(4, 20),
1051 };
1052 static const unsigned int gether_mdio_a_mux[] = {
1053 GETHER_MDC_A_MARK, GETHER_MDIO_A_MARK,
1054 };
1055 static const unsigned int gether_link_b_pins[] = {
1056 /* GETHER_LINK */
1057 RCAR_GP_PIN(0, 18),
1058 };
1059 static const unsigned int gether_link_b_mux[] = {
1060 GETHER_LINK_B_MARK,
1061 };
1062 static const unsigned int gether_phy_int_b_pins[] = {
1063 /* GETHER_PHY_INT */
1064 RCAR_GP_PIN(0, 19),
1065 };
1066 static const unsigned int gether_phy_int_b_mux[] = {
1067 GETHER_PHY_INT_B_MARK,
1068 };
1069 static const unsigned int gether_mdio_b_mux[] = {
1070 GETHER_MDC_B_MARK, GETHER_MDIO_B_MARK,
1071 };
1072 static const unsigned int gether_mdio_b_pins[] = {
1073 /* GETHER_MDC, GETHER_MDIO */
1074 RCAR_GP_PIN(0, 9), RCAR_GP_PIN(0, 10),
1075 };
1076 static const unsigned int gether_magic_pins[] = {
1077 /* GETHER_MAGIC */
1078 RCAR_GP_PIN(4, 22),
1079 };
1080 static const unsigned int gether_magic_mux[] = {
1081 GETHER_MAGIC_MARK,
1082 };
1083 static const unsigned int gether_rgmii_pins[] = {
1084 /*
1085 * GETHER_TX_CTL, GETHER_TXC,
1086 * GETHER_TD0, GETHER_TD1, GETHER_TD2, GETHER_TD3,
1087 * GETHER_RX_CTL, GETHER_RXC,
1088 * GETHER_RD0, GETHER_RD1, GETHER_RD2, GETHER_RD3,
1089 */
1090 RCAR_GP_PIN(4, 12), RCAR_GP_PIN(4, 13),
1091 RCAR_GP_PIN(4, 14), RCAR_GP_PIN(4, 15),
1092 RCAR_GP_PIN(4, 16), RCAR_GP_PIN(4, 17),
1093 RCAR_GP_PIN(4, 6), RCAR_GP_PIN(4, 7),
1094 RCAR_GP_PIN(4, 8), RCAR_GP_PIN(4, 9),
1095 RCAR_GP_PIN(4, 10), RCAR_GP_PIN(4, 11),
1096 };
1097 static const unsigned int gether_rgmii_mux[] = {
1098 GETHER_TX_CTL_MARK, GETHER_TXC_MARK,
1099 GETHER_TD0_MARK, GETHER_TD1_MARK,
1100 GETHER_TD2_MARK, GETHER_TD3_MARK,
1101 GETHER_RX_CTL_MARK, GETHER_RXC_MARK,
1102 GETHER_RD0_MARK, AVB_RD1_MARK,
1103 GETHER_RD2_MARK, AVB_RD3_MARK,
1104 };
1105 static const unsigned int gether_txcrefclk_pins[] = {
1106 /* GETHER_TXCREFCLK */
1107 RCAR_GP_PIN(4, 18),
1108 };
1109 static const unsigned int gether_txcrefclk_mux[] = {
1110 GETHER_TXCREFCLK_MARK,
1111 };
1112 static const unsigned int gether_txcrefclk_mega_pins[] = {
1113 /* GETHER_TXCREFCLK_MEGA */
1114 RCAR_GP_PIN(4, 19),
1115 };
1116 static const unsigned int gether_txcrefclk_mega_mux[] = {
1117 GETHER_TXCREFCLK_MEGA_MARK,
1118 };
1119 static const unsigned int gether_rmii_pins[] = {
1120 /*
1121 * GETHER_RMII_CRS_DV, GETHER_RMII_RX_ER,
1122 * GETHER_RMII_RXD0, GETHER_RMII_RXD1,
1123 * GETHER_RMII_TXD_EN, GETHER_RMII_TXD0,
1124 * GETHER_RMII_TXD1, GETHER_RMII_REFCLK
1125 */
1126 RCAR_GP_PIN(0, 0), RCAR_GP_PIN(0, 1),
1127 RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3),
1128 RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5),
1129 RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7),
1130 };
1131 static const unsigned int gether_rmii_mux[] = {
1132 GETHER_RMII_CRS_DV_MARK, GETHER_RMII_RX_ER_MARK,
1133 GETHER_RMII_RXD0_MARK, GETHER_RMII_RXD1_MARK,
1134 GETHER_RMII_TXD_EN_MARK, GETHER_RMII_TXD0_MARK,
1135 GETHER_RMII_TXD1_MARK, GETHER_RMII_REFCLK_MARK,
1136 };
1137
1138 /* - HSCIF0 ----------------------------------------------------------------- */
1139 static const unsigned int hscif0_data_a_pins[] = {
1140 /* HRX0, HTX0 */
1141 RCAR_GP_PIN(0, 11), RCAR_GP_PIN(0, 15),
1142 };
1143 static const unsigned int hscif0_data_a_mux[] = {
1144 HRX0_A_MARK, HTX0_A_MARK,
1145 };
1146 static const unsigned int hscif0_clk_a_pins[] = {
1147 /* HSCK0 */
1148 RCAR_GP_PIN(0, 12),
1149 };
1150 static const unsigned int hscif0_clk_a_mux[] = {
1151 HSCK0_A_MARK,
1152 };
1153 static const unsigned int hscif0_ctrl_a_pins[] = {
1154 /* HRTS0#, HCTS0# */
1155 RCAR_GP_PIN(0, 13), RCAR_GP_PIN(0, 14),
1156 };
1157 static const unsigned int hscif0_ctrl_a_mux[] = {
1158 HRTS0_N_A_MARK, HCTS0_N_A_MARK,
1159 };
1160 static const unsigned int hscif0_data_b_pins[] = {
1161 /* HRX0, HTX0 */
1162 RCAR_GP_PIN(4, 4), RCAR_GP_PIN(4, 5),
1163 };
1164 static const unsigned int hscif0_data_b_mux[] = {
1165 HRX0_B_MARK, HTX0_B_MARK,
1166 };
1167 static const unsigned int hscif0_clk_b_pins[] = {
1168 /* HSCK0 */
1169 RCAR_GP_PIN(4, 1),
1170 };
1171 static const unsigned int hscif0_clk_b_mux[] = {
1172 HSCK0_B_MARK,
1173 };
1174 static const unsigned int hscif0_ctrl_b_pins[] = {
1175 /* HRTS0#, HCTS0# */
1176 RCAR_GP_PIN(4, 3), RCAR_GP_PIN(4, 2),
1177 };
1178 static const unsigned int hscif0_ctrl_b_mux[] = {
1179 HRTS0_N_B_MARK, HCTS0_N_B_MARK,
1180 };
1181
1182 /* - HSCIF1 ----------------------------------------------------------------- */
1183 static const unsigned int hscif1_data_pins[] = {
1184 /* HRX1, HTX1 */
1185 RCAR_GP_PIN(2, 11), RCAR_GP_PIN(2, 10),
1186 };
1187 static const unsigned int hscif1_data_mux[] = {
1188 HRX1_MARK, HTX1_MARK,
1189 };
1190 static const unsigned int hscif1_clk_pins[] = {
1191 /* HSCK1 */
1192 RCAR_GP_PIN(2, 7),
1193 };
1194 static const unsigned int hscif1_clk_mux[] = {
1195 HSCK1_MARK,
1196 };
1197 static const unsigned int hscif1_ctrl_pins[] = {
1198 /* HRTS1#, HCTS1# */
1199 RCAR_GP_PIN(2, 8), RCAR_GP_PIN(2, 9),
1200 };
1201 static const unsigned int hscif1_ctrl_mux[] = {
1202 HRTS1_N_MARK, HCTS1_N_MARK,
1203 };
1204
1205 /* - HSCIF2 ----------------------------------------------------------------- */
1206 static const unsigned int hscif2_data_pins[] = {
1207 /* HRX2, HTX2 */
1208 RCAR_GP_PIN(2, 16), RCAR_GP_PIN(2, 15),
1209 };
1210 static const unsigned int hscif2_data_mux[] = {
1211 HRX2_MARK, HTX2_MARK,
1212 };
1213 static const unsigned int hscif2_clk_pins[] = {
1214 /* HSCK2 */
1215 RCAR_GP_PIN(2, 12),
1216 };
1217 static const unsigned int hscif2_clk_mux[] = {
1218 HSCK2_MARK,
1219 };
1220 static const unsigned int hscif2_ctrl_pins[] = {
1221 /* HRTS2#, HCTS2# */
1222 RCAR_GP_PIN(2, 14), RCAR_GP_PIN(2, 13),
1223 };
1224 static const unsigned int hscif2_ctrl_mux[] = {
1225 HRTS2_N_MARK, HCTS2_N_MARK,
1226 };
1227
1228 /* - HSCIF3 ----------------------------------------------------------------- */
1229 static const unsigned int hscif3_data_pins[] = {
1230 /* HRX3, HTX3 */
1231 RCAR_GP_PIN(2, 4), RCAR_GP_PIN(2, 3),
1232 };
1233 static const unsigned int hscif3_data_mux[] = {
1234 HRX3_MARK, HTX3_MARK,
1235 };
1236 static const unsigned int hscif3_clk_pins[] = {
1237 /* HSCK3 */
1238 RCAR_GP_PIN(2, 0),
1239 };
1240 static const unsigned int hscif3_clk_mux[] = {
1241 HSCK3_MARK,
1242 };
1243 static const unsigned int hscif3_ctrl_pins[] = {
1244 /* HRTS3#, HCTS3# */
1245 RCAR_GP_PIN(2, 2), RCAR_GP_PIN(2, 1),
1246 };
1247 static const unsigned int hscif3_ctrl_mux[] = {
1248 HRTS3_N_MARK, HCTS3_N_MARK,
1249 };
1250
1251 /* - I2C0 ------------------------------------------------------------------- */
1252 static const unsigned int i2c0_pins[] = {
1253 /* SDA0, SCL0 */
1254 RCAR_GP_PIN(4, 1), RCAR_GP_PIN(4, 0),
1255 };
1256 static const unsigned int i2c0_mux[] = {
1257 SDA0_MARK, SCL0_MARK,
1258 };
1259
1260 /* - I2C1 ------------------------------------------------------------------- */
1261 static const unsigned int i2c1_pins[] = {
1262 /* SDA1, SCL1 */
1263 RCAR_GP_PIN(4, 3), RCAR_GP_PIN(4, 2),
1264 };
1265 static const unsigned int i2c1_mux[] = {
1266 SDA1_MARK, SCL1_MARK,
1267 };
1268
1269 /* - I2C2 ------------------------------------------------------------------- */
1270 static const unsigned int i2c2_pins[] = {
1271 /* SDA2, SCL2 */
1272 RCAR_GP_PIN(4, 5), RCAR_GP_PIN(4, 4),
1273 };
1274 static const unsigned int i2c2_mux[] = {
1275 SDA2_MARK, SCL2_MARK,
1276 };
1277
1278 /* - I2C3 ------------------------------------------------------------------- */
1279 static const unsigned int i2c3_pins[] = {
1280 /* SDA3, SCL3 */
1281 RCAR_GP_PIN(2, 26), RCAR_GP_PIN(2, 25),
1282 };
1283 static const unsigned int i2c3_mux[] = {
1284 SDA3_MARK, SCL3_MARK,
1285 };
1286
1287 /* - I2C4 ------------------------------------------------------------------- */
1288 static const unsigned int i2c4_pins[] = {
1289 /* SDA4, SCL4 */
1290 RCAR_GP_PIN(3, 16), RCAR_GP_PIN(3, 15),
1291 };
1292 static const unsigned int i2c4_mux[] = {
1293 SDA4_MARK, SCL4_MARK,
1294 };
1295
1296 /* - I2C5 ------------------------------------------------------------------- */
1297 static const unsigned int i2c5_pins[] = {
1298 /* SDA5, SCL5 */
1299 RCAR_GP_PIN(0, 9), RCAR_GP_PIN(0, 8),
1300 };
1301 static const unsigned int i2c5_mux[] = {
1302 SDA5_MARK, SCL5_MARK,
1303 };
1304
1305 /* - INTC-EX ---------------------------------------------------------------- */
1306 static const unsigned int intc_ex_irq0_pins[] = {
1307 /* IRQ0 */
1308 RCAR_GP_PIN(1, 0),
1309 };
1310 static const unsigned int intc_ex_irq0_mux[] = {
1311 IRQ0_MARK,
1312 };
1313 static const unsigned int intc_ex_irq1_pins[] = {
1314 /* IRQ1 */
1315 RCAR_GP_PIN(0, 12),
1316 };
1317 static const unsigned int intc_ex_irq1_mux[] = {
1318 IRQ1_MARK,
1319 };
1320 static const unsigned int intc_ex_irq2_pins[] = {
1321 /* IRQ2 */
1322 RCAR_GP_PIN(0, 13),
1323 };
1324 static const unsigned int intc_ex_irq2_mux[] = {
1325 IRQ2_MARK,
1326 };
1327 static const unsigned int intc_ex_irq3_pins[] = {
1328 /* IRQ3 */
1329 RCAR_GP_PIN(0, 14),
1330 };
1331 static const unsigned int intc_ex_irq3_mux[] = {
1332 IRQ3_MARK,
1333 };
1334 static const unsigned int intc_ex_irq4_pins[] = {
1335 /* IRQ4 */
1336 RCAR_GP_PIN(2, 17),
1337 };
1338 static const unsigned int intc_ex_irq4_mux[] = {
1339 IRQ4_MARK,
1340 };
1341 static const unsigned int intc_ex_irq5_pins[] = {
1342 /* IRQ5 */
1343 RCAR_GP_PIN(2, 18),
1344 };
1345 static const unsigned int intc_ex_irq5_mux[] = {
1346 IRQ5_MARK,
1347 };
1348
1349 /* - MMC -------------------------------------------------------------------- */
1350 static const unsigned int mmc_data1_pins[] = {
1351 /* MMC_D0 */
1352 RCAR_GP_PIN(3, 8),
1353 };
1354 static const unsigned int mmc_data1_mux[] = {
1355 MMC_D0_MARK,
1356 };
1357 static const unsigned int mmc_data4_pins[] = {
1358 /* MMC_D[0:3] */
1359 RCAR_GP_PIN(3, 8), RCAR_GP_PIN(3, 9),
1360 RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11),
1361 };
1362 static const unsigned int mmc_data4_mux[] = {
1363 MMC_D0_MARK, MMC_D1_MARK,
1364 MMC_D2_MARK, MMC_D3_MARK,
1365 };
1366 static const unsigned int mmc_data8_pins[] = {
1367 /* MMC_D[0:7] */
1368 RCAR_GP_PIN(3, 8), RCAR_GP_PIN(3, 9),
1369 RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11),
1370 RCAR_GP_PIN(3, 13), RCAR_GP_PIN(3, 14),
1371 RCAR_GP_PIN(3, 15), RCAR_GP_PIN(3, 16),
1372 };
1373 static const unsigned int mmc_data8_mux[] = {
1374 MMC_D0_MARK, MMC_D1_MARK,
1375 MMC_D2_MARK, MMC_D3_MARK,
1376 MMC_D4_MARK, MMC_D5_MARK,
1377 MMC_D6_MARK, MMC_D7_MARK,
1378 };
1379 static const unsigned int mmc_ctrl_pins[] = {
1380 /* MMC_CLK, MMC_CMD */
1381 RCAR_GP_PIN(3, 12), RCAR_GP_PIN(3, 7),
1382 };
1383 static const unsigned int mmc_ctrl_mux[] = {
1384 MMC_CLK_MARK, MMC_CMD_MARK,
1385 };
1386 static const unsigned int mmc_cd_pins[] = {
1387 /* MMC_CD */
1388 RCAR_GP_PIN(3, 5),
1389 };
1390 static const unsigned int mmc_cd_mux[] = {
1391 MMC_CD_MARK,
1392 };
1393 static const unsigned int mmc_wp_pins[] = {
1394 /* MMC_WP */
1395 RCAR_GP_PIN(3, 4),
1396 };
1397 static const unsigned int mmc_wp_mux[] = {
1398 MMC_WP_MARK,
1399 };
1400 static const unsigned int mmc_ds_pins[] = {
1401 /* MMC_DS */
1402 RCAR_GP_PIN(3, 6),
1403 };
1404 static const unsigned int mmc_ds_mux[] = {
1405 MMC_DS_MARK,
1406 };
1407
1408 /* - MSIOF0 ----------------------------------------------------------------- */
1409 static const unsigned int msiof0_clk_pins[] = {
1410 /* MSIOF0_SCK */
1411 RCAR_GP_PIN(2, 21),
1412 };
1413 static const unsigned int msiof0_clk_mux[] = {
1414 MSIOF0_SCK_MARK,
1415 };
1416 static const unsigned int msiof0_sync_pins[] = {
1417 /* MSIOF0_SYNC */
1418 RCAR_GP_PIN(2, 22),
1419 };
1420 static const unsigned int msiof0_sync_mux[] = {
1421 MSIOF0_SYNC_MARK,
1422 };
1423 static const unsigned int msiof0_ss1_pins[] = {
1424 /* MSIOF0_SS1 */
1425 RCAR_GP_PIN(2, 23),
1426 };
1427 static const unsigned int msiof0_ss1_mux[] = {
1428 MSIOF0_SS1_MARK,
1429 };
1430 static const unsigned int msiof0_ss2_pins[] = {
1431 /* MSIOF0_SS2 */
1432 RCAR_GP_PIN(2, 24),
1433 };
1434 static const unsigned int msiof0_ss2_mux[] = {
1435 MSIOF0_SS2_MARK,
1436 };
1437 static const unsigned int msiof0_txd_pins[] = {
1438 /* MSIOF0_TXD */
1439 RCAR_GP_PIN(2, 20),
1440 };
1441 static const unsigned int msiof0_txd_mux[] = {
1442 MSIOF0_TXD_MARK,
1443 };
1444 static const unsigned int msiof0_rxd_pins[] = {
1445 /* MSIOF0_RXD */
1446 RCAR_GP_PIN(2, 19),
1447 };
1448 static const unsigned int msiof0_rxd_mux[] = {
1449 MSIOF0_RXD_MARK,
1450 };
1451
1452 /* - MSIOF1 ----------------------------------------------------------------- */
1453 static const unsigned int msiof1_clk_pins[] = {
1454 /* MSIOF1_SCK */
1455 RCAR_GP_PIN(3, 2),
1456 };
1457 static const unsigned int msiof1_clk_mux[] = {
1458 MSIOF1_SCK_MARK,
1459 };
1460 static const unsigned int msiof1_sync_pins[] = {
1461 /* MSIOF1_SYNC */
1462 RCAR_GP_PIN(3, 3),
1463 };
1464 static const unsigned int msiof1_sync_mux[] = {
1465 MSIOF1_SYNC_MARK,
1466 };
1467 static const unsigned int msiof1_ss1_pins[] = {
1468 /* MSIOF1_SS1 */
1469 RCAR_GP_PIN(3, 4),
1470 };
1471 static const unsigned int msiof1_ss1_mux[] = {
1472 MSIOF1_SS1_MARK,
1473 };
1474 static const unsigned int msiof1_ss2_pins[] = {
1475 /* MSIOF1_SS2 */
1476 RCAR_GP_PIN(3, 5),
1477 };
1478 static const unsigned int msiof1_ss2_mux[] = {
1479 MSIOF1_SS2_MARK,
1480 };
1481 static const unsigned int msiof1_txd_pins[] = {
1482 /* MSIOF1_TXD */
1483 RCAR_GP_PIN(3, 1),
1484 };
1485 static const unsigned int msiof1_txd_mux[] = {
1486 MSIOF1_TXD_MARK,
1487 };
1488 static const unsigned int msiof1_rxd_pins[] = {
1489 /* MSIOF1_RXD */
1490 RCAR_GP_PIN(3, 0),
1491 };
1492 static const unsigned int msiof1_rxd_mux[] = {
1493 MSIOF1_RXD_MARK,
1494 };
1495
1496 /* - MSIOF2 ----------------------------------------------------------------- */
1497 static const unsigned int msiof2_clk_pins[] = {
1498 /* MSIOF2_SCK */
1499 RCAR_GP_PIN(2, 0),
1500 };
1501 static const unsigned int msiof2_clk_mux[] = {
1502 MSIOF2_SCK_MARK,
1503 };
1504 static const unsigned int msiof2_sync_pins[] = {
1505 /* MSIOF2_SYNC */
1506 RCAR_GP_PIN(2, 3),
1507 };
1508 static const unsigned int msiof2_sync_mux[] = {
1509 MSIOF2_SYNC_MARK,
1510 };
1511 static const unsigned int msiof2_ss1_pins[] = {
1512 /* MSIOF2_SS1 */
1513 RCAR_GP_PIN(2, 4),
1514 };
1515 static const unsigned int msiof2_ss1_mux[] = {
1516 MSIOF2_SS1_MARK,
1517 };
1518 static const unsigned int msiof2_ss2_pins[] = {
1519 /* MSIOF2_SS2 */
1520 RCAR_GP_PIN(2, 5),
1521 };
1522 static const unsigned int msiof2_ss2_mux[] = {
1523 MSIOF2_SS2_MARK,
1524 };
1525 static const unsigned int msiof2_txd_pins[] = {
1526 /* MSIOF2_TXD */
1527 RCAR_GP_PIN(2, 2),
1528 };
1529 static const unsigned int msiof2_txd_mux[] = {
1530 MSIOF2_TXD_MARK,
1531 };
1532 static const unsigned int msiof2_rxd_pins[] = {
1533 /* MSIOF2_RXD */
1534 RCAR_GP_PIN(2, 1),
1535 };
1536 static const unsigned int msiof2_rxd_mux[] = {
1537 MSIOF2_RXD_MARK,
1538 };
1539
1540 /* - MSIOF3 ----------------------------------------------------------------- */
1541 static const unsigned int msiof3_clk_pins[] = {
1542 /* MSIOF3_SCK */
1543 RCAR_GP_PIN(0, 20),
1544 };
1545 static const unsigned int msiof3_clk_mux[] = {
1546 MSIOF3_SCK_MARK,
1547 };
1548 static const unsigned int msiof3_sync_pins[] = {
1549 /* MSIOF3_SYNC */
1550 RCAR_GP_PIN(0, 21),
1551 };
1552 static const unsigned int msiof3_sync_mux[] = {
1553 MSIOF3_SYNC_MARK,
1554 };
1555 static const unsigned int msiof3_ss1_pins[] = {
1556 /* MSIOF3_SS1 */
1557 RCAR_GP_PIN(0, 18),
1558 };
1559 static const unsigned int msiof3_ss1_mux[] = {
1560 MSIOF3_SS1_MARK,
1561 };
1562 static const unsigned int msiof3_ss2_pins[] = {
1563 /* MSIOF3_SS2 */
1564 RCAR_GP_PIN(0, 19),
1565 };
1566 static const unsigned int msiof3_ss2_mux[] = {
1567 MSIOF3_SS2_MARK,
1568 };
1569 static const unsigned int msiof3_txd_pins[] = {
1570 /* MSIOF3_TXD */
1571 RCAR_GP_PIN(0, 17),
1572 };
1573 static const unsigned int msiof3_txd_mux[] = {
1574 MSIOF3_TXD_MARK,
1575 };
1576 static const unsigned int msiof3_rxd_pins[] = {
1577 /* MSIOF3_RXD */
1578 RCAR_GP_PIN(0, 16),
1579 };
1580 static const unsigned int msiof3_rxd_mux[] = {
1581 MSIOF3_RXD_MARK,
1582 };
1583
1584 /* - PWM0 ------------------------------------------------------------------- */
1585 static const unsigned int pwm0_a_pins[] = {
1586 /* PWM0 */
1587 RCAR_GP_PIN(0, 15),
1588 };
1589 static const unsigned int pwm0_a_mux[] = {
1590 PWM0_A_MARK,
1591 };
1592 static const unsigned int pwm0_b_pins[] = {
1593 /* PWM0 */
1594 RCAR_GP_PIN(1, 21),
1595 };
1596 static const unsigned int pwm0_b_mux[] = {
1597 PWM0_B_MARK,
1598 };
1599
1600 /* - PWM1 ------------------------------------------------------------------- */
1601 static const unsigned int pwm1_a_pins[] = {
1602 /* PWM1 */
1603 RCAR_GP_PIN(2, 13),
1604 };
1605 static const unsigned int pwm1_a_mux[] = {
1606 PWM1_A_MARK,
1607 };
1608 static const unsigned int pwm1_b_pins[] = {
1609 /* PWM1 */
1610 RCAR_GP_PIN(1, 22),
1611 };
1612 static const unsigned int pwm1_b_mux[] = {
1613 PWM1_B_MARK,
1614 };
1615
1616 /* - PWM2 ------------------------------------------------------------------- */
1617 static const unsigned int pwm2_a_pins[] = {
1618 /* PWM2 */
1619 RCAR_GP_PIN(2, 14),
1620 };
1621 static const unsigned int pwm2_a_mux[] = {
1622 PWM2_A_MARK,
1623 };
1624 static const unsigned int pwm2_b_pins[] = {
1625 /* PWM2 */
1626 RCAR_GP_PIN(1, 23),
1627 };
1628 static const unsigned int pwm2_b_mux[] = {
1629 PWM2_B_MARK,
1630 };
1631
1632 /* - PWM3 ------------------------------------------------------------------- */
1633 static const unsigned int pwm3_a_pins[] = {
1634 /* PWM3 */
1635 RCAR_GP_PIN(2, 15),
1636 };
1637 static const unsigned int pwm3_a_mux[] = {
1638 PWM3_A_MARK,
1639 };
1640 static const unsigned int pwm3_b_pins[] = {
1641 /* PWM3 */
1642 RCAR_GP_PIN(1, 24),
1643 };
1644 static const unsigned int pwm3_b_mux[] = {
1645 PWM3_B_MARK,
1646 };
1647
1648 /* - PWM4 ------------------------------------------------------------------- */
1649 static const unsigned int pwm4_a_pins[] = {
1650 /* PWM4 */
1651 RCAR_GP_PIN(2, 16),
1652 };
1653 static const unsigned int pwm4_a_mux[] = {
1654 PWM4_A_MARK,
1655 };
1656 static const unsigned int pwm4_b_pins[] = {
1657 /* PWM4 */
1658 RCAR_GP_PIN(1, 25),
1659 };
1660 static const unsigned int pwm4_b_mux[] = {
1661 PWM4_B_MARK,
1662 };
1663
1664 /* - QSPI0 ------------------------------------------------------------------ */
1665 static const unsigned int qspi0_ctrl_pins[] = {
1666 /* SPCLK, SSL */
1667 RCAR_GP_PIN(5, 0), RCAR_GP_PIN(5, 5),
1668 };
1669 static const unsigned int qspi0_ctrl_mux[] = {
1670 QSPI0_SPCLK_MARK, QSPI0_SSL_MARK,
1671 };
1672 static const unsigned int qspi0_data2_pins[] = {
1673 /* MOSI_IO0, MISO_IO1 */
1674 RCAR_GP_PIN(5, 1), RCAR_GP_PIN(5, 2),
1675 };
1676 static const unsigned int qspi0_data2_mux[] = {
1677 QSPI0_MOSI_IO0_MARK, QSPI0_MISO_IO1_MARK,
1678 };
1679 static const unsigned int qspi0_data4_pins[] = {
1680 /* MOSI_IO0, MISO_IO1, IO2, IO3 */
1681 RCAR_GP_PIN(5, 1), RCAR_GP_PIN(5, 2),
1682 RCAR_GP_PIN(5, 3), RCAR_GP_PIN(5, 4),
1683 };
1684 static const unsigned int qspi0_data4_mux[] = {
1685 QSPI0_MOSI_IO0_MARK, QSPI0_MISO_IO1_MARK,
1686 QSPI0_IO2_MARK, QSPI0_IO3_MARK
1687 };
1688
1689 /* - QSPI1 ------------------------------------------------------------------ */
1690 static const unsigned int qspi1_ctrl_pins[] = {
1691 /* SPCLK, SSL */
1692 RCAR_GP_PIN(5, 6), RCAR_GP_PIN(5, 11),
1693 };
1694 static const unsigned int qspi1_ctrl_mux[] = {
1695 QSPI1_SPCLK_MARK, QSPI1_SSL_MARK,
1696 };
1697 static const unsigned int qspi1_data2_pins[] = {
1698 /* MOSI_IO0, MISO_IO1 */
1699 RCAR_GP_PIN(5, 7), RCAR_GP_PIN(5, 8),
1700 };
1701 static const unsigned int qspi1_data2_mux[] = {
1702 QSPI1_MOSI_IO0_MARK, QSPI1_MISO_IO1_MARK,
1703 };
1704 static const unsigned int qspi1_data4_pins[] = {
1705 /* MOSI_IO0, MISO_IO1, IO2, IO3 */
1706 RCAR_GP_PIN(5, 7), RCAR_GP_PIN(5, 8),
1707 RCAR_GP_PIN(5, 9), RCAR_GP_PIN(5, 10),
1708 };
1709 static const unsigned int qspi1_data4_mux[] = {
1710 QSPI1_MOSI_IO0_MARK, QSPI1_MISO_IO1_MARK,
1711 QSPI1_IO2_MARK, QSPI1_IO3_MARK
1712 };
1713
1714 /* - RPC -------------------------------------------------------------------- */
1715 static const unsigned int rpc_clk1_pins[] = {
1716 /* Octal-SPI flash: C/SCLK */
1717 RCAR_GP_PIN(5, 0),
1718 };
1719 static const unsigned int rpc_clk1_mux[] = {
1720 QSPI0_SPCLK_MARK,
1721 };
1722 static const unsigned int rpc_clk2_pins[] = {
1723 /* HyperFlash: CK, CK# */
1724 RCAR_GP_PIN(5, 0), RCAR_GP_PIN(5, 6),
1725 };
1726 static const unsigned int rpc_clk2_mux[] = {
1727 QSPI0_SPCLK_MARK, QSPI1_SPCLK_MARK,
1728 };
1729 static const unsigned int rpc_ctrl_pins[] = {
1730 /* Octal-SPI flash: S#/CS, DQS */
1731 /* HyperFlash: CS#, RDS */
1732 RCAR_GP_PIN(5, 5), RCAR_GP_PIN(5, 11),
1733 };
1734 static const unsigned int rpc_ctrl_mux[] = {
1735 QSPI0_SSL_MARK, QSPI1_SSL_MARK,
1736 };
1737 static const unsigned int rpc_data_pins[] = {
1738 /* DQ[0:7] */
1739 RCAR_GP_PIN(5, 1), RCAR_GP_PIN(5, 2),
1740 RCAR_GP_PIN(5, 3), RCAR_GP_PIN(5, 4),
1741 RCAR_GP_PIN(5, 7), RCAR_GP_PIN(5, 8),
1742 RCAR_GP_PIN(5, 9), RCAR_GP_PIN(5, 10),
1743 };
1744 static const unsigned int rpc_data_mux[] = {
1745 QSPI0_MOSI_IO0_MARK, QSPI0_MISO_IO1_MARK,
1746 QSPI0_IO2_MARK, QSPI0_IO3_MARK,
1747 QSPI1_MOSI_IO0_MARK, QSPI1_MISO_IO1_MARK,
1748 QSPI1_IO2_MARK, QSPI1_IO3_MARK,
1749 };
1750 static const unsigned int rpc_reset_pins[] = {
1751 /* RPC_RESET# */
1752 RCAR_GP_PIN(5, 12),
1753 };
1754 static const unsigned int rpc_reset_mux[] = {
1755 RPC_RESET_N_MARK,
1756 };
1757 static const unsigned int rpc_int_pins[] = {
1758 /* RPC_INT# */
1759 RCAR_GP_PIN(5, 14),
1760 };
1761 static const unsigned int rpc_int_mux[] = {
1762 RPC_INT_N_MARK,
1763 };
1764 static const unsigned int rpc_wp_pins[] = {
1765 /* RPC_WP# */
1766 RCAR_GP_PIN(5, 13),
1767 };
1768 static const unsigned int rpc_wp_mux[] = {
1769 RPC_WP_N_MARK,
1770 };
1771
1772 /* - SCIF0 ------------------------------------------------------------------ */
1773 static const unsigned int scif0_data_pins[] = {
1774 /* RX0, TX0 */
1775 RCAR_GP_PIN(4, 4), RCAR_GP_PIN(4, 5),
1776 };
1777 static const unsigned int scif0_data_mux[] = {
1778 RX0_MARK, TX0_MARK,
1779 };
1780 static const unsigned int scif0_clk_pins[] = {
1781 /* SCK0 */
1782 RCAR_GP_PIN(4, 1),
1783 };
1784 static const unsigned int scif0_clk_mux[] = {
1785 SCK0_MARK,
1786 };
1787 static const unsigned int scif0_ctrl_pins[] = {
1788 /* RTS0#, CTS0# */
1789 RCAR_GP_PIN(4, 3), RCAR_GP_PIN(4, 2),
1790 };
1791 static const unsigned int scif0_ctrl_mux[] = {
1792 RTS0_N_MARK, CTS0_N_MARK,
1793 };
1794
1795 /* - SCIF1 ------------------------------------------------------------------ */
1796 static const unsigned int scif1_data_a_pins[] = {
1797 /* RX1, TX1 */
1798 RCAR_GP_PIN(2, 8), RCAR_GP_PIN(2, 9),
1799 };
1800 static const unsigned int scif1_data_a_mux[] = {
1801 RX1_A_MARK, TX1_A_MARK,
1802 };
1803 static const unsigned int scif1_clk_pins[] = {
1804 /* SCK1 */
1805 RCAR_GP_PIN(2, 5),
1806 };
1807 static const unsigned int scif1_clk_mux[] = {
1808 SCK1_MARK,
1809 };
1810 static const unsigned int scif1_ctrl_pins[] = {
1811 /* RTS1#, CTS1# */
1812 RCAR_GP_PIN(2, 11), RCAR_GP_PIN(2, 10),
1813 };
1814 static const unsigned int scif1_ctrl_mux[] = {
1815 RTS1_N_MARK, CTS1_N_MARK,
1816 };
1817 static const unsigned int scif1_data_b_pins[] = {
1818 /* RX1, TX1 */
1819 RCAR_GP_PIN(1, 24), RCAR_GP_PIN(1, 23),
1820 };
1821 static const unsigned int scif1_data_b_mux[] = {
1822 RX1_B_MARK, TX1_B_MARK,
1823 };
1824
1825 /* - SCIF3 ------------------------------------------------------------------ */
1826 static const unsigned int scif3_data_pins[] = {
1827 /* RX3, TX3 */
1828 RCAR_GP_PIN(2, 1), RCAR_GP_PIN(2, 2),
1829 };
1830 static const unsigned int scif3_data_mux[] = {
1831 RX3_MARK, TX3_MARK,
1832 };
1833 static const unsigned int scif3_clk_pins[] = {
1834 /* SCK3 */
1835 RCAR_GP_PIN(2, 0),
1836 };
1837 static const unsigned int scif3_clk_mux[] = {
1838 SCK3_MARK,
1839 };
1840 static const unsigned int scif3_ctrl_pins[] = {
1841 /* RTS3#, CTS3# */
1842 RCAR_GP_PIN(2, 4), RCAR_GP_PIN(2, 3),
1843 };
1844 static const unsigned int scif3_ctrl_mux[] = {
1845 RTS3_N_MARK, CTS3_N_MARK,
1846 };
1847
1848 /* - SCIF4 ------------------------------------------------------------------ */
1849 static const unsigned int scif4_data_pins[] = {
1850 /* RX4, TX4 */
1851 RCAR_GP_PIN(0, 1), RCAR_GP_PIN(0, 2),
1852 };
1853 static const unsigned int scif4_data_mux[] = {
1854 RX4_MARK, TX4_MARK,
1855 };
1856 static const unsigned int scif4_clk_pins[] = {
1857 /* SCK4 */
1858 RCAR_GP_PIN(0, 0),
1859 };
1860 static const unsigned int scif4_clk_mux[] = {
1861 SCK4_MARK,
1862 };
1863 static const unsigned int scif4_ctrl_pins[] = {
1864 /* RTS4#, CTS4# */
1865 RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 3),
1866 };
1867 static const unsigned int scif4_ctrl_mux[] = {
1868 RTS4_N_MARK, CTS4_N_MARK,
1869 };
1870
1871 /* - SCIF Clock ------------------------------------------------------------- */
1872 static const unsigned int scif_clk_a_pins[] = {
1873 /* SCIF_CLK */
1874 RCAR_GP_PIN(0, 10),
1875 };
1876 static const unsigned int scif_clk_a_mux[] = {
1877 SCIF_CLK_A_MARK,
1878 };
1879 static const unsigned int scif_clk_b_pins[] = {
1880 /* SCIF_CLK */
1881 RCAR_GP_PIN(1, 25),
1882 };
1883 static const unsigned int scif_clk_b_mux[] = {
1884 SCIF_CLK_B_MARK,
1885 };
1886
1887 /* - TMU -------------------------------------------------------------------- */
1888 static const unsigned int tmu_tclk1_a_pins[] = {
1889 /* TCLK1 */
1890 RCAR_GP_PIN(3, 13),
1891 };
1892 static const unsigned int tmu_tclk1_a_mux[] = {
1893 TCLK1_A_MARK,
1894 };
1895 static const unsigned int tmu_tclk1_b_pins[] = {
1896 /* TCLK1 */
1897 RCAR_GP_PIN(1, 23),
1898 };
1899 static const unsigned int tmu_tclk1_b_mux[] = {
1900 TCLK1_B_MARK,
1901 };
1902 static const unsigned int tmu_tclk2_a_pins[] = {
1903 /* TCLK2 */
1904 RCAR_GP_PIN(3, 14),
1905 };
1906 static const unsigned int tmu_tclk2_a_mux[] = {
1907 TCLK2_A_MARK,
1908 };
1909 static const unsigned int tmu_tclk2_b_pins[] = {
1910 /* TCLK2 */
1911 RCAR_GP_PIN(1, 24),
1912 };
1913 static const unsigned int tmu_tclk2_b_mux[] = {
1914 TCLK2_B_MARK,
1915 };
1916
1917 /* - TPU ------------------------------------------------------------------- */
1918 static const unsigned int tpu_to0_pins[] = {
1919 /* TPU0TO0 */
1920 RCAR_GP_PIN(1, 19),
1921 };
1922 static const unsigned int tpu_to0_mux[] = {
1923 TPU0TO0_MARK,
1924 };
1925 static const unsigned int tpu_to1_pins[] = {
1926 /* TPU0TO1 */
1927 RCAR_GP_PIN(1, 20),
1928 };
1929 static const unsigned int tpu_to1_mux[] = {
1930 TPU0TO1_MARK,
1931 };
1932 static const unsigned int tpu_to2_pins[] = {
1933 /* TPU0TO2 */
1934 RCAR_GP_PIN(4, 2),
1935 };
1936 static const unsigned int tpu_to2_mux[] = {
1937 TPU0TO2_MARK,
1938 };
1939 static const unsigned int tpu_to3_pins[] = {
1940 /* TPU0TO3 */
1941 RCAR_GP_PIN(4, 3),
1942 };
1943 static const unsigned int tpu_to3_mux[] = {
1944 TPU0TO3_MARK,
1945 };
1946
1947 /* - VIN0 ------------------------------------------------------------------- */
1948 static const union vin_data vin0_data_pins = {
1949 .data24 = {
1950 RCAR_GP_PIN(2, 4), RCAR_GP_PIN(2, 5),
1951 RCAR_GP_PIN(2, 6), RCAR_GP_PIN(2, 7),
1952 RCAR_GP_PIN(2, 8), RCAR_GP_PIN(2, 9),
1953 RCAR_GP_PIN(2, 10), RCAR_GP_PIN(2, 11),
1954 RCAR_GP_PIN(2, 12), RCAR_GP_PIN(2, 13),
1955 RCAR_GP_PIN(2, 14), RCAR_GP_PIN(2, 15),
1956 RCAR_GP_PIN(2, 17), RCAR_GP_PIN(2, 18),
1957 RCAR_GP_PIN(2, 19), RCAR_GP_PIN(2, 20),
1958 RCAR_GP_PIN(2, 21), RCAR_GP_PIN(2, 22),
1959 RCAR_GP_PIN(2, 23), RCAR_GP_PIN(2, 24),
1960 RCAR_GP_PIN(2, 25), RCAR_GP_PIN(2, 26),
1961 RCAR_GP_PIN(2, 27), RCAR_GP_PIN(2, 28),
1962 },
1963 };
1964 static const union vin_data vin0_data_mux = {
1965 .data24 = {
1966 VI0_DATA0_MARK, VI0_DATA1_MARK,
1967 VI0_DATA2_MARK, VI0_DATA3_MARK,
1968 VI0_DATA4_MARK, VI0_DATA5_MARK,
1969 VI0_DATA6_MARK, VI0_DATA7_MARK,
1970 VI0_DATA8_MARK, VI0_DATA9_MARK,
1971 VI0_DATA10_MARK, VI0_DATA11_MARK,
1972 VI0_DATA12_MARK, VI0_DATA13_MARK,
1973 VI0_DATA14_MARK, VI0_DATA15_MARK,
1974 VI0_DATA16_MARK, VI0_DATA17_MARK,
1975 VI0_DATA18_MARK, VI0_DATA19_MARK,
1976 VI0_DATA20_MARK, VI0_DATA21_MARK,
1977 VI0_DATA22_MARK, VI0_DATA23_MARK,
1978 },
1979 };
1980 static const unsigned int vin0_data18_pins[] = {
1981 RCAR_GP_PIN(2, 6), RCAR_GP_PIN(2, 7),
1982 RCAR_GP_PIN(2, 8), RCAR_GP_PIN(2, 9),
1983 RCAR_GP_PIN(2, 10), RCAR_GP_PIN(2, 11),
1984 RCAR_GP_PIN(2, 14), RCAR_GP_PIN(2, 15),
1985 RCAR_GP_PIN(2, 17), RCAR_GP_PIN(2, 18),
1986 RCAR_GP_PIN(2, 19), RCAR_GP_PIN(2, 20),
1987 RCAR_GP_PIN(2, 23), RCAR_GP_PIN(2, 24),
1988 RCAR_GP_PIN(2, 25), RCAR_GP_PIN(2, 26),
1989 RCAR_GP_PIN(2, 27), RCAR_GP_PIN(2, 28),
1990 };
1991 static const unsigned int vin0_data18_mux[] = {
1992 VI0_DATA2_MARK, VI0_DATA3_MARK,
1993 VI0_DATA4_MARK, VI0_DATA5_MARK,
1994 VI0_DATA6_MARK, VI0_DATA7_MARK,
1995 VI0_DATA10_MARK, VI0_DATA11_MARK,
1996 VI0_DATA12_MARK, VI0_DATA13_MARK,
1997 VI0_DATA14_MARK, VI0_DATA15_MARK,
1998 VI0_DATA18_MARK, VI0_DATA19_MARK,
1999 VI0_DATA20_MARK, VI0_DATA21_MARK,
2000 VI0_DATA22_MARK, VI0_DATA23_MARK,
2001 };
2002 static const unsigned int vin0_sync_pins[] = {
2003 /* VI0_VSYNC#, VI0_HSYNC# */
2004 RCAR_GP_PIN(2, 3), RCAR_GP_PIN(2, 2),
2005 };
2006 static const unsigned int vin0_sync_mux[] = {
2007 VI0_VSYNC_N_MARK, VI0_HSYNC_N_MARK,
2008 };
2009 static const unsigned int vin0_field_pins[] = {
2010 /* VI0_FIELD */
2011 RCAR_GP_PIN(2, 16),
2012 };
2013 static const unsigned int vin0_field_mux[] = {
2014 VI0_FIELD_MARK,
2015 };
2016 static const unsigned int vin0_clkenb_pins[] = {
2017 /* VI0_CLKENB */
2018 RCAR_GP_PIN(2, 1),
2019 };
2020 static const unsigned int vin0_clkenb_mux[] = {
2021 VI0_CLKENB_MARK,
2022 };
2023 static const unsigned int vin0_clk_pins[] = {
2024 /* VI0_CLK */
2025 RCAR_GP_PIN(2, 0),
2026 };
2027 static const unsigned int vin0_clk_mux[] = {
2028 VI0_CLK_MARK,
2029 };
2030
2031 /* - VIN1 ------------------------------------------------------------------- */
2032 static const union vin_data12 vin1_data_pins = {
2033 .data12 = {
2034 RCAR_GP_PIN(3, 4), RCAR_GP_PIN(3, 5),
2035 RCAR_GP_PIN(3, 6), RCAR_GP_PIN(3, 7),
2036 RCAR_GP_PIN(3, 8), RCAR_GP_PIN(3, 9),
2037 RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11),
2038 RCAR_GP_PIN(3, 12), RCAR_GP_PIN(3, 13),
2039 RCAR_GP_PIN(3, 14), RCAR_GP_PIN(3, 15),
2040 },
2041 };
2042 static const union vin_data12 vin1_data_mux = {
2043 .data12 = {
2044 VI1_DATA0_MARK, VI1_DATA1_MARK,
2045 VI1_DATA2_MARK, VI1_DATA3_MARK,
2046 VI1_DATA4_MARK, VI1_DATA5_MARK,
2047 VI1_DATA6_MARK, VI1_DATA7_MARK,
2048 VI1_DATA8_MARK, VI1_DATA9_MARK,
2049 VI1_DATA10_MARK, VI1_DATA11_MARK,
2050 },
2051 };
2052 static const unsigned int vin1_sync_pins[] = {
2053 /* VI1_VSYNC#, VI1_HSYNC# */
2054 RCAR_GP_PIN(3, 3), RCAR_GP_PIN(3, 2),
2055 };
2056 static const unsigned int vin1_sync_mux[] = {
2057 VI1_VSYNC_N_MARK, VI1_HSYNC_N_MARK,
2058 };
2059 static const unsigned int vin1_field_pins[] = {
2060 /* VI1_FIELD */
2061 RCAR_GP_PIN(3, 16),
2062 };
2063 static const unsigned int vin1_field_mux[] = {
2064 VI1_FIELD_MARK,
2065 };
2066 static const unsigned int vin1_clkenb_pins[] = {
2067 /* VI1_CLKENB */
2068 RCAR_GP_PIN(3, 1),
2069 };
2070 static const unsigned int vin1_clkenb_mux[] = {
2071 VI1_CLKENB_MARK,
2072 };
2073 static const unsigned int vin1_clk_pins[] = {
2074 /* VI1_CLK */
2075 RCAR_GP_PIN(3, 0),
2076 };
2077 static const unsigned int vin1_clk_mux[] = {
2078 VI1_CLK_MARK,
2079 };
2080
2081 static const struct sh_pfc_pin_group pinmux_groups[] = {
2082 SH_PFC_PIN_GROUP(avb_link),
2083 SH_PFC_PIN_GROUP(avb_magic),
2084 SH_PFC_PIN_GROUP(avb_phy_int),
2085 SH_PFC_PIN_GROUP(avb_mdio),
2086 SH_PFC_PIN_GROUP(avb_rgmii),
2087 SH_PFC_PIN_GROUP(avb_txcrefclk),
2088 SH_PFC_PIN_GROUP(avb_avtp_pps),
2089 SH_PFC_PIN_GROUP(avb_avtp_capture),
2090 SH_PFC_PIN_GROUP(avb_avtp_match),
2091 SH_PFC_PIN_GROUP(canfd0_data_a),
2092 SH_PFC_PIN_GROUP(canfd0_data_b),
2093 SH_PFC_PIN_GROUP(canfd1_data),
2094 SH_PFC_PIN_GROUP(canfd_clk_a),
2095 SH_PFC_PIN_GROUP(canfd_clk_b),
2096 SH_PFC_PIN_GROUP(du_rgb666),
2097 SH_PFC_PIN_GROUP(du_rgb888),
2098 SH_PFC_PIN_GROUP(du_clk_out),
2099 SH_PFC_PIN_GROUP(du_sync),
2100 SH_PFC_PIN_GROUP(du_oddf),
2101 SH_PFC_PIN_GROUP(du_cde),
2102 SH_PFC_PIN_GROUP(du_disp),
2103 SH_PFC_PIN_GROUP(gether_link_a),
2104 SH_PFC_PIN_GROUP(gether_phy_int_a),
2105 SH_PFC_PIN_GROUP(gether_mdio_a),
2106 SH_PFC_PIN_GROUP(gether_link_b),
2107 SH_PFC_PIN_GROUP(gether_phy_int_b),
2108 SH_PFC_PIN_GROUP(gether_mdio_b),
2109 SH_PFC_PIN_GROUP(gether_magic),
2110 SH_PFC_PIN_GROUP(gether_rgmii),
2111 SH_PFC_PIN_GROUP(gether_txcrefclk),
2112 SH_PFC_PIN_GROUP(gether_txcrefclk_mega),
2113 SH_PFC_PIN_GROUP(gether_rmii),
2114 SH_PFC_PIN_GROUP(hscif0_data_a),
2115 SH_PFC_PIN_GROUP(hscif0_clk_a),
2116 SH_PFC_PIN_GROUP(hscif0_ctrl_a),
2117 SH_PFC_PIN_GROUP(hscif0_data_b),
2118 SH_PFC_PIN_GROUP(hscif0_clk_b),
2119 SH_PFC_PIN_GROUP(hscif0_ctrl_b),
2120 SH_PFC_PIN_GROUP(hscif1_data),
2121 SH_PFC_PIN_GROUP(hscif1_clk),
2122 SH_PFC_PIN_GROUP(hscif1_ctrl),
2123 SH_PFC_PIN_GROUP(hscif2_data),
2124 SH_PFC_PIN_GROUP(hscif2_clk),
2125 SH_PFC_PIN_GROUP(hscif2_ctrl),
2126 SH_PFC_PIN_GROUP(hscif3_data),
2127 SH_PFC_PIN_GROUP(hscif3_clk),
2128 SH_PFC_PIN_GROUP(hscif3_ctrl),
2129 SH_PFC_PIN_GROUP(i2c0),
2130 SH_PFC_PIN_GROUP(i2c1),
2131 SH_PFC_PIN_GROUP(i2c2),
2132 SH_PFC_PIN_GROUP(i2c3),
2133 SH_PFC_PIN_GROUP(i2c4),
2134 SH_PFC_PIN_GROUP(i2c5),
2135 SH_PFC_PIN_GROUP(intc_ex_irq0),
2136 SH_PFC_PIN_GROUP(intc_ex_irq1),
2137 SH_PFC_PIN_GROUP(intc_ex_irq2),
2138 SH_PFC_PIN_GROUP(intc_ex_irq3),
2139 SH_PFC_PIN_GROUP(intc_ex_irq4),
2140 SH_PFC_PIN_GROUP(intc_ex_irq5),
2141 SH_PFC_PIN_GROUP(mmc_data1),
2142 SH_PFC_PIN_GROUP(mmc_data4),
2143 SH_PFC_PIN_GROUP(mmc_data8),
2144 SH_PFC_PIN_GROUP(mmc_ctrl),
2145 SH_PFC_PIN_GROUP(mmc_cd),
2146 SH_PFC_PIN_GROUP(mmc_wp),
2147 SH_PFC_PIN_GROUP(mmc_ds),
2148 SH_PFC_PIN_GROUP(msiof0_clk),
2149 SH_PFC_PIN_GROUP(msiof0_sync),
2150 SH_PFC_PIN_GROUP(msiof0_ss1),
2151 SH_PFC_PIN_GROUP(msiof0_ss2),
2152 SH_PFC_PIN_GROUP(msiof0_txd),
2153 SH_PFC_PIN_GROUP(msiof0_rxd),
2154 SH_PFC_PIN_GROUP(msiof1_clk),
2155 SH_PFC_PIN_GROUP(msiof1_sync),
2156 SH_PFC_PIN_GROUP(msiof1_ss1),
2157 SH_PFC_PIN_GROUP(msiof1_ss2),
2158 SH_PFC_PIN_GROUP(msiof1_txd),
2159 SH_PFC_PIN_GROUP(msiof1_rxd),
2160 SH_PFC_PIN_GROUP(msiof2_clk),
2161 SH_PFC_PIN_GROUP(msiof2_sync),
2162 SH_PFC_PIN_GROUP(msiof2_ss1),
2163 SH_PFC_PIN_GROUP(msiof2_ss2),
2164 SH_PFC_PIN_GROUP(msiof2_txd),
2165 SH_PFC_PIN_GROUP(msiof2_rxd),
2166 SH_PFC_PIN_GROUP(msiof3_clk),
2167 SH_PFC_PIN_GROUP(msiof3_sync),
2168 SH_PFC_PIN_GROUP(msiof3_ss1),
2169 SH_PFC_PIN_GROUP(msiof3_ss2),
2170 SH_PFC_PIN_GROUP(msiof3_txd),
2171 SH_PFC_PIN_GROUP(msiof3_rxd),
2172 SH_PFC_PIN_GROUP(pwm0_a),
2173 SH_PFC_PIN_GROUP(pwm0_b),
2174 SH_PFC_PIN_GROUP(pwm1_a),
2175 SH_PFC_PIN_GROUP(pwm1_b),
2176 SH_PFC_PIN_GROUP(pwm2_a),
2177 SH_PFC_PIN_GROUP(pwm2_b),
2178 SH_PFC_PIN_GROUP(pwm3_a),
2179 SH_PFC_PIN_GROUP(pwm3_b),
2180 SH_PFC_PIN_GROUP(pwm4_a),
2181 SH_PFC_PIN_GROUP(pwm4_b),
2182 SH_PFC_PIN_GROUP(qspi0_ctrl),
2183 SH_PFC_PIN_GROUP(qspi0_data2),
2184 SH_PFC_PIN_GROUP(qspi0_data4),
2185 SH_PFC_PIN_GROUP(qspi1_ctrl),
2186 SH_PFC_PIN_GROUP(qspi1_data2),
2187 SH_PFC_PIN_GROUP(qspi1_data4),
2188 SH_PFC_PIN_GROUP(rpc_clk1),
2189 SH_PFC_PIN_GROUP(rpc_clk2),
2190 SH_PFC_PIN_GROUP(rpc_ctrl),
2191 SH_PFC_PIN_GROUP(rpc_data),
2192 SH_PFC_PIN_GROUP(rpc_reset),
2193 SH_PFC_PIN_GROUP(rpc_int),
2194 SH_PFC_PIN_GROUP(rpc_wp),
2195 SH_PFC_PIN_GROUP(scif0_data),
2196 SH_PFC_PIN_GROUP(scif0_clk),
2197 SH_PFC_PIN_GROUP(scif0_ctrl),
2198 SH_PFC_PIN_GROUP(scif1_data_a),
2199 SH_PFC_PIN_GROUP(scif1_clk),
2200 SH_PFC_PIN_GROUP(scif1_ctrl),
2201 SH_PFC_PIN_GROUP(scif1_data_b),
2202 SH_PFC_PIN_GROUP(scif3_data),
2203 SH_PFC_PIN_GROUP(scif3_clk),
2204 SH_PFC_PIN_GROUP(scif3_ctrl),
2205 SH_PFC_PIN_GROUP(scif4_data),
2206 SH_PFC_PIN_GROUP(scif4_clk),
2207 SH_PFC_PIN_GROUP(scif4_ctrl),
2208 SH_PFC_PIN_GROUP(scif_clk_a),
2209 SH_PFC_PIN_GROUP(scif_clk_b),
2210 SH_PFC_PIN_GROUP(tmu_tclk1_a),
2211 SH_PFC_PIN_GROUP(tmu_tclk1_b),
2212 SH_PFC_PIN_GROUP(tmu_tclk2_a),
2213 SH_PFC_PIN_GROUP(tmu_tclk2_b),
2214 SH_PFC_PIN_GROUP(tpu_to0),
2215 SH_PFC_PIN_GROUP(tpu_to1),
2216 SH_PFC_PIN_GROUP(tpu_to2),
2217 SH_PFC_PIN_GROUP(tpu_to3),
2218 VIN_DATA_PIN_GROUP(vin0_data, 8),
2219 VIN_DATA_PIN_GROUP(vin0_data, 10),
2220 VIN_DATA_PIN_GROUP(vin0_data, 12),
2221 VIN_DATA_PIN_GROUP(vin0_data, 16),
2222 SH_PFC_PIN_GROUP(vin0_data18),
2223 VIN_DATA_PIN_GROUP(vin0_data, 20),
2224 VIN_DATA_PIN_GROUP(vin0_data, 24),
2225 SH_PFC_PIN_GROUP(vin0_sync),
2226 SH_PFC_PIN_GROUP(vin0_field),
2227 SH_PFC_PIN_GROUP(vin0_clkenb),
2228 SH_PFC_PIN_GROUP(vin0_clk),
2229 VIN_DATA_PIN_GROUP(vin1_data, 8),
2230 VIN_DATA_PIN_GROUP(vin1_data, 10),
2231 VIN_DATA_PIN_GROUP(vin1_data, 12),
2232 SH_PFC_PIN_GROUP(vin1_sync),
2233 SH_PFC_PIN_GROUP(vin1_field),
2234 SH_PFC_PIN_GROUP(vin1_clkenb),
2235 SH_PFC_PIN_GROUP(vin1_clk),
2236 };
2237
2238 static const char * const avb_groups[] = {
2239 "avb_link",
2240 "avb_magic",
2241 "avb_phy_int",
2242 "avb_mdio",
2243 "avb_rgmii",
2244 "avb_txcrefclk",
2245 "avb_avtp_pps",
2246 "avb_avtp_capture",
2247 "avb_avtp_match",
2248 };
2249
2250 static const char * const canfd0_groups[] = {
2251 "canfd0_data_a",
2252 "canfd0_data_b",
2253 };
2254
2255 static const char * const canfd1_groups[] = {
2256 "canfd1_data",
2257 };
2258
2259 static const char * const canfd_clk_groups[] = {
2260 "canfd_clk_a",
2261 "canfd_clk_b",
2262 };
2263
2264 static const char * const du_groups[] = {
2265 "du_rgb666",
2266 "du_rgb888",
2267 "du_clk_out",
2268 "du_sync",
2269 "du_oddf",
2270 "du_cde",
2271 "du_disp",
2272 };
2273
2274 static const char * const gether_groups[] = {
2275 "gether_link_a",
2276 "gether_phy_int_a",
2277 "gether_mdio_a",
2278 "gether_link_b",
2279 "gether_phy_int_b",
2280 "gether_mdio_b",
2281 "gether_magic",
2282 "gether_rgmii",
2283 "gether_txcrefclk",
2284 "gether_txcrefclk_mega",
2285 "gether_rmii",
2286 };
2287
2288 static const char * const hscif0_groups[] = {
2289 "hscif0_data_a",
2290 "hscif0_clk_a",
2291 "hscif0_ctrl_a",
2292 "hscif0_data_b",
2293 "hscif0_clk_b",
2294 "hscif0_ctrl_b",
2295 };
2296
2297 static const char * const hscif1_groups[] = {
2298 "hscif1_data",
2299 "hscif1_clk",
2300 "hscif1_ctrl",
2301 };
2302
2303 static const char * const hscif2_groups[] = {
2304 "hscif2_data",
2305 "hscif2_clk",
2306 "hscif2_ctrl",
2307 };
2308
2309 static const char * const hscif3_groups[] = {
2310 "hscif3_data",
2311 "hscif3_clk",
2312 "hscif3_ctrl",
2313 };
2314
2315 static const char * const i2c0_groups[] = {
2316 "i2c0",
2317 };
2318
2319 static const char * const i2c1_groups[] = {
2320 "i2c1",
2321 };
2322
2323 static const char * const i2c2_groups[] = {
2324 "i2c2",
2325 };
2326
2327 static const char * const i2c3_groups[] = {
2328 "i2c3",
2329 };
2330
2331 static const char * const i2c4_groups[] = {
2332 "i2c4",
2333 };
2334
2335 static const char * const i2c5_groups[] = {
2336 "i2c5",
2337 };
2338
2339 static const char * const intc_ex_groups[] = {
2340 "intc_ex_irq0",
2341 "intc_ex_irq1",
2342 "intc_ex_irq2",
2343 "intc_ex_irq3",
2344 "intc_ex_irq4",
2345 "intc_ex_irq5",
2346 };
2347
2348 static const char * const mmc_groups[] = {
2349 "mmc_data1",
2350 "mmc_data4",
2351 "mmc_data8",
2352 "mmc_ctrl",
2353 "mmc_cd",
2354 "mmc_wp",
2355 "mmc_ds",
2356 };
2357
2358 static const char * const msiof0_groups[] = {
2359 "msiof0_clk",
2360 "msiof0_sync",
2361 "msiof0_ss1",
2362 "msiof0_ss2",
2363 "msiof0_txd",
2364 "msiof0_rxd",
2365 };
2366
2367 static const char * const msiof1_groups[] = {
2368 "msiof1_clk",
2369 "msiof1_sync",
2370 "msiof1_ss1",
2371 "msiof1_ss2",
2372 "msiof1_txd",
2373 "msiof1_rxd",
2374 };
2375
2376 static const char * const msiof2_groups[] = {
2377 "msiof2_clk",
2378 "msiof2_sync",
2379 "msiof2_ss1",
2380 "msiof2_ss2",
2381 "msiof2_txd",
2382 "msiof2_rxd",
2383 };
2384
2385 static const char * const msiof3_groups[] = {
2386 "msiof3_clk",
2387 "msiof3_sync",
2388 "msiof3_ss1",
2389 "msiof3_ss2",
2390 "msiof3_txd",
2391 "msiof3_rxd",
2392 };
2393
2394 static const char * const pwm0_groups[] = {
2395 "pwm0_a",
2396 "pwm0_b",
2397 };
2398
2399 static const char * const pwm1_groups[] = {
2400 "pwm1_a",
2401 "pwm1_b",
2402 };
2403
2404 static const char * const pwm2_groups[] = {
2405 "pwm2_a",
2406 "pwm2_b",
2407 };
2408
2409 static const char * const pwm3_groups[] = {
2410 "pwm3_a",
2411 "pwm3_b",
2412 };
2413
2414 static const char * const pwm4_groups[] = {
2415 "pwm4_a",
2416 "pwm4_b",
2417 };
2418
2419 static const char * const qspi0_groups[] = {
2420 "qspi0_ctrl",
2421 "qspi0_data2",
2422 "qspi0_data4",
2423 };
2424
2425 static const char * const qspi1_groups[] = {
2426 "qspi1_ctrl",
2427 "qspi1_data2",
2428 "qspi1_data4",
2429 };
2430
2431 static const char * const rpc_groups[] = {
2432 "rpc_clk1",
2433 "rpc_clk2",
2434 "rpc_ctrl",
2435 "rpc_data",
2436 "rpc_reset",
2437 "rpc_int",
2438 "rpc_wp",
2439 };
2440
2441 static const char * const scif0_groups[] = {
2442 "scif0_data",
2443 "scif0_clk",
2444 "scif0_ctrl",
2445 };
2446
2447 static const char * const scif1_groups[] = {
2448 "scif1_data_a",
2449 "scif1_clk",
2450 "scif1_ctrl",
2451 "scif1_data_b",
2452 };
2453
2454 static const char * const scif3_groups[] = {
2455 "scif3_data",
2456 "scif3_clk",
2457 "scif3_ctrl",
2458 };
2459
2460 static const char * const scif4_groups[] = {
2461 "scif4_data",
2462 "scif4_clk",
2463 "scif4_ctrl",
2464 };
2465
2466 static const char * const scif_clk_groups[] = {
2467 "scif_clk_a",
2468 "scif_clk_b",
2469 };
2470
2471 static const char * const tmu_groups[] = {
2472 "tmu_tclk1_a",
2473 "tmu_tclk1_b",
2474 "tmu_tclk2_a",
2475 "tmu_tclk2_b",
2476 };
2477
2478 static const char * const tpu_groups[] = {
2479 "tpu_to0",
2480 "tpu_to1",
2481 "tpu_to2",
2482 "tpu_to3",
2483 };
2484
2485 static const char * const vin0_groups[] = {
2486 "vin0_data8",
2487 "vin0_data10",
2488 "vin0_data12",
2489 "vin0_data16",
2490 "vin0_data18",
2491 "vin0_data20",
2492 "vin0_data24",
2493 "vin0_sync",
2494 "vin0_field",
2495 "vin0_clkenb",
2496 "vin0_clk",
2497 };
2498
2499 static const char * const vin1_groups[] = {
2500 "vin1_data8",
2501 "vin1_data10",
2502 "vin1_data12",
2503 "vin1_sync",
2504 "vin1_field",
2505 "vin1_clkenb",
2506 "vin1_clk",
2507 };
2508
2509 static const struct sh_pfc_function pinmux_functions[] = {
2510 SH_PFC_FUNCTION(avb),
2511 SH_PFC_FUNCTION(canfd0),
2512 SH_PFC_FUNCTION(canfd1),
2513 SH_PFC_FUNCTION(canfd_clk),
2514 SH_PFC_FUNCTION(du),
2515 SH_PFC_FUNCTION(gether),
2516 SH_PFC_FUNCTION(hscif0),
2517 SH_PFC_FUNCTION(hscif1),
2518 SH_PFC_FUNCTION(hscif2),
2519 SH_PFC_FUNCTION(hscif3),
2520 SH_PFC_FUNCTION(i2c0),
2521 SH_PFC_FUNCTION(i2c1),
2522 SH_PFC_FUNCTION(i2c2),
2523 SH_PFC_FUNCTION(i2c3),
2524 SH_PFC_FUNCTION(i2c4),
2525 SH_PFC_FUNCTION(i2c5),
2526 SH_PFC_FUNCTION(intc_ex),
2527 SH_PFC_FUNCTION(mmc),
2528 SH_PFC_FUNCTION(msiof0),
2529 SH_PFC_FUNCTION(msiof1),
2530 SH_PFC_FUNCTION(msiof2),
2531 SH_PFC_FUNCTION(msiof3),
2532 SH_PFC_FUNCTION(pwm0),
2533 SH_PFC_FUNCTION(pwm1),
2534 SH_PFC_FUNCTION(pwm2),
2535 SH_PFC_FUNCTION(pwm3),
2536 SH_PFC_FUNCTION(pwm4),
2537 SH_PFC_FUNCTION(qspi0),
2538 SH_PFC_FUNCTION(qspi1),
2539 SH_PFC_FUNCTION(rpc),
2540 SH_PFC_FUNCTION(scif0),
2541 SH_PFC_FUNCTION(scif1),
2542 SH_PFC_FUNCTION(scif3),
2543 SH_PFC_FUNCTION(scif4),
2544 SH_PFC_FUNCTION(scif_clk),
2545 SH_PFC_FUNCTION(tmu),
2546 SH_PFC_FUNCTION(tpu),
2547 SH_PFC_FUNCTION(vin0),
2548 SH_PFC_FUNCTION(vin1),
2549 };
2550
2551 static const struct pinmux_cfg_reg pinmux_config_regs[] = {
2552 #define F_(x, y) FN_##y
2553 #define FM(x) FN_##x
2554 { PINMUX_CFG_REG("GPSR0", 0xe6060100, 32, 1, GROUP(
2555 0, 0,
2556 0, 0,
2557 0, 0,
2558 0, 0,
2559 0, 0,
2560 0, 0,
2561 0, 0,
2562 0, 0,
2563 0, 0,
2564 0, 0,
2565 GP_0_21_FN, GPSR0_21,
2566 GP_0_20_FN, GPSR0_20,
2567 GP_0_19_FN, GPSR0_19,
2568 GP_0_18_FN, GPSR0_18,
2569 GP_0_17_FN, GPSR0_17,
2570 GP_0_16_FN, GPSR0_16,
2571 GP_0_15_FN, GPSR0_15,
2572 GP_0_14_FN, GPSR0_14,
2573 GP_0_13_FN, GPSR0_13,
2574 GP_0_12_FN, GPSR0_12,
2575 GP_0_11_FN, GPSR0_11,
2576 GP_0_10_FN, GPSR0_10,
2577 GP_0_9_FN, GPSR0_9,
2578 GP_0_8_FN, GPSR0_8,
2579 GP_0_7_FN, GPSR0_7,
2580 GP_0_6_FN, GPSR0_6,
2581 GP_0_5_FN, GPSR0_5,
2582 GP_0_4_FN, GPSR0_4,
2583 GP_0_3_FN, GPSR0_3,
2584 GP_0_2_FN, GPSR0_2,
2585 GP_0_1_FN, GPSR0_1,
2586 GP_0_0_FN, GPSR0_0, ))
2587 },
2588 { PINMUX_CFG_REG("GPSR1", 0xe6060104, 32, 1, GROUP(
2589 0, 0,
2590 0, 0,
2591 0, 0,
2592 0, 0,
2593 GP_1_27_FN, GPSR1_27,
2594 GP_1_26_FN, GPSR1_26,
2595 GP_1_25_FN, GPSR1_25,
2596 GP_1_24_FN, GPSR1_24,
2597 GP_1_23_FN, GPSR1_23,
2598 GP_1_22_FN, GPSR1_22,
2599 GP_1_21_FN, GPSR1_21,
2600 GP_1_20_FN, GPSR1_20,
2601 GP_1_19_FN, GPSR1_19,
2602 GP_1_18_FN, GPSR1_18,
2603 GP_1_17_FN, GPSR1_17,
2604 GP_1_16_FN, GPSR1_16,
2605 GP_1_15_FN, GPSR1_15,
2606 GP_1_14_FN, GPSR1_14,
2607 GP_1_13_FN, GPSR1_13,
2608 GP_1_12_FN, GPSR1_12,
2609 GP_1_11_FN, GPSR1_11,
2610 GP_1_10_FN, GPSR1_10,
2611 GP_1_9_FN, GPSR1_9,
2612 GP_1_8_FN, GPSR1_8,
2613 GP_1_7_FN, GPSR1_7,
2614 GP_1_6_FN, GPSR1_6,
2615 GP_1_5_FN, GPSR1_5,
2616 GP_1_4_FN, GPSR1_4,
2617 GP_1_3_FN, GPSR1_3,
2618 GP_1_2_FN, GPSR1_2,
2619 GP_1_1_FN, GPSR1_1,
2620 GP_1_0_FN, GPSR1_0, ))
2621 },
2622 { PINMUX_CFG_REG("GPSR2", 0xe6060108, 32, 1, GROUP(
2623 0, 0,
2624 0, 0,
2625 GP_2_29_FN, GPSR2_29,
2626 GP_2_28_FN, GPSR2_28,
2627 GP_2_27_FN, GPSR2_27,
2628 GP_2_26_FN, GPSR2_26,
2629 GP_2_25_FN, GPSR2_25,
2630 GP_2_24_FN, GPSR2_24,
2631 GP_2_23_FN, GPSR2_23,
2632 GP_2_22_FN, GPSR2_22,
2633 GP_2_21_FN, GPSR2_21,
2634 GP_2_20_FN, GPSR2_20,
2635 GP_2_19_FN, GPSR2_19,
2636 GP_2_18_FN, GPSR2_18,
2637 GP_2_17_FN, GPSR2_17,
2638 GP_2_16_FN, GPSR2_16,
2639 GP_2_15_FN, GPSR2_15,
2640 GP_2_14_FN, GPSR2_14,
2641 GP_2_13_FN, GPSR2_13,
2642 GP_2_12_FN, GPSR2_12,
2643 GP_2_11_FN, GPSR2_11,
2644 GP_2_10_FN, GPSR2_10,
2645 GP_2_9_FN, GPSR2_9,
2646 GP_2_8_FN, GPSR2_8,
2647 GP_2_7_FN, GPSR2_7,
2648 GP_2_6_FN, GPSR2_6,
2649 GP_2_5_FN, GPSR2_5,
2650 GP_2_4_FN, GPSR2_4,
2651 GP_2_3_FN, GPSR2_3,
2652 GP_2_2_FN, GPSR2_2,
2653 GP_2_1_FN, GPSR2_1,
2654 GP_2_0_FN, GPSR2_0, ))
2655 },
2656 { PINMUX_CFG_REG("GPSR3", 0xe606010c, 32, 1, GROUP(
2657 0, 0,
2658 0, 0,
2659 0, 0,
2660 0, 0,
2661 0, 0,
2662 0, 0,
2663 0, 0,
2664 0, 0,
2665 0, 0,
2666 0, 0,
2667 0, 0,
2668 0, 0,
2669 0, 0,
2670 0, 0,
2671 0, 0,
2672 GP_3_16_FN, GPSR3_16,
2673 GP_3_15_FN, GPSR3_15,
2674 GP_3_14_FN, GPSR3_14,
2675 GP_3_13_FN, GPSR3_13,
2676 GP_3_12_FN, GPSR3_12,
2677 GP_3_11_FN, GPSR3_11,
2678 GP_3_10_FN, GPSR3_10,
2679 GP_3_9_FN, GPSR3_9,
2680 GP_3_8_FN, GPSR3_8,
2681 GP_3_7_FN, GPSR3_7,
2682 GP_3_6_FN, GPSR3_6,
2683 GP_3_5_FN, GPSR3_5,
2684 GP_3_4_FN, GPSR3_4,
2685 GP_3_3_FN, GPSR3_3,
2686 GP_3_2_FN, GPSR3_2,
2687 GP_3_1_FN, GPSR3_1,
2688 GP_3_0_FN, GPSR3_0, ))
2689 },
2690 { PINMUX_CFG_REG("GPSR4", 0xe6060110, 32, 1, GROUP(
2691 0, 0,
2692 0, 0,
2693 0, 0,
2694 0, 0,
2695 0, 0,
2696 0, 0,
2697 0, 0,
2698 GP_4_24_FN, GPSR4_24,
2699 GP_4_23_FN, GPSR4_23,
2700 GP_4_22_FN, GPSR4_22,
2701 GP_4_21_FN, GPSR4_21,
2702 GP_4_20_FN, GPSR4_20,
2703 GP_4_19_FN, GPSR4_19,
2704 GP_4_18_FN, GPSR4_18,
2705 GP_4_17_FN, GPSR4_17,
2706 GP_4_16_FN, GPSR4_16,
2707 GP_4_15_FN, GPSR4_15,
2708 GP_4_14_FN, GPSR4_14,
2709 GP_4_13_FN, GPSR4_13,
2710 GP_4_12_FN, GPSR4_12,
2711 GP_4_11_FN, GPSR4_11,
2712 GP_4_10_FN, GPSR4_10,
2713 GP_4_9_FN, GPSR4_9,
2714 GP_4_8_FN, GPSR4_8,
2715 GP_4_7_FN, GPSR4_7,
2716 GP_4_6_FN, GPSR4_6,
2717 GP_4_5_FN, GPSR4_5,
2718 GP_4_4_FN, GPSR4_4,
2719 GP_4_3_FN, GPSR4_3,
2720 GP_4_2_FN, GPSR4_2,
2721 GP_4_1_FN, GPSR4_1,
2722 GP_4_0_FN, GPSR4_0, ))
2723 },
2724 { PINMUX_CFG_REG("GPSR5", 0xe6060114, 32, 1, GROUP(
2725 0, 0,
2726 0, 0,
2727 0, 0,
2728 0, 0,
2729 0, 0,
2730 0, 0,
2731 0, 0,
2732 0, 0,
2733 0, 0,
2734 0, 0,
2735 0, 0,
2736 0, 0,
2737 0, 0,
2738 0, 0,
2739 0, 0,
2740 0, 0,
2741 0, 0,
2742 GP_5_14_FN, GPSR5_14,
2743 GP_5_13_FN, GPSR5_13,
2744 GP_5_12_FN, GPSR5_12,
2745 GP_5_11_FN, GPSR5_11,
2746 GP_5_10_FN, GPSR5_10,
2747 GP_5_9_FN, GPSR5_9,
2748 GP_5_8_FN, GPSR5_8,
2749 GP_5_7_FN, GPSR5_7,
2750 GP_5_6_FN, GPSR5_6,
2751 GP_5_5_FN, GPSR5_5,
2752 GP_5_4_FN, GPSR5_4,
2753 GP_5_3_FN, GPSR5_3,
2754 GP_5_2_FN, GPSR5_2,
2755 GP_5_1_FN, GPSR5_1,
2756 GP_5_0_FN, GPSR5_0, ))
2757 },
2758 #undef F_
2759 #undef FM
2760
2761 #define F_(x, y) x,
2762 #define FM(x) FN_##x,
2763 { PINMUX_CFG_REG("IPSR0", 0xe6060200, 32, 4, GROUP(
2764 IP0_31_28
2765 IP0_27_24
2766 IP0_23_20
2767 IP0_19_16
2768 IP0_15_12
2769 IP0_11_8
2770 IP0_7_4
2771 IP0_3_0 ))
2772 },
2773 { PINMUX_CFG_REG("IPSR1", 0xe6060204, 32, 4, GROUP(
2774 IP1_31_28
2775 IP1_27_24
2776 IP1_23_20
2777 IP1_19_16
2778 IP1_15_12
2779 IP1_11_8
2780 IP1_7_4
2781 IP1_3_0 ))
2782 },
2783 { PINMUX_CFG_REG("IPSR2", 0xe6060208, 32, 4, GROUP(
2784 IP2_31_28
2785 IP2_27_24
2786 IP2_23_20
2787 IP2_19_16
2788 IP2_15_12
2789 IP2_11_8
2790 IP2_7_4
2791 IP2_3_0 ))
2792 },
2793 { PINMUX_CFG_REG("IPSR3", 0xe606020c, 32, 4, GROUP(
2794 IP3_31_28
2795 IP3_27_24
2796 IP3_23_20
2797 IP3_19_16
2798 IP3_15_12
2799 IP3_11_8
2800 IP3_7_4
2801 IP3_3_0 ))
2802 },
2803 { PINMUX_CFG_REG("IPSR4", 0xe6060210, 32, 4, GROUP(
2804 IP4_31_28
2805 IP4_27_24
2806 IP4_23_20
2807 IP4_19_16
2808 IP4_15_12
2809 IP4_11_8
2810 IP4_7_4
2811 IP4_3_0 ))
2812 },
2813 { PINMUX_CFG_REG("IPSR5", 0xe6060214, 32, 4, GROUP(
2814 IP5_31_28
2815 IP5_27_24
2816 IP5_23_20
2817 IP5_19_16
2818 IP5_15_12
2819 IP5_11_8
2820 IP5_7_4
2821 IP5_3_0 ))
2822 },
2823 { PINMUX_CFG_REG("IPSR6", 0xe6060218, 32, 4, GROUP(
2824 IP6_31_28
2825 IP6_27_24
2826 IP6_23_20
2827 IP6_19_16
2828 IP6_15_12
2829 IP6_11_8
2830 IP6_7_4
2831 IP6_3_0 ))
2832 },
2833 { PINMUX_CFG_REG("IPSR7", 0xe606021c, 32, 4, GROUP(
2834 IP7_31_28
2835 IP7_27_24
2836 IP7_23_20
2837 IP7_19_16
2838 IP7_15_12
2839 IP7_11_8
2840 IP7_7_4
2841 IP7_3_0 ))
2842 },
2843 { PINMUX_CFG_REG("IPSR8", 0xe6060220, 32, 4, GROUP(
2844 IP8_31_28
2845 IP8_27_24
2846 IP8_23_20
2847 IP8_19_16
2848 IP8_15_12
2849 IP8_11_8
2850 IP8_7_4
2851 IP8_3_0 ))
2852 },
2853 { PINMUX_CFG_REG("IPSR9", 0xe6060224, 32, 4, GROUP(
2854 IP9_31_28
2855 IP9_27_24
2856 IP9_23_20
2857 IP9_19_16
2858 IP9_15_12
2859 IP9_11_8
2860 IP9_7_4
2861 IP9_3_0 ))
2862 },
2863 { PINMUX_CFG_REG("IPSR10", 0xe6060228, 32, 4, GROUP(
2864 IP10_31_28
2865 IP10_27_24
2866 IP10_23_20
2867 IP10_19_16
2868 IP10_15_12
2869 IP10_11_8
2870 IP10_7_4
2871 IP10_3_0 ))
2872 },
2873 #undef F_
2874 #undef FM
2875
2876 #define F_(x, y) x,
2877 #define FM(x) FN_##x,
2878 { PINMUX_CFG_REG_VAR("MOD_SEL0", 0xe6060500, 32,
2879 GROUP(4, 4, 4, 4, 4, 1, 1, 1, 1, 1, 1, 1,
2880 1, 1, 1, 1, 1),
2881 GROUP(
2882 /* RESERVED 31, 30, 29, 28 */
2883 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2884 /* RESERVED 27, 26, 25, 24 */
2885 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2886 /* RESERVED 23, 22, 21, 20 */
2887 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2888 /* RESERVED 19, 18, 17, 16 */
2889 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2890 /* RESERVED 15, 14, 13, 12 */
2891 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2892 MOD_SEL0_11
2893 MOD_SEL0_10
2894 MOD_SEL0_9
2895 MOD_SEL0_8
2896 MOD_SEL0_7
2897 MOD_SEL0_6
2898 MOD_SEL0_5
2899 MOD_SEL0_4
2900 0, 0,
2901 MOD_SEL0_2
2902 MOD_SEL0_1
2903 MOD_SEL0_0 ))
2904 },
2905 { },
2906 };
2907
2908 enum ioctrl_regs {
2909 POCCTRL0,
2910 POCCTRL1,
2911 POCCTRL2,
2912 POCCTRL3,
2913 TDSELCTRL,
2914 };
2915
2916 static const struct pinmux_ioctrl_reg pinmux_ioctrl_regs[] = {
2917 [POCCTRL0] = { 0xe6060380, },
2918 [POCCTRL1] = { 0xe6060384, },
2919 [POCCTRL2] = { 0xe6060388, },
2920 [POCCTRL3] = { 0xe606038c, },
2921 [TDSELCTRL] = { 0xe60603c0, },
2922 { /* sentinel */ },
2923 };
2924
r8a77980_pin_to_pocctrl(struct sh_pfc * pfc,unsigned int pin,u32 * pocctrl)2925 static int r8a77980_pin_to_pocctrl(struct sh_pfc *pfc, unsigned int pin,
2926 u32 *pocctrl)
2927 {
2928 int bit = pin & 0x1f;
2929
2930 *pocctrl = pinmux_ioctrl_regs[POCCTRL0].reg;
2931 if (pin >= RCAR_GP_PIN(0, 0) && pin <= RCAR_GP_PIN(0, 21))
2932 return bit;
2933 else if (pin >= RCAR_GP_PIN(2, 0) && pin <= RCAR_GP_PIN(2, 9))
2934 return bit + 22;
2935
2936 *pocctrl = pinmux_ioctrl_regs[POCCTRL1].reg;
2937 if (pin >= RCAR_GP_PIN(2, 10) && pin <= RCAR_GP_PIN(2, 16))
2938 return bit - 10;
2939 if ((pin >= RCAR_GP_PIN(2, 17) && pin <= RCAR_GP_PIN(2, 24)) ||
2940 (pin >= RCAR_GP_PIN(3, 0) && pin <= RCAR_GP_PIN(3, 16)))
2941 return bit + 7;
2942
2943 *pocctrl = pinmux_ioctrl_regs[POCCTRL2].reg;
2944 if (pin >= RCAR_GP_PIN(2, 25) && pin <= RCAR_GP_PIN(2, 29))
2945 return pin - 25;
2946
2947 return -EINVAL;
2948 }
2949
2950 static const struct sh_pfc_soc_operations pinmux_ops = {
2951 .pin_to_pocctrl = r8a77980_pin_to_pocctrl,
2952 };
2953
2954 const struct sh_pfc_soc_info r8a77980_pinmux_info = {
2955 .name = "r8a77980_pfc",
2956 .ops = &pinmux_ops,
2957 .unlock_reg = 0xe6060000, /* PMMR */
2958
2959 .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
2960
2961 .pins = pinmux_pins,
2962 .nr_pins = ARRAY_SIZE(pinmux_pins),
2963 .groups = pinmux_groups,
2964 .nr_groups = ARRAY_SIZE(pinmux_groups),
2965 .functions = pinmux_functions,
2966 .nr_functions = ARRAY_SIZE(pinmux_functions),
2967
2968 .cfg_regs = pinmux_config_regs,
2969 .ioctrl_regs = pinmux_ioctrl_regs,
2970
2971 .pinmux_data = pinmux_data,
2972 .pinmux_data_size = ARRAY_SIZE(pinmux_data),
2973 };
2974