1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Freescale i.MX28 USB Host driver
4 *
5 * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com>
6 * on behalf of DENX Software Engineering GmbH
7 */
8
9 #include <common.h>
10 #include <asm/io.h>
11 #include <asm/arch/imx-regs.h>
12 #include <errno.h>
13 #include <linux/delay.h>
14
15 #include "ehci.h"
16
17 /* This DIGCTL register ungates clock to USB */
18 #define HW_DIGCTL_CTRL 0x8001c000
19 #define HW_DIGCTL_CTRL_USB0_CLKGATE (1 << 2)
20 #define HW_DIGCTL_CTRL_USB1_CLKGATE (1 << 16)
21
22 struct ehci_mxs_port {
23 uint32_t usb_regs;
24 struct mxs_usbphy_regs *phy_regs;
25
26 struct mxs_register_32 *pll;
27 uint32_t pll_en_bits;
28 uint32_t pll_dis_bits;
29 uint32_t gate_bits;
30 };
31
32 static const struct ehci_mxs_port mxs_port[] = {
33 #ifdef CONFIG_EHCI_MXS_PORT0
34 {
35 MXS_USBCTRL0_BASE,
36 (struct mxs_usbphy_regs *)MXS_USBPHY0_BASE,
37 (struct mxs_register_32 *)(MXS_CLKCTRL_BASE +
38 offsetof(struct mxs_clkctrl_regs,
39 hw_clkctrl_pll0ctrl0_reg)),
40 CLKCTRL_PLL0CTRL0_EN_USB_CLKS | CLKCTRL_PLL0CTRL0_POWER,
41 CLKCTRL_PLL0CTRL0_EN_USB_CLKS,
42 HW_DIGCTL_CTRL_USB0_CLKGATE,
43 },
44 #endif
45 #ifdef CONFIG_EHCI_MXS_PORT1
46 {
47 MXS_USBCTRL1_BASE,
48 (struct mxs_usbphy_regs *)MXS_USBPHY1_BASE,
49 (struct mxs_register_32 *)(MXS_CLKCTRL_BASE +
50 offsetof(struct mxs_clkctrl_regs,
51 hw_clkctrl_pll1ctrl0_reg)),
52 CLKCTRL_PLL1CTRL0_EN_USB_CLKS | CLKCTRL_PLL1CTRL0_POWER,
53 CLKCTRL_PLL1CTRL0_EN_USB_CLKS,
54 HW_DIGCTL_CTRL_USB1_CLKGATE,
55 },
56 #endif
57 };
58
ehci_mxs_toggle_clock(const struct ehci_mxs_port * port,int enable)59 static int ehci_mxs_toggle_clock(const struct ehci_mxs_port *port, int enable)
60 {
61 struct mxs_register_32 *digctl_ctrl =
62 (struct mxs_register_32 *)HW_DIGCTL_CTRL;
63 int pll_offset, dig_offset;
64
65 if (enable) {
66 pll_offset = offsetof(struct mxs_register_32, reg_set);
67 dig_offset = offsetof(struct mxs_register_32, reg_clr);
68 writel(port->gate_bits, (u32)&digctl_ctrl->reg + dig_offset);
69 writel(port->pll_en_bits, (u32)port->pll + pll_offset);
70 } else {
71 pll_offset = offsetof(struct mxs_register_32, reg_clr);
72 dig_offset = offsetof(struct mxs_register_32, reg_set);
73 writel(port->pll_dis_bits, (u32)port->pll + pll_offset);
74 writel(port->gate_bits, (u32)&digctl_ctrl->reg + dig_offset);
75 }
76
77 return 0;
78 }
79
board_ehci_hcd_init(int port)80 int __weak board_ehci_hcd_init(int port)
81 {
82 return 0;
83 }
84
board_ehci_hcd_exit(int port)85 int __weak board_ehci_hcd_exit(int port)
86 {
87 return 0;
88 }
89
ehci_hcd_init(int index,enum usb_init_type init,struct ehci_hccr ** hccr,struct ehci_hcor ** hcor)90 int ehci_hcd_init(int index, enum usb_init_type init,
91 struct ehci_hccr **hccr, struct ehci_hcor **hcor)
92 {
93
94 int ret;
95 uint32_t usb_base, cap_base;
96 const struct ehci_mxs_port *port;
97
98 if ((index < 0) || (index >= ARRAY_SIZE(mxs_port))) {
99 printf("Invalid port index (index = %d)!\n", index);
100 return -EINVAL;
101 }
102
103 ret = board_ehci_hcd_init(index);
104 if (ret)
105 return ret;
106
107 port = &mxs_port[index];
108
109 /* Reset the PHY block */
110 writel(USBPHY_CTRL_SFTRST, &port->phy_regs->hw_usbphy_ctrl_set);
111 udelay(10);
112 writel(USBPHY_CTRL_SFTRST | USBPHY_CTRL_CLKGATE,
113 &port->phy_regs->hw_usbphy_ctrl_clr);
114
115 /* Enable USB clock */
116 ret = ehci_mxs_toggle_clock(port, 1);
117 if (ret)
118 return ret;
119
120 /* Start USB PHY */
121 writel(0, &port->phy_regs->hw_usbphy_pwd);
122
123 /* Enable UTMI+ Level 2 and Level 3 compatibility */
124 writel(USBPHY_CTRL_ENUTMILEVEL3 | USBPHY_CTRL_ENUTMILEVEL2 | 1,
125 &port->phy_regs->hw_usbphy_ctrl_set);
126
127 usb_base = port->usb_regs + 0x100;
128 *hccr = (struct ehci_hccr *)usb_base;
129
130 cap_base = ehci_readl(&(*hccr)->cr_capbase);
131 *hcor = (struct ehci_hcor *)(usb_base + HC_LENGTH(cap_base));
132
133 return 0;
134 }
135
ehci_hcd_stop(int index)136 int ehci_hcd_stop(int index)
137 {
138 int ret;
139 uint32_t usb_base, cap_base, tmp;
140 struct ehci_hccr *hccr;
141 struct ehci_hcor *hcor;
142 const struct ehci_mxs_port *port;
143
144 if ((index < 0) || (index >= ARRAY_SIZE(mxs_port))) {
145 printf("Invalid port index (index = %d)!\n", index);
146 return -EINVAL;
147 }
148
149 port = &mxs_port[index];
150
151 /* Stop the USB port */
152 usb_base = port->usb_regs + 0x100;
153 hccr = (struct ehci_hccr *)usb_base;
154 cap_base = ehci_readl(&hccr->cr_capbase);
155 hcor = (struct ehci_hcor *)(usb_base + HC_LENGTH(cap_base));
156
157 tmp = ehci_readl(&hcor->or_usbcmd);
158 tmp &= ~CMD_RUN;
159 ehci_writel(&hcor->or_usbcmd, tmp);
160
161 /* Disable the PHY */
162 tmp = USBPHY_PWD_RXPWDRX | USBPHY_PWD_RXPWDDIFF |
163 USBPHY_PWD_RXPWD1PT1 | USBPHY_PWD_RXPWDENV |
164 USBPHY_PWD_TXPWDV2I | USBPHY_PWD_TXPWDIBIAS |
165 USBPHY_PWD_TXPWDFS;
166 writel(tmp, &port->phy_regs->hw_usbphy_pwd);
167
168 /* Disable USB clock */
169 ret = ehci_mxs_toggle_clock(port, 0);
170
171 board_ehci_hcd_exit(index);
172
173 return ret;
174 }
175