1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * URB OHCI HCD (Host Controller Driver) for USB on the AT91RM9200 and PCI bus.
4 *
5 * Interrupt support is added. Now, it has been tested
6 * on ULI1575 chip and works well with USB keyboard.
7 *
8 * (C) Copyright 2007
9 * Zhang Wei, Freescale Semiconductor, Inc. <wei.zhang@freescale.com>
10 *
11 * (C) Copyright 2003
12 * Gary Jennejohn, DENX Software Engineering <garyj@denx.de>
13 *
14 * Note: Much of this code has been derived from Linux 2.4
15 * (C) Copyright 1999 Roman Weissgaerber <weissg@vienna.at>
16 * (C) Copyright 2000-2002 David Brownell
17 *
18 * Modified for the MP2USB by (C) Copyright 2005 Eric Benard
19 * ebenard@eukrea.com - based on s3c24x0's driver
20 */
21 /*
22 * IMPORTANT NOTES
23 * 1 - Read doc/README.generic_usb_ohci
24 * 2 - this driver is intended for use with USB Mass Storage Devices
25 * (BBB) and USB keyboard. There is NO support for Isochronous pipes!
26 * 2 - when running on a PQFP208 AT91RM9200, define CONFIG_AT91C_PQFP_UHPBUG
27 * to activate workaround for bug #41 or this driver will NOT work!
28 */
29
30 #include <common.h>
31 #include <cpu_func.h>
32 #include <asm/byteorder.h>
33 #include <dm.h>
34 #include <errno.h>
35 #include <asm/cache.h>
36 #include <linux/delay.h>
37
38 #if defined(CONFIG_PCI_OHCI)
39 # include <pci.h>
40 #if !defined(CONFIG_PCI_OHCI_DEVNO)
41 #define CONFIG_PCI_OHCI_DEVNO 0
42 #endif
43 #endif
44
45 #include <malloc.h>
46 #include <memalign.h>
47 #include <usb.h>
48
49 #include "ohci.h"
50
51 #ifdef CONFIG_AT91RM9200
52 #include <asm/arch/hardware.h> /* needed for AT91_USB_HOST_BASE */
53 #endif
54
55 #if defined(CONFIG_CPU_ARM920T) || \
56 defined(CONFIG_PCI_OHCI) || \
57 defined(CONFIG_DM_PCI) || \
58 defined(CONFIG_SYS_OHCI_USE_NPS)
59 # define OHCI_USE_NPS /* force NoPowerSwitching mode */
60 #endif
61
62 #undef OHCI_VERBOSE_DEBUG /* not always helpful */
63 #undef DEBUG
64 #undef SHOW_INFO
65 #undef OHCI_FILL_TRACE
66
67 /* For initializing controller (mask in an HCFS mode too) */
68 #define OHCI_CONTROL_INIT \
69 (OHCI_CTRL_CBSR & 0x3) | OHCI_CTRL_IE | OHCI_CTRL_PLE
70
71 #if !CONFIG_IS_ENABLED(DM_USB)
72 #ifdef CONFIG_PCI_OHCI
73 static struct pci_device_id ohci_pci_ids[] = {
74 {0x10b9, 0x5237}, /* ULI1575 PCI OHCI module ids */
75 {0x1033, 0x0035}, /* NEC PCI OHCI module ids */
76 {0x1131, 0x1561}, /* Philips 1561 PCI OHCI module ids */
77 /* Please add supported PCI OHCI controller ids here */
78 {0, 0}
79 };
80 #endif
81 #endif
82
83 #ifdef CONFIG_PCI_EHCI_DEVNO
84 static struct pci_device_id ehci_pci_ids[] = {
85 {0x1131, 0x1562}, /* Philips 1562 PCI EHCI module ids */
86 /* Please add supported PCI EHCI controller ids here */
87 {0, 0}
88 };
89 #endif
90
91 #ifdef DEBUG
92 #define dbg(format, arg...) printf("DEBUG: " format "\n", ## arg)
93 #else
94 #define dbg(format, arg...) do {} while (0)
95 #endif /* DEBUG */
96 #define err(format, arg...) printf("ERROR: " format "\n", ## arg)
97 #ifdef SHOW_INFO
98 #define info(format, arg...) printf("INFO: " format "\n", ## arg)
99 #else
100 #define info(format, arg...) do {} while (0)
101 #endif
102
103 #ifdef CONFIG_SYS_OHCI_BE_CONTROLLER
104 # define m16_swap(x) cpu_to_be16(x)
105 # define m32_swap(x) cpu_to_be32(x)
106 #else
107 # define m16_swap(x) cpu_to_le16(x)
108 # define m32_swap(x) cpu_to_le32(x)
109 #endif /* CONFIG_SYS_OHCI_BE_CONTROLLER */
110
111 /* We really should do proper cache flushing everywhere */
112 #define flush_dcache_buffer(addr, size) \
113 flush_dcache_range((unsigned long)(addr), \
114 ALIGN((unsigned long)(addr) + size, ARCH_DMA_MINALIGN))
115 #define invalidate_dcache_buffer(addr, size) \
116 invalidate_dcache_range((unsigned long)(addr), \
117 ALIGN((unsigned long)(addr) + size, ARCH_DMA_MINALIGN))
118
119 /* Do not use sizeof(ed / td) as our ed / td structs contain extra members */
120 #define flush_dcache_ed(addr) flush_dcache_buffer(addr, 16)
121 #define flush_dcache_td(addr) flush_dcache_buffer(addr, 16)
122 #define flush_dcache_iso_td(addr) flush_dcache_buffer(addr, 32)
123 #define flush_dcache_hcca(addr) flush_dcache_buffer(addr, 256)
124 #define invalidate_dcache_ed(addr) invalidate_dcache_buffer(addr, 16)
125 #define invalidate_dcache_td(addr) invalidate_dcache_buffer(addr, 16)
126 #define invalidate_dcache_iso_td(addr) invalidate_dcache_buffer(addr, 32)
127 #define invalidate_dcache_hcca(addr) invalidate_dcache_buffer(addr, 256)
128
129 #if CONFIG_IS_ENABLED(DM_USB)
130 /*
131 * The various ohci_mdelay(1) calls in the code seem unnecessary. We keep
132 * them around when building for older boards not yet converted to the dm
133 * just in case (to avoid regressions), for dm this turns them into nops.
134 */
135 #define ohci_mdelay(x)
136 #else
137 #define ohci_mdelay(x) mdelay(x)
138 #endif
139
140 #if !CONFIG_IS_ENABLED(DM_USB)
141 /* global ohci_t */
142 static ohci_t gohci;
143 /* this must be aligned to a 256 byte boundary */
144 struct ohci_hcca ghcca[1];
145 #endif
146
147 /* mapping of the OHCI CC status to error codes */
148 static int cc_to_error[16] = {
149 /* No Error */ 0,
150 /* CRC Error */ USB_ST_CRC_ERR,
151 /* Bit Stuff */ USB_ST_BIT_ERR,
152 /* Data Togg */ USB_ST_CRC_ERR,
153 /* Stall */ USB_ST_STALLED,
154 /* DevNotResp */ -1,
155 /* PIDCheck */ USB_ST_BIT_ERR,
156 /* UnExpPID */ USB_ST_BIT_ERR,
157 /* DataOver */ USB_ST_BUF_ERR,
158 /* DataUnder */ USB_ST_BUF_ERR,
159 /* reservd */ -1,
160 /* reservd */ -1,
161 /* BufferOver */ USB_ST_BUF_ERR,
162 /* BuffUnder */ USB_ST_BUF_ERR,
163 /* Not Access */ -1,
164 /* Not Access */ -1
165 };
166
167 static const char *cc_to_string[16] = {
168 "No Error",
169 "CRC: Last data packet from endpoint contained a CRC error.",
170 "BITSTUFFING: Last data packet from endpoint contained a bit " \
171 "stuffing violation",
172 "DATATOGGLEMISMATCH: Last packet from endpoint had data toggle PID\n" \
173 "that did not match the expected value.",
174 "STALL: TD was moved to the Done Queue because the endpoint returned" \
175 " a STALL PID",
176 "DEVICENOTRESPONDING: Device did not respond to token (IN) or did\n" \
177 "not provide a handshake (OUT)",
178 "PIDCHECKFAILURE: Check bits on PID from endpoint failed on data PID\n"\
179 "(IN) or handshake (OUT)",
180 "UNEXPECTEDPID: Receive PID was not valid when encountered or PID\n" \
181 "value is not defined.",
182 "DATAOVERRUN: The amount of data returned by the endpoint exceeded\n" \
183 "either the size of the maximum data packet allowed\n" \
184 "from the endpoint (found in MaximumPacketSize field\n" \
185 "of ED) or the remaining buffer size.",
186 "DATAUNDERRUN: The endpoint returned less than MaximumPacketSize\n" \
187 "and that amount was not sufficient to fill the\n" \
188 "specified buffer",
189 "reserved1",
190 "reserved2",
191 "BUFFEROVERRUN: During an IN, HC received data from endpoint faster\n" \
192 "than it could be written to system memory",
193 "BUFFERUNDERRUN: During an OUT, HC could not retrieve data from\n" \
194 "system memory fast enough to keep up with data USB " \
195 "data rate.",
196 "NOT ACCESSED: This code is set by software before the TD is placed" \
197 "on a list to be processed by the HC.(1)",
198 "NOT ACCESSED: This code is set by software before the TD is placed" \
199 "on a list to be processed by the HC.(2)",
200 };
201
roothub_a(struct ohci * hc)202 static inline u32 roothub_a(struct ohci *hc)
203 { return ohci_readl(&hc->regs->roothub.a); }
roothub_b(struct ohci * hc)204 static inline u32 roothub_b(struct ohci *hc)
205 { return ohci_readl(&hc->regs->roothub.b); }
roothub_status(struct ohci * hc)206 static inline u32 roothub_status(struct ohci *hc)
207 { return ohci_readl(&hc->regs->roothub.status); }
roothub_portstatus(struct ohci * hc,int i)208 static inline u32 roothub_portstatus(struct ohci *hc, int i)
209 { return ohci_readl(&hc->regs->roothub.portstatus[i]); }
210
211 /* forward declaration */
212 static int hc_interrupt(ohci_t *ohci);
213 static void td_submit_job(ohci_t *ohci, struct usb_device *dev,
214 unsigned long pipe, void *buffer, int transfer_len,
215 struct devrequest *setup, urb_priv_t *urb,
216 int interval);
217 static int ep_link(ohci_t * ohci, ed_t * ed);
218 static int ep_unlink(ohci_t * ohci, ed_t * ed);
219 static ed_t *ep_add_ed(ohci_dev_t *ohci_dev, struct usb_device *usb_dev,
220 unsigned long pipe, int interval, int load);
221
222 /*-------------------------------------------------------------------------*/
223
224 /* TDs ... */
td_alloc(ohci_dev_t * ohci_dev,struct usb_device * usb_dev)225 static struct td *td_alloc(ohci_dev_t *ohci_dev, struct usb_device *usb_dev)
226 {
227 int i;
228 struct td *td;
229
230 td = NULL;
231 for (i = 0; i < NUM_TD; i++)
232 {
233 if (ohci_dev->tds[i].usb_dev == NULL)
234 {
235 td = &ohci_dev->tds[i];
236 td->usb_dev = usb_dev;
237 break;
238 }
239 }
240
241 return td;
242 }
243
ed_free(struct ed * ed)244 static inline void ed_free(struct ed *ed)
245 {
246 ed->usb_dev = NULL;
247 }
248
249 /*-------------------------------------------------------------------------*
250 * URB support functions
251 *-------------------------------------------------------------------------*/
252
253 /* free HCD-private data associated with this URB */
254
urb_free_priv(urb_priv_t * urb)255 static void urb_free_priv(urb_priv_t *urb)
256 {
257 int i;
258 int last;
259 struct td *td;
260
261 last = urb->length - 1;
262 if (last >= 0) {
263 for (i = 0; i <= last; i++) {
264 td = urb->td[i];
265 if (td) {
266 td->usb_dev = NULL;
267 urb->td[i] = NULL;
268 }
269 }
270 }
271 free(urb);
272 }
273
274 /*-------------------------------------------------------------------------*/
275
276 #ifdef DEBUG
277 static int sohci_get_current_frame_number(ohci_t *ohci);
278
279 /* debug| print the main components of an URB
280 * small: 0) header + data packets 1) just header */
281
pkt_print(ohci_t * ohci,urb_priv_t * purb,struct usb_device * dev,unsigned long pipe,void * buffer,int transfer_len,struct devrequest * setup,char * str,int small)282 static void pkt_print(ohci_t *ohci, urb_priv_t *purb, struct usb_device *dev,
283 unsigned long pipe, void *buffer, int transfer_len,
284 struct devrequest *setup, char *str, int small)
285 {
286 dbg("%s URB:[%4x] dev:%2lu,ep:%2lu-%c,type:%s,len:%d/%d stat:%#lx",
287 str,
288 sohci_get_current_frame_number(ohci),
289 usb_pipedevice(pipe),
290 usb_pipeendpoint(pipe),
291 usb_pipeout(pipe)? 'O': 'I',
292 usb_pipetype(pipe) < 2 ? \
293 (usb_pipeint(pipe)? "INTR": "ISOC"): \
294 (usb_pipecontrol(pipe)? "CTRL": "BULK"),
295 (purb ? purb->actual_length : 0),
296 transfer_len, dev->status);
297 #ifdef OHCI_VERBOSE_DEBUG
298 if (!small) {
299 int i, len;
300
301 if (usb_pipecontrol(pipe)) {
302 printf(__FILE__ ": cmd(8):");
303 for (i = 0; i < 8 ; i++)
304 printf(" %02x", ((__u8 *) setup) [i]);
305 printf("\n");
306 }
307 if (transfer_len > 0 && buffer) {
308 printf(__FILE__ ": data(%d/%d):",
309 (purb ? purb->actual_length : 0),
310 transfer_len);
311 len = usb_pipeout(pipe)? transfer_len:
312 (purb ? purb->actual_length : 0);
313 for (i = 0; i < 16 && i < len; i++)
314 printf(" %02x", ((__u8 *) buffer) [i]);
315 printf("%s\n", i < len? "...": "");
316 }
317 }
318 #endif
319 }
320
321 /* just for debugging; prints non-empty branches of the int ed tree
322 * inclusive iso eds */
ep_print_int_eds(ohci_t * ohci,char * str)323 void ep_print_int_eds(ohci_t *ohci, char *str)
324 {
325 int i, j;
326 __u32 *ed_p;
327 for (i = 0; i < 32; i++) {
328 j = 5;
329 ed_p = &(ohci->hcca->int_table [i]);
330 if (*ed_p == 0)
331 continue;
332 invalidate_dcache_ed(ed_p);
333 printf(__FILE__ ": %s branch int %2d(%2x):", str, i, i);
334 while (*ed_p != 0 && j--) {
335 ed_t *ed = (ed_t *)m32_swap(ed_p);
336 invalidate_dcache_ed(ed);
337 printf(" ed: %4x;", ed->hwINFO);
338 ed_p = &ed->hwNextED;
339 }
340 printf("\n");
341 }
342 }
343
ohci_dump_intr_mask(char * label,__u32 mask)344 static void ohci_dump_intr_mask(char *label, __u32 mask)
345 {
346 dbg("%s: 0x%08x%s%s%s%s%s%s%s%s%s",
347 label,
348 mask,
349 (mask & OHCI_INTR_MIE) ? " MIE" : "",
350 (mask & OHCI_INTR_OC) ? " OC" : "",
351 (mask & OHCI_INTR_RHSC) ? " RHSC" : "",
352 (mask & OHCI_INTR_FNO) ? " FNO" : "",
353 (mask & OHCI_INTR_UE) ? " UE" : "",
354 (mask & OHCI_INTR_RD) ? " RD" : "",
355 (mask & OHCI_INTR_SF) ? " SF" : "",
356 (mask & OHCI_INTR_WDH) ? " WDH" : "",
357 (mask & OHCI_INTR_SO) ? " SO" : ""
358 );
359 }
360
maybe_print_eds(char * label,__u32 value)361 static void maybe_print_eds(char *label, __u32 value)
362 {
363 ed_t *edp = (ed_t *)value;
364
365 if (value) {
366 dbg("%s %08x", label, value);
367 invalidate_dcache_ed(edp);
368 dbg("%08x", edp->hwINFO);
369 dbg("%08x", edp->hwTailP);
370 dbg("%08x", edp->hwHeadP);
371 dbg("%08x", edp->hwNextED);
372 }
373 }
374
hcfs2string(int state)375 static char *hcfs2string(int state)
376 {
377 switch (state) {
378 case OHCI_USB_RESET: return "reset";
379 case OHCI_USB_RESUME: return "resume";
380 case OHCI_USB_OPER: return "operational";
381 case OHCI_USB_SUSPEND: return "suspend";
382 }
383 return "?";
384 }
385
386 /* dump control and status registers */
ohci_dump_status(ohci_t * controller)387 static void ohci_dump_status(ohci_t *controller)
388 {
389 struct ohci_regs *regs = controller->regs;
390 __u32 temp;
391
392 temp = ohci_readl(®s->revision) & 0xff;
393 if (temp != 0x10)
394 dbg("spec %d.%d", (temp >> 4), (temp & 0x0f));
395
396 temp = ohci_readl(®s->control);
397 dbg("control: 0x%08x%s%s%s HCFS=%s%s%s%s%s CBSR=%d", temp,
398 (temp & OHCI_CTRL_RWE) ? " RWE" : "",
399 (temp & OHCI_CTRL_RWC) ? " RWC" : "",
400 (temp & OHCI_CTRL_IR) ? " IR" : "",
401 hcfs2string(temp & OHCI_CTRL_HCFS),
402 (temp & OHCI_CTRL_BLE) ? " BLE" : "",
403 (temp & OHCI_CTRL_CLE) ? " CLE" : "",
404 (temp & OHCI_CTRL_IE) ? " IE" : "",
405 (temp & OHCI_CTRL_PLE) ? " PLE" : "",
406 temp & OHCI_CTRL_CBSR
407 );
408
409 temp = ohci_readl(®s->cmdstatus);
410 dbg("cmdstatus: 0x%08x SOC=%d%s%s%s%s", temp,
411 (temp & OHCI_SOC) >> 16,
412 (temp & OHCI_OCR) ? " OCR" : "",
413 (temp & OHCI_BLF) ? " BLF" : "",
414 (temp & OHCI_CLF) ? " CLF" : "",
415 (temp & OHCI_HCR) ? " HCR" : ""
416 );
417
418 ohci_dump_intr_mask("intrstatus", ohci_readl(®s->intrstatus));
419 ohci_dump_intr_mask("intrenable", ohci_readl(®s->intrenable));
420
421 maybe_print_eds("ed_periodcurrent",
422 ohci_readl(®s->ed_periodcurrent));
423
424 maybe_print_eds("ed_controlhead", ohci_readl(®s->ed_controlhead));
425 maybe_print_eds("ed_controlcurrent",
426 ohci_readl(®s->ed_controlcurrent));
427
428 maybe_print_eds("ed_bulkhead", ohci_readl(®s->ed_bulkhead));
429 maybe_print_eds("ed_bulkcurrent", ohci_readl(®s->ed_bulkcurrent));
430
431 maybe_print_eds("donehead", ohci_readl(®s->donehead));
432 }
433
ohci_dump_roothub(ohci_t * controller,int verbose)434 static void ohci_dump_roothub(ohci_t *controller, int verbose)
435 {
436 __u32 temp, ndp, i;
437
438 temp = roothub_a(controller);
439 ndp = (temp & RH_A_NDP);
440 #ifdef CONFIG_AT91C_PQFP_UHPBUG
441 ndp = (ndp == 2) ? 1:0;
442 #endif
443 if (verbose) {
444 dbg("roothub.a: %08x POTPGT=%d%s%s%s%s%s NDP=%d", temp,
445 ((temp & RH_A_POTPGT) >> 24) & 0xff,
446 (temp & RH_A_NOCP) ? " NOCP" : "",
447 (temp & RH_A_OCPM) ? " OCPM" : "",
448 (temp & RH_A_DT) ? " DT" : "",
449 (temp & RH_A_NPS) ? " NPS" : "",
450 (temp & RH_A_PSM) ? " PSM" : "",
451 ndp
452 );
453 temp = roothub_b(controller);
454 dbg("roothub.b: %08x PPCM=%04x DR=%04x",
455 temp,
456 (temp & RH_B_PPCM) >> 16,
457 (temp & RH_B_DR)
458 );
459 temp = roothub_status(controller);
460 dbg("roothub.status: %08x%s%s%s%s%s%s",
461 temp,
462 (temp & RH_HS_CRWE) ? " CRWE" : "",
463 (temp & RH_HS_OCIC) ? " OCIC" : "",
464 (temp & RH_HS_LPSC) ? " LPSC" : "",
465 (temp & RH_HS_DRWE) ? " DRWE" : "",
466 (temp & RH_HS_OCI) ? " OCI" : "",
467 (temp & RH_HS_LPS) ? " LPS" : ""
468 );
469 }
470
471 for (i = 0; i < ndp; i++) {
472 temp = roothub_portstatus(controller, i);
473 dbg("roothub.portstatus [%d] = 0x%08x%s%s%s%s%s%s%s%s%s%s%s%s",
474 i,
475 temp,
476 (temp & RH_PS_PRSC) ? " PRSC" : "",
477 (temp & RH_PS_OCIC) ? " OCIC" : "",
478 (temp & RH_PS_PSSC) ? " PSSC" : "",
479 (temp & RH_PS_PESC) ? " PESC" : "",
480 (temp & RH_PS_CSC) ? " CSC" : "",
481
482 (temp & RH_PS_LSDA) ? " LSDA" : "",
483 (temp & RH_PS_PPS) ? " PPS" : "",
484 (temp & RH_PS_PRS) ? " PRS" : "",
485 (temp & RH_PS_POCI) ? " POCI" : "",
486 (temp & RH_PS_PSS) ? " PSS" : "",
487
488 (temp & RH_PS_PES) ? " PES" : "",
489 (temp & RH_PS_CCS) ? " CCS" : ""
490 );
491 }
492 }
493
ohci_dump(ohci_t * controller,int verbose)494 static void ohci_dump(ohci_t *controller, int verbose)
495 {
496 dbg("OHCI controller usb-%s state", controller->slot_name);
497
498 /* dumps some of the state we know about */
499 ohci_dump_status(controller);
500 if (verbose)
501 ep_print_int_eds(controller, "hcca");
502 invalidate_dcache_hcca(controller->hcca);
503 dbg("hcca frame #%04x", controller->hcca->frame_no);
504 ohci_dump_roothub(controller, 1);
505 }
506 #endif /* DEBUG */
507
508 /*-------------------------------------------------------------------------*
509 * Interface functions (URB)
510 *-------------------------------------------------------------------------*/
511
512 /* get a transfer request */
513
sohci_submit_job(ohci_t * ohci,ohci_dev_t * ohci_dev,urb_priv_t * urb,struct devrequest * setup)514 int sohci_submit_job(ohci_t *ohci, ohci_dev_t *ohci_dev, urb_priv_t *urb,
515 struct devrequest *setup)
516 {
517 ed_t *ed;
518 urb_priv_t *purb_priv = urb;
519 int i, size = 0;
520 struct usb_device *dev = urb->dev;
521 unsigned long pipe = urb->pipe;
522 void *buffer = urb->transfer_buffer;
523 int transfer_len = urb->transfer_buffer_length;
524 int interval = urb->interval;
525
526 /* when controller's hung, permit only roothub cleanup attempts
527 * such as powering down ports */
528 if (ohci->disabled) {
529 err("sohci_submit_job: EPIPE");
530 return -1;
531 }
532
533 /* we're about to begin a new transaction here so mark the
534 * URB unfinished */
535 urb->finished = 0;
536
537 /* every endpoint has a ed, locate and fill it */
538 ed = ep_add_ed(ohci_dev, dev, pipe, interval, 1);
539 if (!ed) {
540 err("sohci_submit_job: ENOMEM");
541 return -1;
542 }
543
544 /* for the private part of the URB we need the number of TDs (size) */
545 switch (usb_pipetype(pipe)) {
546 case PIPE_BULK: /* one TD for every 4096 Byte */
547 size = (transfer_len - 1) / 4096 + 1;
548 break;
549 case PIPE_CONTROL:/* 1 TD for setup, 1 for ACK and 1 for every 4096 B */
550 size = (transfer_len == 0)? 2:
551 (transfer_len - 1) / 4096 + 3;
552 break;
553 case PIPE_INTERRUPT: /* 1 TD */
554 size = 1;
555 break;
556 }
557
558 ed->purb = urb;
559
560 if (size >= (N_URB_TD - 1)) {
561 err("need %d TDs, only have %d", size, N_URB_TD);
562 return -1;
563 }
564 purb_priv->pipe = pipe;
565
566 /* fill the private part of the URB */
567 purb_priv->length = size;
568 purb_priv->ed = ed;
569 purb_priv->actual_length = 0;
570
571 /* allocate the TDs */
572 /* note that td[0] was allocated in ep_add_ed */
573 for (i = 0; i < size; i++) {
574 purb_priv->td[i] = td_alloc(ohci_dev, dev);
575 if (!purb_priv->td[i]) {
576 purb_priv->length = i;
577 urb_free_priv(purb_priv);
578 err("sohci_submit_job: ENOMEM");
579 return -1;
580 }
581 }
582
583 if (ed->state == ED_NEW || (ed->state & ED_DEL)) {
584 urb_free_priv(purb_priv);
585 err("sohci_submit_job: EINVAL");
586 return -1;
587 }
588
589 /* link the ed into a chain if is not already */
590 if (ed->state != ED_OPER)
591 ep_link(ohci, ed);
592
593 /* fill the TDs and link it to the ed */
594 td_submit_job(ohci, dev, pipe, buffer, transfer_len,
595 setup, purb_priv, interval);
596
597 return 0;
598 }
599
600 /*-------------------------------------------------------------------------*/
601
602 #ifdef DEBUG
603 /* tell us the current USB frame number */
sohci_get_current_frame_number(ohci_t * ohci)604 static int sohci_get_current_frame_number(ohci_t *ohci)
605 {
606 invalidate_dcache_hcca(ohci->hcca);
607 return m16_swap(ohci->hcca->frame_no);
608 }
609 #endif
610
611 /*-------------------------------------------------------------------------*
612 * ED handling functions
613 *-------------------------------------------------------------------------*/
614
615 /* search for the right branch to insert an interrupt ed into the int tree
616 * do some load ballancing;
617 * returns the branch and
618 * sets the interval to interval = 2^integer (ld (interval)) */
619
ep_int_ballance(ohci_t * ohci,int interval,int load)620 static int ep_int_ballance(ohci_t *ohci, int interval, int load)
621 {
622 int i, branch = 0;
623
624 /* search for the least loaded interrupt endpoint
625 * branch of all 32 branches
626 */
627 for (i = 0; i < 32; i++)
628 if (ohci->ohci_int_load [branch] > ohci->ohci_int_load [i])
629 branch = i;
630
631 branch = branch % interval;
632 for (i = branch; i < 32; i += interval)
633 ohci->ohci_int_load [i] += load;
634
635 return branch;
636 }
637
638 /*-------------------------------------------------------------------------*/
639
640 /* 2^int( ld (inter)) */
641
ep_2_n_interval(int inter)642 static int ep_2_n_interval(int inter)
643 {
644 int i;
645 for (i = 0; ((inter >> i) > 1) && (i < 5); i++);
646 return 1 << i;
647 }
648
649 /*-------------------------------------------------------------------------*/
650
651 /* the int tree is a binary tree
652 * in order to process it sequentially the indexes of the branches have to
653 * be mapped the mapping reverses the bits of a word of num_bits length */
ep_rev(int num_bits,int word)654 static int ep_rev(int num_bits, int word)
655 {
656 int i, wout = 0;
657
658 for (i = 0; i < num_bits; i++)
659 wout |= (((word >> i) & 1) << (num_bits - i - 1));
660 return wout;
661 }
662
663 /*-------------------------------------------------------------------------*
664 * ED handling functions
665 *-------------------------------------------------------------------------*/
666
667 /* link an ed into one of the HC chains */
668
ep_link(ohci_t * ohci,ed_t * edi)669 static int ep_link(ohci_t *ohci, ed_t *edi)
670 {
671 volatile ed_t *ed = edi;
672 int int_branch;
673 int i;
674 int inter;
675 int interval;
676 int load;
677 __u32 *ed_p;
678
679 ed->state = ED_OPER;
680 ed->int_interval = 0;
681
682 switch (ed->type) {
683 case PIPE_CONTROL:
684 ed->hwNextED = 0;
685 flush_dcache_ed(ed);
686 if (ohci->ed_controltail == NULL)
687 ohci_writel((uintptr_t)ed, &ohci->regs->ed_controlhead);
688 else
689 ohci->ed_controltail->hwNextED =
690 m32_swap((unsigned long)ed);
691
692 ed->ed_prev = ohci->ed_controltail;
693 if (!ohci->ed_controltail && !ohci->ed_rm_list[0] &&
694 !ohci->ed_rm_list[1] && !ohci->sleeping) {
695 ohci->hc_control |= OHCI_CTRL_CLE;
696 ohci_writel(ohci->hc_control, &ohci->regs->control);
697 }
698 ohci->ed_controltail = edi;
699 break;
700
701 case PIPE_BULK:
702 ed->hwNextED = 0;
703 flush_dcache_ed(ed);
704 if (ohci->ed_bulktail == NULL)
705 ohci_writel((uintptr_t)ed, &ohci->regs->ed_bulkhead);
706 else
707 ohci->ed_bulktail->hwNextED =
708 m32_swap((unsigned long)ed);
709
710 ed->ed_prev = ohci->ed_bulktail;
711 if (!ohci->ed_bulktail && !ohci->ed_rm_list[0] &&
712 !ohci->ed_rm_list[1] && !ohci->sleeping) {
713 ohci->hc_control |= OHCI_CTRL_BLE;
714 ohci_writel(ohci->hc_control, &ohci->regs->control);
715 }
716 ohci->ed_bulktail = edi;
717 break;
718
719 case PIPE_INTERRUPT:
720 load = ed->int_load;
721 interval = ep_2_n_interval(ed->int_period);
722 ed->int_interval = interval;
723 int_branch = ep_int_ballance(ohci, interval, load);
724 ed->int_branch = int_branch;
725
726 for (i = 0; i < ep_rev(6, interval); i += inter) {
727 inter = 1;
728 for (ed_p = &(ohci->hcca->int_table[\
729 ep_rev(5, i) + int_branch]);
730 (*ed_p != 0) &&
731 (((ed_t *)ed_p)->int_interval >= interval);
732 ed_p = &(((ed_t *)ed_p)->hwNextED))
733 inter = ep_rev(6,
734 ((ed_t *)ed_p)->int_interval);
735 ed->hwNextED = *ed_p;
736 flush_dcache_ed(ed);
737 *ed_p = m32_swap((unsigned long)ed);
738 flush_dcache_hcca(ohci->hcca);
739 }
740 break;
741 }
742 return 0;
743 }
744
745 /*-------------------------------------------------------------------------*/
746
747 /* scan the periodic table to find and unlink this ED */
periodic_unlink(struct ohci * ohci,volatile struct ed * ed,unsigned index,unsigned period)748 static void periodic_unlink(struct ohci *ohci, volatile struct ed *ed,
749 unsigned index, unsigned period)
750 {
751 __maybe_unused unsigned long aligned_ed_p;
752
753 for (; index < NUM_INTS; index += period) {
754 __u32 *ed_p = &ohci->hcca->int_table [index];
755
756 /* ED might have been unlinked through another path */
757 while (*ed_p != 0) {
758 if (((struct ed *)(uintptr_t)
759 m32_swap((unsigned long)ed_p)) == ed) {
760 *ed_p = ed->hwNextED;
761 aligned_ed_p = (unsigned long)ed_p;
762 aligned_ed_p &= ~(ARCH_DMA_MINALIGN - 1);
763 flush_dcache_range(aligned_ed_p,
764 aligned_ed_p + ARCH_DMA_MINALIGN);
765 break;
766 }
767 ed_p = &(((struct ed *)(uintptr_t)
768 m32_swap((unsigned long)ed_p))->hwNextED);
769 }
770 }
771 }
772
773 /* unlink an ed from one of the HC chains.
774 * just the link to the ed is unlinked.
775 * the link from the ed still points to another operational ed or 0
776 * so the HC can eventually finish the processing of the unlinked ed */
777
ep_unlink(ohci_t * ohci,ed_t * edi)778 static int ep_unlink(ohci_t *ohci, ed_t *edi)
779 {
780 volatile ed_t *ed = edi;
781 int i;
782
783 ed->hwINFO |= m32_swap(OHCI_ED_SKIP);
784 flush_dcache_ed(ed);
785
786 switch (ed->type) {
787 case PIPE_CONTROL:
788 if (ed->ed_prev == NULL) {
789 if (!ed->hwNextED) {
790 ohci->hc_control &= ~OHCI_CTRL_CLE;
791 ohci_writel(ohci->hc_control,
792 &ohci->regs->control);
793 }
794 ohci_writel(m32_swap(*((__u32 *)&ed->hwNextED)),
795 &ohci->regs->ed_controlhead);
796 } else {
797 ed->ed_prev->hwNextED = ed->hwNextED;
798 flush_dcache_ed(ed->ed_prev);
799 }
800 if (ohci->ed_controltail == ed) {
801 ohci->ed_controltail = ed->ed_prev;
802 } else {
803 ((ed_t *)(uintptr_t)m32_swap(
804 *((__u32 *)&ed->hwNextED)))->ed_prev = ed->ed_prev;
805 }
806 break;
807
808 case PIPE_BULK:
809 if (ed->ed_prev == NULL) {
810 if (!ed->hwNextED) {
811 ohci->hc_control &= ~OHCI_CTRL_BLE;
812 ohci_writel(ohci->hc_control,
813 &ohci->regs->control);
814 }
815 ohci_writel(m32_swap(*((__u32 *)&ed->hwNextED)),
816 &ohci->regs->ed_bulkhead);
817 } else {
818 ed->ed_prev->hwNextED = ed->hwNextED;
819 flush_dcache_ed(ed->ed_prev);
820 }
821 if (ohci->ed_bulktail == ed) {
822 ohci->ed_bulktail = ed->ed_prev;
823 } else {
824 ((ed_t *)(uintptr_t)m32_swap(
825 *((__u32 *)&ed->hwNextED)))->ed_prev = ed->ed_prev;
826 }
827 break;
828
829 case PIPE_INTERRUPT:
830 periodic_unlink(ohci, ed, 0, 1);
831 for (i = ed->int_branch; i < 32; i += ed->int_interval)
832 ohci->ohci_int_load[i] -= ed->int_load;
833 break;
834 }
835 ed->state = ED_UNLINK;
836 return 0;
837 }
838
839 /*-------------------------------------------------------------------------*/
840
841 /* add/reinit an endpoint; this should be done once at the
842 * usb_set_configuration command, but the USB stack is a little bit
843 * stateless so we do it at every transaction if the state of the ed
844 * is ED_NEW then a dummy td is added and the state is changed to
845 * ED_UNLINK in all other cases the state is left unchanged the ed
846 * info fields are setted anyway even though most of them should not
847 * change
848 */
ep_add_ed(ohci_dev_t * ohci_dev,struct usb_device * usb_dev,unsigned long pipe,int interval,int load)849 static ed_t *ep_add_ed(ohci_dev_t *ohci_dev, struct usb_device *usb_dev,
850 unsigned long pipe, int interval, int load)
851 {
852 td_t *td;
853 ed_t *ed_ret;
854 volatile ed_t *ed;
855
856 ed = ed_ret = &ohci_dev->ed[(usb_pipeendpoint(pipe) << 1) |
857 (usb_pipecontrol(pipe)? 0: usb_pipeout(pipe))];
858
859 if ((ed->state & ED_DEL) || (ed->state & ED_URB_DEL)) {
860 err("ep_add_ed: pending delete");
861 /* pending delete request */
862 return NULL;
863 }
864
865 if (ed->state == ED_NEW) {
866 /* dummy td; end of td list for ed */
867 td = td_alloc(ohci_dev, usb_dev);
868 ed->hwTailP = m32_swap((unsigned long)td);
869 ed->hwHeadP = ed->hwTailP;
870 ed->state = ED_UNLINK;
871 ed->type = usb_pipetype(pipe);
872 ohci_dev->ed_cnt++;
873 }
874
875 ed->hwINFO = m32_swap(usb_pipedevice(pipe)
876 | usb_pipeendpoint(pipe) << 7
877 | (usb_pipeisoc(pipe)? 0x8000: 0)
878 | (usb_pipecontrol(pipe)? 0: \
879 (usb_pipeout(pipe)? 0x800: 0x1000))
880 | (usb_dev->speed == USB_SPEED_LOW) << 13
881 | usb_maxpacket(usb_dev, pipe) << 16);
882
883 if (ed->type == PIPE_INTERRUPT && ed->state == ED_UNLINK) {
884 ed->int_period = interval;
885 ed->int_load = load;
886 }
887
888 flush_dcache_ed(ed);
889
890 return ed_ret;
891 }
892
893 /*-------------------------------------------------------------------------*
894 * TD handling functions
895 *-------------------------------------------------------------------------*/
896
897 /* enqueue next TD for this URB (OHCI spec 5.2.8.2) */
898
td_fill(ohci_t * ohci,unsigned int info,void * data,int len,struct usb_device * dev,int index,urb_priv_t * urb_priv)899 static void td_fill(ohci_t *ohci, unsigned int info,
900 void *data, int len,
901 struct usb_device *dev, int index, urb_priv_t *urb_priv)
902 {
903 volatile td_t *td, *td_pt;
904 #ifdef OHCI_FILL_TRACE
905 int i;
906 #endif
907
908 if (index > urb_priv->length) {
909 err("index > length");
910 return;
911 }
912 /* use this td as the next dummy */
913 td_pt = urb_priv->td [index];
914 td_pt->hwNextTD = 0;
915 flush_dcache_td(td_pt);
916
917 /* fill the old dummy TD */
918 td = urb_priv->td [index] =
919 (td_t *)(uintptr_t)
920 (m32_swap(urb_priv->ed->hwTailP) & ~0xf);
921
922 td->ed = urb_priv->ed;
923 td->next_dl_td = NULL;
924 td->index = index;
925 td->data = (uintptr_t)data;
926 #ifdef OHCI_FILL_TRACE
927 if (usb_pipebulk(urb_priv->pipe) && usb_pipeout(urb_priv->pipe)) {
928 for (i = 0; i < len; i++)
929 printf("td->data[%d] %#2x ", i, ((unsigned char *)td->data)[i]);
930 printf("\n");
931 }
932 #endif
933 if (!len)
934 data = 0;
935
936 td->hwINFO = m32_swap(info);
937 td->hwCBP = m32_swap((unsigned long)data);
938 if (data)
939 td->hwBE = m32_swap((unsigned long)(data + len - 1));
940 else
941 td->hwBE = 0;
942
943 td->hwNextTD = m32_swap((unsigned long)td_pt);
944 flush_dcache_td(td);
945
946 /* append to queue */
947 td->ed->hwTailP = td->hwNextTD;
948 flush_dcache_ed(td->ed);
949 }
950
951 /*-------------------------------------------------------------------------*/
952
953 /* prepare all TDs of a transfer */
954
td_submit_job(ohci_t * ohci,struct usb_device * dev,unsigned long pipe,void * buffer,int transfer_len,struct devrequest * setup,urb_priv_t * urb,int interval)955 static void td_submit_job(ohci_t *ohci, struct usb_device *dev,
956 unsigned long pipe, void *buffer, int transfer_len,
957 struct devrequest *setup, urb_priv_t *urb,
958 int interval)
959 {
960 int data_len = transfer_len;
961 void *data;
962 int cnt = 0;
963 __u32 info = 0;
964 unsigned int toggle = 0;
965
966 flush_dcache_buffer(buffer, data_len);
967
968 /* OHCI handles the DATA-toggles itself, we just use the USB-toggle
969 * bits for resetting */
970 if (usb_gettoggle(dev, usb_pipeendpoint(pipe), usb_pipeout(pipe))) {
971 toggle = TD_T_TOGGLE;
972 } else {
973 toggle = TD_T_DATA0;
974 usb_settoggle(dev, usb_pipeendpoint(pipe),
975 usb_pipeout(pipe), 1);
976 }
977 urb->td_cnt = 0;
978 if (data_len)
979 data = buffer;
980 else
981 data = 0;
982
983 switch (usb_pipetype(pipe)) {
984 case PIPE_BULK:
985 info = usb_pipeout(pipe)?
986 TD_CC | TD_DP_OUT : TD_CC | TD_DP_IN ;
987 while (data_len > 4096) {
988 td_fill(ohci, info | (cnt? TD_T_TOGGLE:toggle),
989 data, 4096, dev, cnt, urb);
990 data += 4096; data_len -= 4096; cnt++;
991 }
992 info = usb_pipeout(pipe)?
993 TD_CC | TD_DP_OUT : TD_CC | TD_R | TD_DP_IN ;
994 td_fill(ohci, info | (cnt? TD_T_TOGGLE:toggle), data,
995 data_len, dev, cnt, urb);
996 cnt++;
997
998 if (!ohci->sleeping) {
999 /* start bulk list */
1000 ohci_writel(OHCI_BLF, &ohci->regs->cmdstatus);
1001 }
1002 break;
1003
1004 case PIPE_CONTROL:
1005 /* Setup phase */
1006 info = TD_CC | TD_DP_SETUP | TD_T_DATA0;
1007 flush_dcache_buffer(setup, 8);
1008 td_fill(ohci, info, setup, 8, dev, cnt++, urb);
1009
1010 /* Optional Data phase */
1011 if (data_len > 0) {
1012 info = usb_pipeout(pipe)?
1013 TD_CC | TD_R | TD_DP_OUT | TD_T_DATA1 :
1014 TD_CC | TD_R | TD_DP_IN | TD_T_DATA1;
1015 /* NOTE: mishandles transfers >8K, some >4K */
1016 td_fill(ohci, info, data, data_len, dev, cnt++, urb);
1017 }
1018
1019 /* Status phase */
1020 info = (usb_pipeout(pipe) || data_len == 0) ?
1021 TD_CC | TD_DP_IN | TD_T_DATA1:
1022 TD_CC | TD_DP_OUT | TD_T_DATA1;
1023 td_fill(ohci, info, data, 0, dev, cnt++, urb);
1024
1025 if (!ohci->sleeping) {
1026 /* start Control list */
1027 ohci_writel(OHCI_CLF, &ohci->regs->cmdstatus);
1028 }
1029 break;
1030
1031 case PIPE_INTERRUPT:
1032 info = usb_pipeout(urb->pipe)?
1033 TD_CC | TD_DP_OUT | toggle:
1034 TD_CC | TD_R | TD_DP_IN | toggle;
1035 td_fill(ohci, info, data, data_len, dev, cnt++, urb);
1036 break;
1037 }
1038 if (urb->length != cnt)
1039 dbg("TD LENGTH %d != CNT %d", urb->length, cnt);
1040 }
1041
1042 /*-------------------------------------------------------------------------*
1043 * Done List handling functions
1044 *-------------------------------------------------------------------------*/
1045
1046 /* calculate the transfer length and update the urb */
1047
dl_transfer_length(td_t * td)1048 static void dl_transfer_length(td_t *td)
1049 {
1050 __u32 tdBE, tdCBP;
1051 urb_priv_t *lurb_priv = td->ed->purb;
1052
1053 tdBE = m32_swap(td->hwBE);
1054 tdCBP = m32_swap(td->hwCBP);
1055
1056 if (!(usb_pipecontrol(lurb_priv->pipe) &&
1057 ((td->index == 0) || (td->index == lurb_priv->length - 1)))) {
1058 if (tdBE != 0) {
1059 if (td->hwCBP == 0)
1060 lurb_priv->actual_length += tdBE - td->data + 1;
1061 else
1062 lurb_priv->actual_length += tdCBP - td->data;
1063 }
1064 }
1065 }
1066
1067 /*-------------------------------------------------------------------------*/
check_status(td_t * td_list)1068 static void check_status(td_t *td_list)
1069 {
1070 urb_priv_t *lurb_priv = td_list->ed->purb;
1071 int urb_len = lurb_priv->length;
1072 __u32 *phwHeadP = &td_list->ed->hwHeadP;
1073 int cc;
1074
1075 cc = TD_CC_GET(m32_swap(td_list->hwINFO));
1076 if (cc) {
1077 err(" USB-error: %s (%x)", cc_to_string[cc], cc);
1078
1079 invalidate_dcache_ed(td_list->ed);
1080 if (*phwHeadP & m32_swap(0x1)) {
1081 if (lurb_priv &&
1082 ((td_list->index + 1) < urb_len)) {
1083 *phwHeadP =
1084 (lurb_priv->td[urb_len - 1]->hwNextTD &\
1085 m32_swap(0xfffffff0)) |
1086 (*phwHeadP & m32_swap(0x2));
1087
1088 lurb_priv->td_cnt += urb_len -
1089 td_list->index - 1;
1090 } else
1091 *phwHeadP &= m32_swap(0xfffffff2);
1092 flush_dcache_ed(td_list->ed);
1093 }
1094 }
1095 }
1096
1097 /* replies to the request have to be on a FIFO basis so
1098 * we reverse the reversed done-list */
dl_reverse_done_list(ohci_t * ohci)1099 static td_t *dl_reverse_done_list(ohci_t *ohci)
1100 {
1101 uintptr_t td_list_hc;
1102 td_t *td_rev = NULL;
1103 td_t *td_list = NULL;
1104
1105 invalidate_dcache_hcca(ohci->hcca);
1106 td_list_hc = m32_swap(ohci->hcca->done_head) & 0xfffffff0;
1107 ohci->hcca->done_head = 0;
1108 flush_dcache_hcca(ohci->hcca);
1109
1110 while (td_list_hc) {
1111 td_list = (td_t *)td_list_hc;
1112 invalidate_dcache_td(td_list);
1113 check_status(td_list);
1114 td_list->next_dl_td = td_rev;
1115 td_rev = td_list;
1116 td_list_hc = m32_swap(td_list->hwNextTD) & 0xfffffff0;
1117 }
1118 return td_list;
1119 }
1120
1121 /*-------------------------------------------------------------------------*/
1122 /*-------------------------------------------------------------------------*/
1123
finish_urb(ohci_t * ohci,urb_priv_t * urb,int status)1124 static void finish_urb(ohci_t *ohci, urb_priv_t *urb, int status)
1125 {
1126 if ((status & (ED_OPER | ED_UNLINK)) && (urb->state != URB_DEL))
1127 urb->finished = 1;
1128 else
1129 dbg("finish_urb: strange.., ED state %x, \n", status);
1130 }
1131
1132 /*
1133 * Used to take back a TD from the host controller. This would normally be
1134 * called from within dl_done_list, however it may be called directly if the
1135 * HC no longer sees the TD and it has not appeared on the donelist (after
1136 * two frames). This bug has been observed on ZF Micro systems.
1137 */
takeback_td(ohci_t * ohci,td_t * td_list)1138 static int takeback_td(ohci_t *ohci, td_t *td_list)
1139 {
1140 ed_t *ed;
1141 int cc;
1142 int stat = 0;
1143 /* urb_t *urb; */
1144 urb_priv_t *lurb_priv;
1145 __u32 tdINFO, edHeadP, edTailP;
1146
1147 invalidate_dcache_td(td_list);
1148 tdINFO = m32_swap(td_list->hwINFO);
1149
1150 ed = td_list->ed;
1151 lurb_priv = ed->purb;
1152
1153 dl_transfer_length(td_list);
1154
1155 lurb_priv->td_cnt++;
1156
1157 /* error code of transfer */
1158 cc = TD_CC_GET(tdINFO);
1159 if (cc) {
1160 err("USB-error: %s (%x)", cc_to_string[cc], cc);
1161 stat = cc_to_error[cc];
1162 }
1163
1164 /* see if this done list makes for all TD's of current URB,
1165 * and mark the URB finished if so */
1166 if (lurb_priv->td_cnt == lurb_priv->length)
1167 finish_urb(ohci, lurb_priv, ed->state);
1168
1169 dbg("dl_done_list: processing TD %x, len %x\n",
1170 lurb_priv->td_cnt, lurb_priv->length);
1171
1172 if (ed->state != ED_NEW && (!usb_pipeint(lurb_priv->pipe))) {
1173 invalidate_dcache_ed(ed);
1174 edHeadP = m32_swap(ed->hwHeadP) & 0xfffffff0;
1175 edTailP = m32_swap(ed->hwTailP);
1176
1177 /* unlink eds if they are not busy */
1178 if ((edHeadP == edTailP) && (ed->state == ED_OPER))
1179 ep_unlink(ohci, ed);
1180 }
1181 return stat;
1182 }
1183
dl_done_list(ohci_t * ohci)1184 static int dl_done_list(ohci_t *ohci)
1185 {
1186 int stat = 0;
1187 td_t *td_list = dl_reverse_done_list(ohci);
1188
1189 while (td_list) {
1190 td_t *td_next = td_list->next_dl_td;
1191 stat = takeback_td(ohci, td_list);
1192 td_list = td_next;
1193 }
1194 return stat;
1195 }
1196
1197 /*-------------------------------------------------------------------------*
1198 * Virtual Root Hub
1199 *-------------------------------------------------------------------------*/
1200
1201 #include <usbroothubdes.h>
1202
1203 /* Hub class-specific descriptor is constructed dynamically */
1204
1205 /*-------------------------------------------------------------------------*/
1206
1207 #define OK(x) len = (x); break
1208 #ifdef DEBUG
1209 #define WR_RH_STAT(x) {info("WR:status %#8x", (x)); ohci_writel((x), \
1210 &ohci->regs->roothub.status); }
1211 #define WR_RH_PORTSTAT(x) {info("WR:portstatus[%d] %#8x", wIndex-1, \
1212 (x)); ohci_writel((x), &ohci->regs->roothub.portstatus[wIndex-1]); }
1213 #else
1214 #define WR_RH_STAT(x) ohci_writel((x), &ohci->regs->roothub.status)
1215 #define WR_RH_PORTSTAT(x) ohci_writel((x), \
1216 &ohci->regs->roothub.portstatus[wIndex-1])
1217 #endif
1218 #define RD_RH_STAT roothub_status(ohci)
1219 #define RD_RH_PORTSTAT roothub_portstatus(ohci, wIndex-1)
1220
1221 /* request to virtual root hub */
1222
rh_check_port_status(ohci_t * controller)1223 int rh_check_port_status(ohci_t *controller)
1224 {
1225 __u32 temp, ndp, i;
1226 int res;
1227
1228 res = -1;
1229 temp = roothub_a(controller);
1230 ndp = (temp & RH_A_NDP);
1231 #ifdef CONFIG_AT91C_PQFP_UHPBUG
1232 ndp = (ndp == 2) ? 1:0;
1233 #endif
1234 for (i = 0; i < ndp; i++) {
1235 temp = roothub_portstatus(controller, i);
1236 /* check for a device disconnect */
1237 if (((temp & (RH_PS_PESC | RH_PS_CSC)) ==
1238 (RH_PS_PESC | RH_PS_CSC)) &&
1239 ((temp & RH_PS_CCS) == 0)) {
1240 res = i;
1241 break;
1242 }
1243 }
1244 return res;
1245 }
1246
ohci_submit_rh_msg(ohci_t * ohci,struct usb_device * dev,unsigned long pipe,void * buffer,int transfer_len,struct devrequest * cmd)1247 static int ohci_submit_rh_msg(ohci_t *ohci, struct usb_device *dev,
1248 unsigned long pipe, void *buffer, int transfer_len,
1249 struct devrequest *cmd)
1250 {
1251 void *data = buffer;
1252 int leni = transfer_len;
1253 int len = 0;
1254 int stat = 0;
1255 __u16 bmRType_bReq;
1256 __u16 wValue;
1257 __u16 wIndex;
1258 __u16 wLength;
1259 ALLOC_ALIGN_BUFFER(__u8, databuf, 16, sizeof(u32));
1260
1261 #ifdef DEBUG
1262 pkt_print(ohci, NULL, dev, pipe, buffer, transfer_len,
1263 cmd, "SUB(rh)", usb_pipein(pipe));
1264 #else
1265 ohci_mdelay(1);
1266 #endif
1267 if (usb_pipeint(pipe)) {
1268 info("Root-Hub submit IRQ: NOT implemented");
1269 return 0;
1270 }
1271
1272 bmRType_bReq = cmd->requesttype | (cmd->request << 8);
1273 wValue = le16_to_cpu(cmd->value);
1274 wIndex = le16_to_cpu(cmd->index);
1275 wLength = le16_to_cpu(cmd->length);
1276
1277 info("Root-Hub: adr: %2x cmd(%1x): %08x %04x %04x %04x",
1278 dev->devnum, 8, bmRType_bReq, wValue, wIndex, wLength);
1279
1280 switch (bmRType_bReq) {
1281 /* Request Destination:
1282 without flags: Device,
1283 RH_INTERFACE: interface,
1284 RH_ENDPOINT: endpoint,
1285 RH_CLASS means HUB here,
1286 RH_OTHER | RH_CLASS almost ever means HUB_PORT here
1287 */
1288
1289 case RH_GET_STATUS:
1290 *(u16 *)databuf = cpu_to_le16(1);
1291 OK(2);
1292 case RH_GET_STATUS | RH_INTERFACE:
1293 *(u16 *)databuf = cpu_to_le16(0);
1294 OK(2);
1295 case RH_GET_STATUS | RH_ENDPOINT:
1296 *(u16 *)databuf = cpu_to_le16(0);
1297 OK(2);
1298 case RH_GET_STATUS | RH_CLASS:
1299 *(u32 *)databuf = cpu_to_le32(
1300 RD_RH_STAT & ~(RH_HS_CRWE | RH_HS_DRWE));
1301 OK(4);
1302 case RH_GET_STATUS | RH_OTHER | RH_CLASS:
1303 *(u32 *)databuf = cpu_to_le32(RD_RH_PORTSTAT);
1304 OK(4);
1305
1306 case RH_CLEAR_FEATURE | RH_ENDPOINT:
1307 switch (wValue) {
1308 case (RH_ENDPOINT_STALL):
1309 OK(0);
1310 }
1311 break;
1312
1313 case RH_CLEAR_FEATURE | RH_CLASS:
1314 switch (wValue) {
1315 case RH_C_HUB_LOCAL_POWER:
1316 OK(0);
1317 case (RH_C_HUB_OVER_CURRENT):
1318 WR_RH_STAT(RH_HS_OCIC);
1319 OK(0);
1320 }
1321 break;
1322
1323 case RH_CLEAR_FEATURE | RH_OTHER | RH_CLASS:
1324 switch (wValue) {
1325 case (RH_PORT_ENABLE): WR_RH_PORTSTAT(RH_PS_CCS); OK(0);
1326 case (RH_PORT_SUSPEND): WR_RH_PORTSTAT(RH_PS_POCI); OK(0);
1327 case (RH_PORT_POWER): WR_RH_PORTSTAT(RH_PS_LSDA); OK(0);
1328 case (RH_C_PORT_CONNECTION): WR_RH_PORTSTAT(RH_PS_CSC); OK(0);
1329 case (RH_C_PORT_ENABLE): WR_RH_PORTSTAT(RH_PS_PESC); OK(0);
1330 case (RH_C_PORT_SUSPEND): WR_RH_PORTSTAT(RH_PS_PSSC); OK(0);
1331 case (RH_C_PORT_OVER_CURRENT):WR_RH_PORTSTAT(RH_PS_OCIC); OK(0);
1332 case (RH_C_PORT_RESET): WR_RH_PORTSTAT(RH_PS_PRSC); OK(0);
1333 }
1334 break;
1335
1336 case RH_SET_FEATURE | RH_OTHER | RH_CLASS:
1337 switch (wValue) {
1338 case (RH_PORT_SUSPEND):
1339 WR_RH_PORTSTAT(RH_PS_PSS); OK(0);
1340 case (RH_PORT_RESET): /* BUG IN HUP CODE *********/
1341 if (RD_RH_PORTSTAT & RH_PS_CCS)
1342 WR_RH_PORTSTAT(RH_PS_PRS);
1343 OK(0);
1344 case (RH_PORT_POWER):
1345 WR_RH_PORTSTAT(RH_PS_PPS);
1346 OK(0);
1347 case (RH_PORT_ENABLE): /* BUG IN HUP CODE *********/
1348 if (RD_RH_PORTSTAT & RH_PS_CCS)
1349 WR_RH_PORTSTAT(RH_PS_PES);
1350 OK(0);
1351 }
1352 break;
1353
1354 case RH_SET_ADDRESS:
1355 ohci->rh.devnum = wValue;
1356 OK(0);
1357
1358 case RH_GET_DESCRIPTOR:
1359 switch ((wValue & 0xff00) >> 8) {
1360 case (0x01): /* device descriptor */
1361 len = min_t(unsigned int,
1362 leni,
1363 min_t(unsigned int,
1364 sizeof(root_hub_dev_des),
1365 wLength));
1366 databuf = root_hub_dev_des; OK(len);
1367 case (0x02): /* configuration descriptor */
1368 len = min_t(unsigned int,
1369 leni,
1370 min_t(unsigned int,
1371 sizeof(root_hub_config_des),
1372 wLength));
1373 databuf = root_hub_config_des; OK(len);
1374 case (0x03): /* string descriptors */
1375 if (wValue == 0x0300) {
1376 len = min_t(unsigned int,
1377 leni,
1378 min_t(unsigned int,
1379 sizeof(root_hub_str_index0),
1380 wLength));
1381 databuf = root_hub_str_index0;
1382 OK(len);
1383 }
1384 if (wValue == 0x0301) {
1385 len = min_t(unsigned int,
1386 leni,
1387 min_t(unsigned int,
1388 sizeof(root_hub_str_index1),
1389 wLength));
1390 databuf = root_hub_str_index1;
1391 OK(len);
1392 }
1393 default:
1394 stat = USB_ST_STALLED;
1395 }
1396 break;
1397
1398 case RH_GET_DESCRIPTOR | RH_CLASS:
1399 {
1400 __u32 temp = roothub_a(ohci);
1401
1402 databuf[0] = 9; /* min length; */
1403 databuf[1] = 0x29;
1404 databuf[2] = temp & RH_A_NDP;
1405 #ifdef CONFIG_AT91C_PQFP_UHPBUG
1406 databuf[2] = (databuf[2] == 2) ? 1 : 0;
1407 #endif
1408 databuf[3] = 0;
1409 if (temp & RH_A_PSM) /* per-port power switching? */
1410 databuf[3] |= 0x1;
1411 if (temp & RH_A_NOCP) /* no overcurrent reporting? */
1412 databuf[3] |= 0x10;
1413 else if (temp & RH_A_OCPM)/* per-port overcurrent reporting? */
1414 databuf[3] |= 0x8;
1415
1416 databuf[4] = 0;
1417 databuf[5] = (temp & RH_A_POTPGT) >> 24;
1418 databuf[6] = 0;
1419 temp = roothub_b(ohci);
1420 databuf[7] = temp & RH_B_DR;
1421 if (databuf[2] < 7) {
1422 databuf[8] = 0xff;
1423 } else {
1424 databuf[0] += 2;
1425 databuf[8] = (temp & RH_B_DR) >> 8;
1426 databuf[10] = databuf[9] = 0xff;
1427 }
1428
1429 len = min_t(unsigned int, leni,
1430 min_t(unsigned int, databuf[0], wLength));
1431 OK(len);
1432 }
1433
1434 case RH_GET_CONFIGURATION:
1435 databuf[0] = 0x01;
1436 OK(1);
1437
1438 case RH_SET_CONFIGURATION:
1439 WR_RH_STAT(0x10000);
1440 OK(0);
1441
1442 default:
1443 dbg("unsupported root hub command");
1444 stat = USB_ST_STALLED;
1445 }
1446
1447 #ifdef DEBUG
1448 ohci_dump_roothub(ohci, 1);
1449 #else
1450 ohci_mdelay(1);
1451 #endif
1452
1453 len = min_t(int, len, leni);
1454 if (data != databuf)
1455 memcpy(data, databuf, len);
1456 dev->act_len = len;
1457 dev->status = stat;
1458
1459 #ifdef DEBUG
1460 pkt_print(ohci, NULL, dev, pipe, buffer,
1461 transfer_len, cmd, "RET(rh)", 0/*usb_pipein(pipe)*/);
1462 #else
1463 ohci_mdelay(1);
1464 #endif
1465
1466 return stat;
1467 }
1468
1469 /*-------------------------------------------------------------------------*/
1470
ohci_get_ohci_dev(ohci_t * ohci,int devnum,int intr)1471 static ohci_dev_t *ohci_get_ohci_dev(ohci_t *ohci, int devnum, int intr)
1472 {
1473 int i;
1474
1475 if (!intr)
1476 return &ohci->ohci_dev;
1477
1478 /* First see if we already have an ohci_dev for this dev. */
1479 for (i = 0; i < NUM_INT_DEVS; i++) {
1480 if (ohci->int_dev[i].devnum == devnum)
1481 return &ohci->int_dev[i];
1482 }
1483
1484 /* If not then find a free one. */
1485 for (i = 0; i < NUM_INT_DEVS; i++) {
1486 if (ohci->int_dev[i].devnum == -1) {
1487 ohci->int_dev[i].devnum = devnum;
1488 return &ohci->int_dev[i];
1489 }
1490 }
1491
1492 printf("ohci: Error out of ohci_devs for interrupt endpoints\n");
1493 return NULL;
1494 }
1495
1496 /* common code for handling submit messages - used for all but root hub */
1497 /* accesses. */
ohci_alloc_urb(struct usb_device * dev,unsigned long pipe,void * buffer,int transfer_len,int interval)1498 static urb_priv_t *ohci_alloc_urb(struct usb_device *dev, unsigned long pipe,
1499 void *buffer, int transfer_len, int interval)
1500 {
1501 urb_priv_t *urb;
1502
1503 urb = calloc(1, sizeof(urb_priv_t));
1504 if (!urb) {
1505 printf("ohci: Error out of memory allocating urb\n");
1506 return NULL;
1507 }
1508
1509 urb->dev = dev;
1510 urb->pipe = pipe;
1511 urb->transfer_buffer = buffer;
1512 urb->transfer_buffer_length = transfer_len;
1513 urb->interval = interval;
1514
1515 return urb;
1516 }
1517
submit_common_msg(ohci_t * ohci,struct usb_device * dev,unsigned long pipe,void * buffer,int transfer_len,struct devrequest * setup,int interval)1518 static int submit_common_msg(ohci_t *ohci, struct usb_device *dev,
1519 unsigned long pipe, void *buffer, int transfer_len,
1520 struct devrequest *setup, int interval)
1521 {
1522 int stat = 0;
1523 int maxsize = usb_maxpacket(dev, pipe);
1524 int timeout;
1525 urb_priv_t *urb;
1526 ohci_dev_t *ohci_dev;
1527
1528 urb = ohci_alloc_urb(dev, pipe, buffer, transfer_len, interval);
1529 if (!urb)
1530 return -ENOMEM;
1531
1532 #ifdef DEBUG
1533 urb->actual_length = 0;
1534 pkt_print(ohci, urb, dev, pipe, buffer, transfer_len,
1535 setup, "SUB", usb_pipein(pipe));
1536 #else
1537 ohci_mdelay(1);
1538 #endif
1539 if (!maxsize) {
1540 err("submit_common_message: pipesize for pipe %lx is zero",
1541 pipe);
1542 return -1;
1543 }
1544
1545 ohci_dev = ohci_get_ohci_dev(ohci, dev->devnum, usb_pipeint(pipe));
1546 if (!ohci_dev)
1547 return -ENOMEM;
1548
1549 if (sohci_submit_job(ohci, ohci_dev, urb, setup) < 0) {
1550 err("sohci_submit_job failed");
1551 return -1;
1552 }
1553
1554 mdelay(10);
1555 /* ohci_dump_status(ohci); */
1556
1557 timeout = USB_TIMEOUT_MS(pipe);
1558
1559 /* wait for it to complete */
1560 for (;;) {
1561 /* check whether the controller is done */
1562 stat = hc_interrupt(ohci);
1563 if (stat < 0) {
1564 stat = USB_ST_CRC_ERR;
1565 break;
1566 }
1567
1568 /* NOTE: since we are not interrupt driven in U-Boot and always
1569 * handle only one URB at a time, we cannot assume the
1570 * transaction finished on the first successful return from
1571 * hc_interrupt().. unless the flag for current URB is set,
1572 * meaning that all TD's to/from device got actually
1573 * transferred and processed. If the current URB is not
1574 * finished we need to re-iterate this loop so as
1575 * hc_interrupt() gets called again as there needs to be some
1576 * more TD's to process still */
1577 if ((stat >= 0) && (stat != 0xff) && (urb->finished)) {
1578 /* 0xff is returned for an SF-interrupt */
1579 break;
1580 }
1581
1582 if (--timeout) {
1583 mdelay(1);
1584 if (!urb->finished)
1585 dbg("*");
1586
1587 } else {
1588 if (!usb_pipeint(pipe))
1589 err("CTL:TIMEOUT ");
1590 dbg("submit_common_msg: TO status %x\n", stat);
1591 urb->finished = 1;
1592 stat = USB_ST_CRC_ERR;
1593 break;
1594 }
1595 }
1596
1597 dev->status = stat;
1598 dev->act_len = urb->actual_length;
1599
1600 if (usb_pipein(pipe) && dev->status == 0 && dev->act_len)
1601 invalidate_dcache_buffer(buffer, dev->act_len);
1602
1603 #ifdef DEBUG
1604 pkt_print(ohci, urb, dev, pipe, buffer, transfer_len,
1605 setup, "RET(ctlr)", usb_pipein(pipe));
1606 #else
1607 ohci_mdelay(1);
1608 #endif
1609 urb_free_priv(urb);
1610 return 0;
1611 }
1612
1613 #define MAX_INT_QUEUESIZE 8
1614
1615 struct int_queue {
1616 int queuesize;
1617 int curr_urb;
1618 urb_priv_t *urb[MAX_INT_QUEUESIZE];
1619 };
1620
_ohci_create_int_queue(ohci_t * ohci,struct usb_device * udev,unsigned long pipe,int queuesize,int elementsize,void * buffer,int interval)1621 static struct int_queue *_ohci_create_int_queue(ohci_t *ohci,
1622 struct usb_device *udev, unsigned long pipe, int queuesize,
1623 int elementsize, void *buffer, int interval)
1624 {
1625 struct int_queue *queue;
1626 ohci_dev_t *ohci_dev;
1627 int i;
1628
1629 if (queuesize > MAX_INT_QUEUESIZE)
1630 return NULL;
1631
1632 ohci_dev = ohci_get_ohci_dev(ohci, udev->devnum, 1);
1633 if (!ohci_dev)
1634 return NULL;
1635
1636 queue = malloc(sizeof(*queue));
1637 if (!queue) {
1638 printf("ohci: Error out of memory allocating int queue\n");
1639 return NULL;
1640 }
1641
1642 for (i = 0; i < queuesize; i++) {
1643 queue->urb[i] = ohci_alloc_urb(udev, pipe,
1644 buffer + i * elementsize,
1645 elementsize, interval);
1646 if (!queue->urb[i])
1647 break;
1648
1649 if (sohci_submit_job(ohci, ohci_dev, queue->urb[i], NULL)) {
1650 printf("ohci: Error submitting int queue job\n");
1651 urb_free_priv(queue->urb[i]);
1652 break;
1653 }
1654 }
1655 if (i == 0) {
1656 /* We did not succeed in submitting even 1 urb */
1657 free(queue);
1658 return NULL;
1659 }
1660
1661 queue->queuesize = i;
1662 queue->curr_urb = 0;
1663
1664 return queue;
1665 }
1666
_ohci_poll_int_queue(ohci_t * ohci,struct usb_device * udev,struct int_queue * queue)1667 static void *_ohci_poll_int_queue(ohci_t *ohci, struct usb_device *udev,
1668 struct int_queue *queue)
1669 {
1670 if (queue->curr_urb == queue->queuesize)
1671 return NULL; /* Queue depleted */
1672
1673 if (hc_interrupt(ohci) < 0)
1674 return NULL;
1675
1676 if (queue->urb[queue->curr_urb]->finished) {
1677 void *ret = queue->urb[queue->curr_urb]->transfer_buffer;
1678 queue->curr_urb++;
1679 return ret;
1680 }
1681
1682 return NULL;
1683 }
1684
_ohci_destroy_int_queue(ohci_t * ohci,struct usb_device * dev,struct int_queue * queue)1685 static int _ohci_destroy_int_queue(ohci_t *ohci, struct usb_device *dev,
1686 struct int_queue *queue)
1687 {
1688 int i;
1689
1690 for (i = 0; i < queue->queuesize; i++)
1691 urb_free_priv(queue->urb[i]);
1692
1693 free(queue);
1694
1695 return 0;
1696 }
1697
1698 #if !CONFIG_IS_ENABLED(DM_USB)
1699 /* submit routines called from usb.c */
submit_bulk_msg(struct usb_device * dev,unsigned long pipe,void * buffer,int transfer_len)1700 int submit_bulk_msg(struct usb_device *dev, unsigned long pipe, void *buffer,
1701 int transfer_len)
1702 {
1703 info("submit_bulk_msg");
1704 return submit_common_msg(&gohci, dev, pipe, buffer, transfer_len,
1705 NULL, 0);
1706 }
1707
submit_int_msg(struct usb_device * dev,unsigned long pipe,void * buffer,int transfer_len,int interval,bool nonblock)1708 int submit_int_msg(struct usb_device *dev, unsigned long pipe, void *buffer,
1709 int transfer_len, int interval, bool nonblock)
1710 {
1711 info("submit_int_msg");
1712 return submit_common_msg(&gohci, dev, pipe, buffer, transfer_len, NULL,
1713 interval);
1714 }
1715
create_int_queue(struct usb_device * dev,unsigned long pipe,int queuesize,int elementsize,void * buffer,int interval)1716 struct int_queue *create_int_queue(struct usb_device *dev,
1717 unsigned long pipe, int queuesize, int elementsize,
1718 void *buffer, int interval)
1719 {
1720 return _ohci_create_int_queue(&gohci, dev, pipe, queuesize,
1721 elementsize, buffer, interval);
1722 }
1723
poll_int_queue(struct usb_device * dev,struct int_queue * queue)1724 void *poll_int_queue(struct usb_device *dev, struct int_queue *queue)
1725 {
1726 return _ohci_poll_int_queue(&gohci, dev, queue);
1727 }
1728
destroy_int_queue(struct usb_device * dev,struct int_queue * queue)1729 int destroy_int_queue(struct usb_device *dev, struct int_queue *queue)
1730 {
1731 return _ohci_destroy_int_queue(&gohci, dev, queue);
1732 }
1733 #endif
1734
_ohci_submit_control_msg(ohci_t * ohci,struct usb_device * dev,unsigned long pipe,void * buffer,int transfer_len,struct devrequest * setup)1735 static int _ohci_submit_control_msg(ohci_t *ohci, struct usb_device *dev,
1736 unsigned long pipe, void *buffer, int transfer_len,
1737 struct devrequest *setup)
1738 {
1739 int maxsize = usb_maxpacket(dev, pipe);
1740
1741 info("submit_control_msg");
1742 #ifdef DEBUG
1743 pkt_print(ohci, NULL, dev, pipe, buffer, transfer_len,
1744 setup, "SUB", usb_pipein(pipe));
1745 #else
1746 ohci_mdelay(1);
1747 #endif
1748 if (!maxsize) {
1749 err("submit_control_message: pipesize for pipe %lx is zero",
1750 pipe);
1751 return -1;
1752 }
1753 if (((pipe >> 8) & 0x7f) == ohci->rh.devnum) {
1754 ohci->rh.dev = dev;
1755 /* root hub - redirect */
1756 return ohci_submit_rh_msg(ohci, dev, pipe, buffer,
1757 transfer_len, setup);
1758 }
1759
1760 return submit_common_msg(ohci, dev, pipe, buffer, transfer_len,
1761 setup, 0);
1762 }
1763
1764 /*-------------------------------------------------------------------------*
1765 * HC functions
1766 *-------------------------------------------------------------------------*/
1767
1768 /* reset the HC and BUS */
1769
hc_reset(ohci_t * ohci)1770 static int hc_reset(ohci_t *ohci)
1771 {
1772 #ifdef CONFIG_PCI_EHCI_DEVNO
1773 pci_dev_t pdev;
1774 #endif
1775 int timeout = 30;
1776 int smm_timeout = 50; /* 0,5 sec */
1777
1778 dbg("%s\n", __FUNCTION__);
1779
1780 #ifdef CONFIG_PCI_EHCI_DEVNO
1781 /*
1782 * Some multi-function controllers (e.g. ISP1562) allow root hub
1783 * resetting via EHCI registers only.
1784 */
1785 pdev = pci_find_devices(ehci_pci_ids, CONFIG_PCI_EHCI_DEVNO);
1786 if (pdev != -1) {
1787 u32 base;
1788 int timeout = 1000;
1789
1790 pci_read_config_dword(pdev, PCI_BASE_ADDRESS_0, &base);
1791 base += EHCI_USBCMD_OFF;
1792 ohci_writel(ohci_readl(base) | EHCI_USBCMD_HCRESET, base);
1793
1794 while (ohci_readl(base) & EHCI_USBCMD_HCRESET) {
1795 if (timeout-- <= 0) {
1796 printf("USB RootHub reset timed out!");
1797 break;
1798 }
1799 udelay(1);
1800 }
1801 } else
1802 printf("No EHCI func at %d index!\n", CONFIG_PCI_EHCI_DEVNO);
1803 #endif
1804 if (ohci_readl(&ohci->regs->control) & OHCI_CTRL_IR) {
1805 /* SMM owns the HC, request ownership */
1806 ohci_writel(OHCI_OCR, &ohci->regs->cmdstatus);
1807 info("USB HC TakeOver from SMM");
1808 while (ohci_readl(&ohci->regs->control) & OHCI_CTRL_IR) {
1809 mdelay(10);
1810 if (--smm_timeout == 0) {
1811 err("USB HC TakeOver failed!");
1812 return -1;
1813 }
1814 }
1815 }
1816
1817 /* Disable HC interrupts */
1818 ohci_writel(OHCI_INTR_MIE, &ohci->regs->intrdisable);
1819
1820 dbg("USB HC reset_hc usb-%s: ctrl = 0x%X ;\n",
1821 ohci->slot_name,
1822 ohci_readl(&ohci->regs->control));
1823
1824 /* Reset USB (needed by some controllers) */
1825 ohci->hc_control = 0;
1826 ohci_writel(ohci->hc_control, &ohci->regs->control);
1827
1828 /* HC Reset requires max 10 us delay */
1829 ohci_writel(OHCI_HCR, &ohci->regs->cmdstatus);
1830 while ((ohci_readl(&ohci->regs->cmdstatus) & OHCI_HCR) != 0) {
1831 if (--timeout == 0) {
1832 err("USB HC reset timed out!");
1833 return -1;
1834 }
1835 udelay(1);
1836 }
1837 return 0;
1838 }
1839
1840 /*-------------------------------------------------------------------------*/
1841
1842 /* Start an OHCI controller, set the BUS operational
1843 * enable interrupts
1844 * connect the virtual root hub */
1845
hc_start(ohci_t * ohci)1846 static int hc_start(ohci_t *ohci)
1847 {
1848 __u32 mask;
1849 unsigned int fminterval;
1850 int i;
1851
1852 ohci->disabled = 1;
1853 for (i = 0; i < NUM_INT_DEVS; i++)
1854 ohci->int_dev[i].devnum = -1;
1855
1856 /* Tell the controller where the control and bulk lists are
1857 * The lists are empty now. */
1858
1859 ohci_writel(0, &ohci->regs->ed_controlhead);
1860 ohci_writel(0, &ohci->regs->ed_bulkhead);
1861
1862 ohci_writel((uintptr_t)ohci->hcca,
1863 &ohci->regs->hcca); /* reset clears this */
1864
1865 fminterval = 0x2edf;
1866 ohci_writel((fminterval * 9) / 10, &ohci->regs->periodicstart);
1867 fminterval |= ((((fminterval - 210) * 6) / 7) << 16);
1868 ohci_writel(fminterval, &ohci->regs->fminterval);
1869 ohci_writel(0x628, &ohci->regs->lsthresh);
1870
1871 /* start controller operations */
1872 ohci->hc_control = OHCI_CONTROL_INIT | OHCI_USB_OPER;
1873 ohci->disabled = 0;
1874 ohci_writel(ohci->hc_control, &ohci->regs->control);
1875
1876 /* disable all interrupts */
1877 mask = (OHCI_INTR_SO | OHCI_INTR_WDH | OHCI_INTR_SF | OHCI_INTR_RD |
1878 OHCI_INTR_UE | OHCI_INTR_FNO | OHCI_INTR_RHSC |
1879 OHCI_INTR_OC | OHCI_INTR_MIE);
1880 ohci_writel(mask, &ohci->regs->intrdisable);
1881 /* clear all interrupts */
1882 mask &= ~OHCI_INTR_MIE;
1883 ohci_writel(mask, &ohci->regs->intrstatus);
1884 /* Choose the interrupts we care about now - but w/o MIE */
1885 mask = OHCI_INTR_RHSC | OHCI_INTR_UE | OHCI_INTR_WDH | OHCI_INTR_SO;
1886 ohci_writel(mask, &ohci->regs->intrenable);
1887
1888 #ifdef OHCI_USE_NPS
1889 /* required for AMD-756 and some Mac platforms */
1890 ohci_writel((roothub_a(ohci) | RH_A_NPS) & ~RH_A_PSM,
1891 &ohci->regs->roothub.a);
1892 ohci_writel(RH_HS_LPSC, &ohci->regs->roothub.status);
1893 #endif /* OHCI_USE_NPS */
1894
1895 /* connect the virtual root hub */
1896 ohci->rh.devnum = 0;
1897
1898 return 0;
1899 }
1900
1901 /*-------------------------------------------------------------------------*/
1902
1903 /* an interrupt happens */
1904
hc_interrupt(ohci_t * ohci)1905 static int hc_interrupt(ohci_t *ohci)
1906 {
1907 struct ohci_regs *regs = ohci->regs;
1908 int ints;
1909 int stat = -1;
1910
1911 invalidate_dcache_hcca(ohci->hcca);
1912
1913 if ((ohci->hcca->done_head != 0) &&
1914 !(m32_swap(ohci->hcca->done_head) & 0x01)) {
1915 ints = OHCI_INTR_WDH;
1916 } else {
1917 ints = ohci_readl(®s->intrstatus);
1918 if (ints == ~(u32)0) {
1919 ohci->disabled++;
1920 err("%s device removed!", ohci->slot_name);
1921 return -1;
1922 } else {
1923 ints &= ohci_readl(®s->intrenable);
1924 if (ints == 0) {
1925 dbg("hc_interrupt: returning..\n");
1926 return 0xff;
1927 }
1928 }
1929 }
1930
1931 /* dbg("Interrupt: %x frame: %x", ints,
1932 le16_to_cpu(ohci->hcca->frame_no)); */
1933
1934 if (ints & OHCI_INTR_RHSC)
1935 stat = 0xff;
1936
1937 if (ints & OHCI_INTR_UE) {
1938 ohci->disabled++;
1939 err("OHCI Unrecoverable Error, controller usb-%s disabled",
1940 ohci->slot_name);
1941 /* e.g. due to PCI Master/Target Abort */
1942
1943 #ifdef DEBUG
1944 ohci_dump(ohci, 1);
1945 #else
1946 ohci_mdelay(1);
1947 #endif
1948 /* FIXME: be optimistic, hope that bug won't repeat often. */
1949 /* Make some non-interrupt context restart the controller. */
1950 /* Count and limit the retries though; either hardware or */
1951 /* software errors can go forever... */
1952 hc_reset(ohci);
1953 return -1;
1954 }
1955
1956 if (ints & OHCI_INTR_WDH) {
1957 ohci_mdelay(1);
1958 ohci_writel(OHCI_INTR_WDH, ®s->intrdisable);
1959 (void)ohci_readl(®s->intrdisable); /* flush */
1960 stat = dl_done_list(ohci);
1961 ohci_writel(OHCI_INTR_WDH, ®s->intrenable);
1962 (void)ohci_readl(®s->intrdisable); /* flush */
1963 }
1964
1965 if (ints & OHCI_INTR_SO) {
1966 dbg("USB Schedule overrun\n");
1967 ohci_writel(OHCI_INTR_SO, ®s->intrenable);
1968 stat = -1;
1969 }
1970
1971 /* FIXME: this assumes SOF (1/ms) interrupts don't get lost... */
1972 if (ints & OHCI_INTR_SF) {
1973 unsigned int frame = m16_swap(ohci->hcca->frame_no) & 1;
1974 mdelay(1);
1975 ohci_writel(OHCI_INTR_SF, ®s->intrdisable);
1976 if (ohci->ed_rm_list[frame] != NULL)
1977 ohci_writel(OHCI_INTR_SF, ®s->intrenable);
1978 stat = 0xff;
1979 }
1980
1981 ohci_writel(ints, ®s->intrstatus);
1982 return stat;
1983 }
1984
1985 /*-------------------------------------------------------------------------*/
1986
1987 #if !CONFIG_IS_ENABLED(DM_USB)
1988
1989 /*-------------------------------------------------------------------------*/
1990
1991 /* De-allocate all resources.. */
1992
hc_release_ohci(ohci_t * ohci)1993 static void hc_release_ohci(ohci_t *ohci)
1994 {
1995 dbg("USB HC release ohci usb-%s", ohci->slot_name);
1996
1997 if (!ohci->disabled)
1998 hc_reset(ohci);
1999 }
2000
2001 /*-------------------------------------------------------------------------*/
2002
2003 /*
2004 * low level initalisation routine, called from usb.c
2005 */
2006 static char ohci_inited = 0;
2007
usb_lowlevel_init(int index,enum usb_init_type init,void ** controller)2008 int usb_lowlevel_init(int index, enum usb_init_type init, void **controller)
2009 {
2010 #ifdef CONFIG_PCI_OHCI
2011 pci_dev_t pdev;
2012 #endif
2013
2014 #ifdef CONFIG_SYS_USB_OHCI_CPU_INIT
2015 /* cpu dependant init */
2016 if (usb_cpu_init())
2017 return -1;
2018 #endif
2019
2020 #ifdef CONFIG_SYS_USB_OHCI_BOARD_INIT
2021 /* board dependant init */
2022 if (board_usb_init(index, USB_INIT_HOST))
2023 return -1;
2024 #endif
2025 memset(&gohci, 0, sizeof(ohci_t));
2026
2027 /* align the storage */
2028 if ((__u32)&ghcca[0] & 0xff) {
2029 err("HCCA not aligned!!");
2030 return -1;
2031 }
2032 gohci.hcca = &ghcca[0];
2033 info("aligned ghcca %p", gohci.hcca);
2034 memset(gohci.hcca, 0, sizeof(struct ohci_hcca));
2035
2036 gohci.disabled = 1;
2037 gohci.sleeping = 0;
2038 gohci.irq = -1;
2039 #ifdef CONFIG_PCI_OHCI
2040 pdev = pci_find_devices(ohci_pci_ids, CONFIG_PCI_OHCI_DEVNO);
2041
2042 if (pdev != -1) {
2043 u16 vid, did;
2044 u32 base;
2045 pci_read_config_word(pdev, PCI_VENDOR_ID, &vid);
2046 pci_read_config_word(pdev, PCI_DEVICE_ID, &did);
2047 printf("OHCI pci controller (%04x, %04x) found @(%d:%d:%d)\n",
2048 vid, did, (pdev >> 16) & 0xff,
2049 (pdev >> 11) & 0x1f, (pdev >> 8) & 0x7);
2050 pci_read_config_dword(pdev, PCI_BASE_ADDRESS_0, &base);
2051 printf("OHCI regs address 0x%08x\n", base);
2052 gohci.regs = (struct ohci_regs *)base;
2053 } else {
2054 printf("%s: OHCI devnr: %d not found\n", __func__,
2055 CONFIG_PCI_OHCI_DEVNO);
2056 return -1;
2057 }
2058 #else
2059 gohci.regs = (struct ohci_regs *)CONFIG_SYS_USB_OHCI_REGS_BASE;
2060 #endif
2061
2062 gohci.flags = 0;
2063 gohci.slot_name = CONFIG_SYS_USB_OHCI_SLOT_NAME;
2064
2065 if (hc_reset (&gohci) < 0) {
2066 hc_release_ohci (&gohci);
2067 err ("can't reset usb-%s", gohci.slot_name);
2068 #ifdef CONFIG_SYS_USB_OHCI_BOARD_INIT
2069 /* board dependant cleanup */
2070 board_usb_cleanup(index, USB_INIT_HOST);
2071 #endif
2072
2073 #ifdef CONFIG_SYS_USB_OHCI_CPU_INIT
2074 /* cpu dependant cleanup */
2075 usb_cpu_init_fail();
2076 #endif
2077 return -1;
2078 }
2079
2080 if (hc_start(&gohci) < 0) {
2081 err("can't start usb-%s", gohci.slot_name);
2082 hc_release_ohci(&gohci);
2083 /* Initialization failed */
2084 #ifdef CONFIG_SYS_USB_OHCI_BOARD_INIT
2085 /* board dependant cleanup */
2086 usb_board_stop();
2087 #endif
2088
2089 #ifdef CONFIG_SYS_USB_OHCI_CPU_INIT
2090 /* cpu dependant cleanup */
2091 usb_cpu_stop();
2092 #endif
2093 return -1;
2094 }
2095
2096 #ifdef DEBUG
2097 ohci_dump(&gohci, 1);
2098 #else
2099 ohci_mdelay(1);
2100 #endif
2101 ohci_inited = 1;
2102 return 0;
2103 }
2104
usb_lowlevel_stop(int index)2105 int usb_lowlevel_stop(int index)
2106 {
2107 /* this gets called really early - before the controller has */
2108 /* even been initialized! */
2109 if (!ohci_inited)
2110 return 0;
2111 /* TODO release any interrupts, etc. */
2112 /* call hc_release_ohci() here ? */
2113 hc_reset(&gohci);
2114
2115 #ifdef CONFIG_SYS_USB_OHCI_BOARD_INIT
2116 /* board dependant cleanup */
2117 if (usb_board_stop())
2118 return -1;
2119 #endif
2120
2121 #ifdef CONFIG_SYS_USB_OHCI_CPU_INIT
2122 /* cpu dependant cleanup */
2123 if (usb_cpu_stop())
2124 return -1;
2125 #endif
2126 /* This driver is no longer initialised. It needs a new low-level
2127 * init (board/cpu) before it can be used again. */
2128 ohci_inited = 0;
2129 return 0;
2130 }
2131
submit_control_msg(struct usb_device * dev,unsigned long pipe,void * buffer,int transfer_len,struct devrequest * setup)2132 int submit_control_msg(struct usb_device *dev, unsigned long pipe,
2133 void *buffer, int transfer_len, struct devrequest *setup)
2134 {
2135 return _ohci_submit_control_msg(&gohci, dev, pipe, buffer,
2136 transfer_len, setup);
2137 }
2138 #endif
2139
2140 #if CONFIG_IS_ENABLED(DM_USB)
ohci_submit_control_msg(struct udevice * dev,struct usb_device * udev,unsigned long pipe,void * buffer,int length,struct devrequest * setup)2141 static int ohci_submit_control_msg(struct udevice *dev, struct usb_device *udev,
2142 unsigned long pipe, void *buffer, int length,
2143 struct devrequest *setup)
2144 {
2145 ohci_t *ohci = dev_get_priv(usb_get_bus(dev));
2146
2147 return _ohci_submit_control_msg(ohci, udev, pipe, buffer,
2148 length, setup);
2149 }
2150
ohci_submit_bulk_msg(struct udevice * dev,struct usb_device * udev,unsigned long pipe,void * buffer,int length)2151 static int ohci_submit_bulk_msg(struct udevice *dev, struct usb_device *udev,
2152 unsigned long pipe, void *buffer, int length)
2153 {
2154 ohci_t *ohci = dev_get_priv(usb_get_bus(dev));
2155
2156 return submit_common_msg(ohci, udev, pipe, buffer, length, NULL, 0);
2157 }
2158
ohci_submit_int_msg(struct udevice * dev,struct usb_device * udev,unsigned long pipe,void * buffer,int length,int interval,bool nonblock)2159 static int ohci_submit_int_msg(struct udevice *dev, struct usb_device *udev,
2160 unsigned long pipe, void *buffer, int length,
2161 int interval, bool nonblock)
2162 {
2163 ohci_t *ohci = dev_get_priv(usb_get_bus(dev));
2164
2165 return submit_common_msg(ohci, udev, pipe, buffer, length,
2166 NULL, interval);
2167 }
2168
ohci_create_int_queue(struct udevice * dev,struct usb_device * udev,unsigned long pipe,int queuesize,int elementsize,void * buffer,int interval)2169 static struct int_queue *ohci_create_int_queue(struct udevice *dev,
2170 struct usb_device *udev, unsigned long pipe, int queuesize,
2171 int elementsize, void *buffer, int interval)
2172 {
2173 ohci_t *ohci = dev_get_priv(usb_get_bus(dev));
2174
2175 return _ohci_create_int_queue(ohci, udev, pipe, queuesize, elementsize,
2176 buffer, interval);
2177 }
2178
ohci_poll_int_queue(struct udevice * dev,struct usb_device * udev,struct int_queue * queue)2179 static void *ohci_poll_int_queue(struct udevice *dev, struct usb_device *udev,
2180 struct int_queue *queue)
2181 {
2182 ohci_t *ohci = dev_get_priv(usb_get_bus(dev));
2183
2184 return _ohci_poll_int_queue(ohci, udev, queue);
2185 }
2186
ohci_destroy_int_queue(struct udevice * dev,struct usb_device * udev,struct int_queue * queue)2187 static int ohci_destroy_int_queue(struct udevice *dev, struct usb_device *udev,
2188 struct int_queue *queue)
2189 {
2190 ohci_t *ohci = dev_get_priv(usb_get_bus(dev));
2191
2192 return _ohci_destroy_int_queue(ohci, udev, queue);
2193 }
2194
ohci_register(struct udevice * dev,struct ohci_regs * regs)2195 int ohci_register(struct udevice *dev, struct ohci_regs *regs)
2196 {
2197 struct usb_bus_priv *priv = dev_get_uclass_priv(dev);
2198 ohci_t *ohci = dev_get_priv(dev);
2199 u32 reg;
2200
2201 priv->desc_before_addr = true;
2202
2203 ohci->regs = regs;
2204 ohci->hcca = memalign(256, sizeof(struct ohci_hcca));
2205 if (!ohci->hcca)
2206 return -ENOMEM;
2207 memset(ohci->hcca, 0, sizeof(struct ohci_hcca));
2208 flush_dcache_hcca(ohci->hcca);
2209
2210 if (hc_reset(ohci) < 0)
2211 return -EIO;
2212
2213 if (hc_start(ohci) < 0)
2214 return -EIO;
2215
2216 reg = ohci_readl(®s->revision);
2217 printf("USB OHCI %x.%x\n", (reg >> 4) & 0xf, reg & 0xf);
2218
2219 return 0;
2220 }
2221
ohci_deregister(struct udevice * dev)2222 int ohci_deregister(struct udevice *dev)
2223 {
2224 ohci_t *ohci = dev_get_priv(dev);
2225
2226 if (hc_reset(ohci) < 0)
2227 return -EIO;
2228
2229 free(ohci->hcca);
2230
2231 return 0;
2232 }
2233
2234 struct dm_usb_ops ohci_usb_ops = {
2235 .control = ohci_submit_control_msg,
2236 .bulk = ohci_submit_bulk_msg,
2237 .interrupt = ohci_submit_int_msg,
2238 .create_int_queue = ohci_create_int_queue,
2239 .poll_int_queue = ohci_poll_int_queue,
2240 .destroy_int_queue = ohci_destroy_int_queue,
2241 };
2242
2243 #endif
2244