1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Copyright (c) 2019 MediaTek, Inc.
4 * Authors: Chunfeng Yun <chunfeng.yun@mediatek.com>
5 */
6
7 #include <clk.h>
8 #include <common.h>
9 #include <dm.h>
10 #include <dm/device_compat.h>
11 #include <dm/devres.h>
12 #include <generic-phy.h>
13 #include <malloc.h>
14 #include <power/regulator.h>
15 #include <usb.h>
16 #include <usb/xhci.h>
17 #include <linux/errno.h>
18 #include <linux/compat.h>
19 #include <linux/iopoll.h>
20
21 /* IPPC (IP Port Control) registers */
22 #define IPPC_IP_PW_CTRL0 0x00
23 #define CTRL0_IP_SW_RST BIT(0)
24
25 #define IPPC_IP_PW_CTRL1 0x04
26 #define CTRL1_IP_HOST_PDN BIT(0)
27
28 #define IPPC_IP_PW_STS1 0x10
29 #define STS1_IP_SLEEP_STS BIT(30)
30 #define STS1_U3_MAC_RST BIT(16)
31 #define STS1_XHCI_RST BIT(11)
32 #define STS1_SYS125_RST BIT(10)
33 #define STS1_REF_RST BIT(8)
34 #define STS1_SYSPLL_STABLE BIT(0)
35
36 #define IPPC_IP_XHCI_CAP 0x24
37 #define CAP_U3_PORT_NUM(p) ((p) & 0xff)
38 #define CAP_U2_PORT_NUM(p) (((p) >> 8) & 0xff)
39
40 #define IPPC_U3_CTRL_0P 0x30
41 #define CTRL_U3_PORT_HOST_SEL BIT(2)
42 #define CTRL_U3_PORT_PDN BIT(1)
43 #define CTRL_U3_PORT_DIS BIT(0)
44
45 #define IPPC_U2_CTRL_0P 0x50
46 #define CTRL_U2_PORT_HOST_SEL BIT(2)
47 #define CTRL_U2_PORT_PDN BIT(1)
48 #define CTRL_U2_PORT_DIS BIT(0)
49
50 #define IPPC_U3_CTRL(p) (IPPC_U3_CTRL_0P + ((p) * 0x08))
51 #define IPPC_U2_CTRL(p) (IPPC_U2_CTRL_0P + ((p) * 0x08))
52
53 struct mtk_xhci {
54 struct xhci_ctrl ctrl; /* Needs to come first in this struct! */
55 struct xhci_hccr *hcd;
56 void __iomem *ippc;
57 struct udevice *dev;
58 struct udevice *vusb33_supply;
59 struct udevice *vbus_supply;
60 struct clk_bulk clks;
61 struct phy_bulk phys;
62 int num_u2ports;
63 int num_u3ports;
64 u32 u3p_dis_msk;
65 u32 u2p_dis_msk;
66 };
67
xhci_mtk_host_enable(struct mtk_xhci * mtk)68 static int xhci_mtk_host_enable(struct mtk_xhci *mtk)
69 {
70 int u3_ports_disabed = 0;
71 u32 value;
72 u32 check_val;
73 int ret;
74 int i;
75
76 /* power on host ip */
77 clrbits_le32(mtk->ippc + IPPC_IP_PW_CTRL1, CTRL1_IP_HOST_PDN);
78
79 /* power on and enable u3 ports except skipped ones */
80 for (i = 0; i < mtk->num_u3ports; i++) {
81 if (BIT(i) & mtk->u3p_dis_msk) {
82 u3_ports_disabed++;
83 continue;
84 }
85
86 clrsetbits_le32(mtk->ippc + IPPC_U3_CTRL(i),
87 CTRL_U3_PORT_PDN | CTRL_U3_PORT_DIS,
88 CTRL_U3_PORT_HOST_SEL);
89 }
90
91 /* power on and enable u2 ports except skipped ones */
92 for (i = 0; i < mtk->num_u2ports; i++) {
93 if (BIT(i) & mtk->u2p_dis_msk)
94 continue;
95
96 clrsetbits_le32(mtk->ippc + IPPC_U2_CTRL(i),
97 CTRL_U2_PORT_PDN | CTRL_U2_PORT_DIS,
98 CTRL_U2_PORT_HOST_SEL);
99 }
100
101 /*
102 * wait for clocks to be stable, and clock domains reset to
103 * be inactive after power on and enable ports
104 */
105 check_val = STS1_SYSPLL_STABLE | STS1_REF_RST |
106 STS1_SYS125_RST | STS1_XHCI_RST;
107
108 if (mtk->num_u3ports > u3_ports_disabed)
109 check_val |= STS1_U3_MAC_RST;
110
111 ret = readl_poll_timeout(mtk->ippc + IPPC_IP_PW_STS1, value,
112 (check_val == (value & check_val)), 20000);
113 if (ret)
114 dev_err(mtk->dev, "clocks are not stable 0x%x!\n", value);
115
116 return ret;
117 }
118
xhci_mtk_host_disable(struct mtk_xhci * mtk)119 static int xhci_mtk_host_disable(struct mtk_xhci *mtk)
120 {
121 int i;
122
123 /* power down all u3 ports */
124 for (i = 0; i < mtk->num_u3ports; i++)
125 setbits_le32(mtk->ippc + IPPC_U3_CTRL(i), CTRL_U3_PORT_PDN);
126
127 /* power down all u2 ports */
128 for (i = 0; i < mtk->num_u2ports; i++)
129 setbits_le32(mtk->ippc + IPPC_U2_CTRL(i), CTRL_U2_PORT_PDN);
130
131 /* power down host ip */
132 setbits_le32(mtk->ippc + IPPC_IP_PW_CTRL1, CTRL1_IP_HOST_PDN);
133
134 return 0;
135 }
136
xhci_mtk_ssusb_init(struct mtk_xhci * mtk)137 static int xhci_mtk_ssusb_init(struct mtk_xhci *mtk)
138 {
139 u32 value;
140
141 /* reset whole ip */
142 setbits_le32(mtk->ippc + IPPC_IP_PW_CTRL0, CTRL0_IP_SW_RST);
143 udelay(1);
144 clrbits_le32(mtk->ippc + IPPC_IP_PW_CTRL0, CTRL0_IP_SW_RST);
145
146 value = readl(mtk->ippc + IPPC_IP_XHCI_CAP);
147 mtk->num_u3ports = CAP_U3_PORT_NUM(value);
148 mtk->num_u2ports = CAP_U2_PORT_NUM(value);
149 dev_info(mtk->dev, "u2p:%d, u3p:%d\n",
150 mtk->num_u2ports, mtk->num_u3ports);
151
152 return xhci_mtk_host_enable(mtk);
153 }
154
xhci_mtk_ofdata_get(struct mtk_xhci * mtk)155 static int xhci_mtk_ofdata_get(struct mtk_xhci *mtk)
156 {
157 struct udevice *dev = mtk->dev;
158 int ret = 0;
159
160 mtk->hcd = devfdt_remap_addr_name(dev, "mac");
161 if (!mtk->hcd) {
162 dev_err(dev, "failed to get xHCI base address\n");
163 return -ENXIO;
164 }
165
166 mtk->ippc = devfdt_remap_addr_name(dev, "ippc");
167 if (!mtk->ippc) {
168 dev_err(dev, "failed to get IPPC base address\n");
169 return -ENXIO;
170 }
171
172 dev_info(dev, "hcd: 0x%p, ippc: 0x%p\n", mtk->hcd, mtk->ippc);
173
174 ret = clk_get_bulk(dev, &mtk->clks);
175 if (ret) {
176 dev_err(dev, "failed to get clocks %d!\n", ret);
177 return ret;
178 }
179
180 ret = device_get_supply_regulator(dev, "vusb33-supply",
181 &mtk->vusb33_supply);
182 if (ret)
183 debug("can't get vusb33 regulator %d!\n", ret);
184
185 ret = device_get_supply_regulator(dev, "vbus-supply",
186 &mtk->vbus_supply);
187 if (ret)
188 debug("can't get vbus regulator %d!\n", ret);
189
190 /* optional properties to disable ports, ignore the error */
191 dev_read_u32(dev, "mediatek,u3p-dis-msk", &mtk->u3p_dis_msk);
192 dev_read_u32(dev, "mediatek,u2p-dis-msk", &mtk->u2p_dis_msk);
193 dev_info(dev, "ports disabled mask: u3p-0x%x, u2p-0x%x\n",
194 mtk->u3p_dis_msk, mtk->u2p_dis_msk);
195
196 return 0;
197 }
198
xhci_mtk_ldos_enable(struct mtk_xhci * mtk)199 static int xhci_mtk_ldos_enable(struct mtk_xhci *mtk)
200 {
201 int ret;
202
203 ret = regulator_set_enable(mtk->vusb33_supply, true);
204 if (ret < 0 && ret != -ENOSYS) {
205 dev_err(mtk->dev, "failed to enable vusb33 %d!\n", ret);
206 return ret;
207 }
208
209 ret = regulator_set_enable(mtk->vbus_supply, true);
210 if (ret < 0 && ret != -ENOSYS) {
211 dev_err(mtk->dev, "failed to enable vbus %d!\n", ret);
212 regulator_set_enable(mtk->vusb33_supply, false);
213 return ret;
214 }
215
216 return 0;
217 }
218
xhci_mtk_ldos_disable(struct mtk_xhci * mtk)219 static void xhci_mtk_ldos_disable(struct mtk_xhci *mtk)
220 {
221 regulator_set_enable(mtk->vbus_supply, false);
222 regulator_set_enable(mtk->vusb33_supply, false);
223 }
224
xhci_mtk_phy_setup(struct mtk_xhci * mtk)225 static int xhci_mtk_phy_setup(struct mtk_xhci *mtk)
226 {
227 struct udevice *dev = mtk->dev;
228 struct phy_bulk *phys = &mtk->phys;
229 int ret;
230
231 ret = generic_phy_get_bulk(dev, phys);
232 if (ret)
233 return ret;
234
235 ret = generic_phy_init_bulk(phys);
236 if (ret)
237 return ret;
238
239 ret = generic_phy_power_on_bulk(phys);
240 if (ret)
241 generic_phy_exit_bulk(phys);
242
243 return ret;
244 }
245
xhci_mtk_phy_shutdown(struct mtk_xhci * mtk)246 static void xhci_mtk_phy_shutdown(struct mtk_xhci *mtk)
247 {
248 generic_phy_power_off_bulk(&mtk->phys);
249 generic_phy_exit_bulk(&mtk->phys);
250 }
251
xhci_mtk_probe(struct udevice * dev)252 static int xhci_mtk_probe(struct udevice *dev)
253 {
254 struct mtk_xhci *mtk = dev_get_priv(dev);
255 struct xhci_hcor *hcor;
256 int ret;
257
258 mtk->dev = dev;
259 ret = xhci_mtk_ofdata_get(mtk);
260 if (ret)
261 return ret;
262
263 ret = xhci_mtk_ldos_enable(mtk);
264 if (ret)
265 goto ldos_err;
266
267 ret = clk_enable_bulk(&mtk->clks);
268 if (ret)
269 goto clks_err;
270
271 ret = xhci_mtk_phy_setup(mtk);
272 if (ret)
273 goto phys_err;
274
275 ret = xhci_mtk_ssusb_init(mtk);
276 if (ret)
277 goto ssusb_init_err;
278
279 mtk->ctrl.quirks = XHCI_MTK_HOST;
280 hcor = (struct xhci_hcor *)((uintptr_t)mtk->hcd +
281 HC_LENGTH(xhci_readl(&mtk->hcd->cr_capbase)));
282
283 return xhci_register(dev, mtk->hcd, hcor);
284
285 ssusb_init_err:
286 xhci_mtk_phy_shutdown(mtk);
287 phys_err:
288 clk_disable_bulk(&mtk->clks);
289 clks_err:
290 xhci_mtk_ldos_disable(mtk);
291 ldos_err:
292 return ret;
293 }
294
xhci_mtk_remove(struct udevice * dev)295 static int xhci_mtk_remove(struct udevice *dev)
296 {
297 struct mtk_xhci *mtk = dev_get_priv(dev);
298
299 xhci_deregister(dev);
300 xhci_mtk_host_disable(mtk);
301 xhci_mtk_ldos_disable(mtk);
302 clk_disable_bulk(&mtk->clks);
303
304 return 0;
305 }
306
307 static const struct udevice_id xhci_mtk_ids[] = {
308 { .compatible = "mediatek,mtk-xhci" },
309 { }
310 };
311
312 U_BOOT_DRIVER(usb_xhci) = {
313 .name = "xhci-mtk",
314 .id = UCLASS_USB,
315 .of_match = xhci_mtk_ids,
316 .probe = xhci_mtk_probe,
317 .remove = xhci_mtk_remove,
318 .ops = &xhci_usb_ops,
319 .bind = dm_scan_fdt_dev,
320 .priv_auto = sizeof(struct mtk_xhci),
321 .flags = DM_FLAG_ALLOC_PRIV_DMA,
322 };
323