1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * LPC32xx MLC NAND flash controller driver
4 *
5 * (C) Copyright 2014 3ADEV <http://3adev.com>
6 * Written by Albert ARIBAUD <albert.aribaud@3adev.fr>
7 *
8 * NOTE:
9 *
10 * The MLC NAND flash controller provides hardware Reed-Solomon ECC
11 * covering in- and out-of-band data together. Therefore, in- and out-
12 * of-band data must be written together in order to have a valid ECC.
13 *
14 * Consequently, pages with meaningful in-band data are written with
15 * blank (all-ones) out-of-band data and a valid ECC, and any later
16 * out-of-band data write will void the ECC.
17 *
18 * Therefore, code which reads such late-written out-of-band data
19 * should not rely on the ECC validity.
20 */
21
22 #include <common.h>
23 #include <nand.h>
24 #include <linux/delay.h>
25 #include <linux/errno.h>
26 #include <asm/io.h>
27 #include <nand.h>
28 #include <asm/arch/clk.h>
29 #include <asm/arch/sys_proto.h>
30
31 /*
32 * MLC NAND controller registers.
33 */
34 struct lpc32xx_nand_mlc_registers {
35 u8 buff[32768]; /* controller's serial data buffer */
36 u8 data[32768]; /* NAND's raw data buffer */
37 u32 cmd;
38 u32 addr;
39 u32 ecc_enc_reg;
40 u32 ecc_dec_reg;
41 u32 ecc_auto_enc_reg;
42 u32 ecc_auto_dec_reg;
43 u32 rpr;
44 u32 wpr;
45 u32 rubp;
46 u32 robp;
47 u32 sw_wp_add_low;
48 u32 sw_wp_add_hig;
49 u32 icr;
50 u32 time_reg;
51 u32 irq_mr;
52 u32 irq_sr;
53 u32 lock_pr;
54 u32 isr;
55 u32 ceh;
56 };
57
58 /* LOCK_PR register defines */
59 #define LOCK_PR_UNLOCK_KEY 0x0000A25E /* Magic unlock value */
60
61 /* ICR defines */
62 #define ICR_LARGE_BLOCKS 0x00000004 /* configure for 2KB blocks */
63 #define ICR_ADDR4 0x00000002 /* configure for 4-word addrs */
64
65 /* CEH defines */
66 #define CEH_NORMAL_CE 0x00000001 /* do not force CE ON */
67
68 /* ISR register defines */
69 #define ISR_NAND_READY 0x00000001
70 #define ISR_CONTROLLER_READY 0x00000002
71 #define ISR_ECC_READY 0x00000004
72 #define ISR_DECODER_ERRORS(s) ((((s) >> 4) & 3)+1)
73 #define ISR_DECODER_FAILURE 0x00000040
74 #define ISR_DECODER_ERROR 0x00000008
75
76 /* time-out for NAND chip / controller loops, in us */
77 #define LPC32X_NAND_TIMEOUT 5000
78
79 /*
80 * There is a single instance of the NAND MLC controller
81 */
82
83 static struct lpc32xx_nand_mlc_registers __iomem *lpc32xx_nand_mlc_registers
84 = (struct lpc32xx_nand_mlc_registers __iomem *)MLC_NAND_BASE;
85
86 #if !defined(CONFIG_SYS_MAX_NAND_CHIPS)
87 #define CONFIG_SYS_MAX_NAND_CHIPS 1
88 #endif
89
90 #define clkdiv(v, w, o) (((1+(clk/v)) & w) << o)
91
92 /**
93 * OOB data in each small page are 6 'free' then 10 ECC bytes.
94 * To make things easier, when reading large pages, the four pages'
95 * 'free' OOB bytes are grouped in the first 24 bytes of the OOB buffer,
96 * while the the four ECC bytes are groupe in its last 40 bytes.
97 *
98 * The struct below represents how free vs ecc oob bytes are stored
99 * in the buffer.
100 *
101 * Note: the OOB bytes contain the bad block marker at offsets 0 and 1.
102 */
103
104 struct lpc32xx_oob {
105 struct {
106 uint8_t free_oob_bytes[6];
107 } free[4];
108 struct {
109 uint8_t ecc_oob_bytes[10];
110 } ecc[4];
111 };
112
113 /*
114 * Initialize the controller
115 */
116
lpc32xx_nand_init(void)117 static void lpc32xx_nand_init(void)
118 {
119 unsigned int clk;
120
121 /* Configure controller for no software write protection, x8 bus
122 width, large block device, and 4 address words */
123
124 /* unlock controller registers with magic key */
125 writel(LOCK_PR_UNLOCK_KEY,
126 &lpc32xx_nand_mlc_registers->lock_pr);
127
128 /* enable large blocks and large NANDs */
129 writel(ICR_LARGE_BLOCKS | ICR_ADDR4,
130 &lpc32xx_nand_mlc_registers->icr);
131
132 /* Make sure MLC interrupts are disabled */
133 writel(0, &lpc32xx_nand_mlc_registers->irq_mr);
134
135 /* Normal chip enable operation */
136 writel(CEH_NORMAL_CE,
137 &lpc32xx_nand_mlc_registers->ceh);
138
139 /* Setup NAND timing */
140 clk = get_hclk_clk_rate();
141
142 writel(
143 clkdiv(CONFIG_LPC32XX_NAND_MLC_TCEA_DELAY, 0x03, 24) |
144 clkdiv(CONFIG_LPC32XX_NAND_MLC_BUSY_DELAY, 0x1F, 19) |
145 clkdiv(CONFIG_LPC32XX_NAND_MLC_NAND_TA, 0x07, 16) |
146 clkdiv(CONFIG_LPC32XX_NAND_MLC_RD_HIGH, 0x0F, 12) |
147 clkdiv(CONFIG_LPC32XX_NAND_MLC_RD_LOW, 0x0F, 8) |
148 clkdiv(CONFIG_LPC32XX_NAND_MLC_WR_HIGH, 0x0F, 4) |
149 clkdiv(CONFIG_LPC32XX_NAND_MLC_WR_LOW, 0x0F, 0),
150 &lpc32xx_nand_mlc_registers->time_reg);
151 }
152
153 #if !defined(CONFIG_SPL_BUILD)
154
155 /**
156 * lpc32xx_cmd_ctrl - write command to either cmd or data register
157 */
158
lpc32xx_cmd_ctrl(struct mtd_info * mtd,int cmd,unsigned int ctrl)159 static void lpc32xx_cmd_ctrl(struct mtd_info *mtd, int cmd,
160 unsigned int ctrl)
161 {
162 if (cmd == NAND_CMD_NONE)
163 return;
164
165 if (ctrl & NAND_CLE)
166 writeb(cmd & 0Xff, &lpc32xx_nand_mlc_registers->cmd);
167 else if (ctrl & NAND_ALE)
168 writeb(cmd & 0Xff, &lpc32xx_nand_mlc_registers->addr);
169 }
170
171 /**
172 * lpc32xx_read_byte - read a byte from the NAND
173 * @mtd: MTD device structure
174 */
175
lpc32xx_read_byte(struct mtd_info * mtd)176 static uint8_t lpc32xx_read_byte(struct mtd_info *mtd)
177 {
178 return readb(&lpc32xx_nand_mlc_registers->data);
179 }
180
181 /**
182 * lpc32xx_dev_ready - test if NAND device (actually controller) is ready
183 * @mtd: MTD device structure
184 * @mode: mode to set the ECC HW to.
185 */
186
lpc32xx_dev_ready(struct mtd_info * mtd)187 static int lpc32xx_dev_ready(struct mtd_info *mtd)
188 {
189 /* means *controller* ready for us */
190 int status = readl(&lpc32xx_nand_mlc_registers->isr);
191 return status & ISR_CONTROLLER_READY;
192 }
193
194 /**
195 * ECC layout -- this is needed whatever ECC mode we are using.
196 * In a 2KB (4*512B) page, R/S codes occupy 40 (4*10) bytes.
197 * To make U-Boot's life easier, we pack 'useable' OOB at the
198 * front and R/S ECC at the back.
199 */
200
201 static struct nand_ecclayout lpc32xx_largepage_ecclayout = {
202 .eccbytes = 40,
203 .eccpos = {24, 25, 26, 27, 28, 29, 30, 31, 32, 33,
204 34, 35, 36, 37, 38, 39, 40, 41, 42, 43,
205 44, 45, 46, 47, 48, 48, 50, 51, 52, 53,
206 54, 55, 56, 57, 58, 59, 60, 61, 62, 63,
207 },
208 .oobfree = {
209 /* bytes 0 and 1 are used for the bad block marker */
210 {
211 .offset = 2,
212 .length = 22
213 },
214 }
215 };
216
217 /**
218 * lpc32xx_read_page_hwecc - read in- and out-of-band data with ECC
219 * @mtd: mtd info structure
220 * @chip: nand chip info structure
221 * @buf: buffer to store read data
222 * @oob_required: caller requires OOB data read to chip->oob_poi
223 * @page: page number to read
224 *
225 * Use large block Auto Decode Read Mode(1) as described in User Manual
226 * section 8.6.2.1.
227 *
228 * The initial Read Mode and Read Start commands are sent by the caller.
229 *
230 * ECC will be false if out-of-band data has been updated since in-band
231 * data was initially written.
232 */
233
lpc32xx_read_page_hwecc(struct mtd_info * mtd,struct nand_chip * chip,uint8_t * buf,int oob_required,int page)234 static int lpc32xx_read_page_hwecc(struct mtd_info *mtd,
235 struct nand_chip *chip, uint8_t *buf, int oob_required,
236 int page)
237 {
238 unsigned int i, status, timeout, err, max_bitflips = 0;
239 struct lpc32xx_oob *oob = (struct lpc32xx_oob *)chip->oob_poi;
240
241 /* go through all four small pages */
242 for (i = 0; i < 4; i++) {
243 /* start auto decode (reads 528 NAND bytes) */
244 writel(0, &lpc32xx_nand_mlc_registers->ecc_auto_dec_reg);
245 /* wait for controller to return to ready state */
246 for (timeout = LPC32X_NAND_TIMEOUT; timeout; timeout--) {
247 status = readl(&lpc32xx_nand_mlc_registers->isr);
248 if (status & ISR_CONTROLLER_READY)
249 break;
250 udelay(1);
251 }
252 /* if decoder failed, return failure */
253 if (status & ISR_DECODER_FAILURE)
254 return -1;
255 /* keep count of maximum bitflips performed */
256 if (status & ISR_DECODER_ERROR) {
257 err = ISR_DECODER_ERRORS(status);
258 if (err > max_bitflips)
259 max_bitflips = err;
260 }
261 /* copy first 512 bytes into buffer */
262 memcpy(buf+512*i, lpc32xx_nand_mlc_registers->buff, 512);
263 /* copy next 6 bytes at front of OOB buffer */
264 memcpy(&oob->free[i], lpc32xx_nand_mlc_registers->buff, 6);
265 /* copy last 10 bytes (R/S ECC) at back of OOB buffer */
266 memcpy(&oob->ecc[i], lpc32xx_nand_mlc_registers->buff, 10);
267 }
268 return max_bitflips;
269 }
270
271 /**
272 * lpc32xx_read_page_raw - read raw (in-band, out-of-band and ECC) data
273 * @mtd: mtd info structure
274 * @chip: nand chip info structure
275 * @buf: buffer to store read data
276 * @oob_required: caller requires OOB data read to chip->oob_poi
277 * @page: page number to read
278 *
279 * Read NAND directly; can read pages with invalid ECC.
280 */
281
lpc32xx_read_page_raw(struct mtd_info * mtd,struct nand_chip * chip,uint8_t * buf,int oob_required,int page)282 static int lpc32xx_read_page_raw(struct mtd_info *mtd,
283 struct nand_chip *chip, uint8_t *buf, int oob_required,
284 int page)
285 {
286 unsigned int i, status, timeout;
287 struct lpc32xx_oob *oob = (struct lpc32xx_oob *)chip->oob_poi;
288
289 /* when we get here we've already had the Read Mode(1) */
290
291 /* go through all four small pages */
292 for (i = 0; i < 4; i++) {
293 /* wait for NAND to return to ready state */
294 for (timeout = LPC32X_NAND_TIMEOUT; timeout; timeout--) {
295 status = readl(&lpc32xx_nand_mlc_registers->isr);
296 if (status & ISR_NAND_READY)
297 break;
298 udelay(1);
299 }
300 /* if NAND stalled, return failure */
301 if (!(status & ISR_NAND_READY))
302 return -1;
303 /* copy first 512 bytes into buffer */
304 memcpy(buf+512*i, lpc32xx_nand_mlc_registers->data, 512);
305 /* copy next 6 bytes at front of OOB buffer */
306 memcpy(&oob->free[i], lpc32xx_nand_mlc_registers->data, 6);
307 /* copy last 10 bytes (R/S ECC) at back of OOB buffer */
308 memcpy(&oob->ecc[i], lpc32xx_nand_mlc_registers->data, 10);
309 }
310 return 0;
311 }
312
313 /**
314 * lpc32xx_read_oob - read out-of-band data
315 * @mtd: mtd info structure
316 * @chip: nand chip info structure
317 * @page: page number to read
318 *
319 * Read out-of-band data. User Manual section 8.6.4 suggests using Read
320 * Mode(3) which the controller will turn into a Read Mode(1) internally
321 * but nand_base.c will turn Mode(3) into Mode(0), so let's use Mode(0)
322 * directly.
323 *
324 * ECC covers in- and out-of-band data and was written when out-of-band
325 * data was blank. Therefore, if the out-of-band being read here is not
326 * blank, then the ECC will be false and the read will return bitflips,
327 * even in case of ECC failure where we will return 5 bitflips. The
328 * caller should be prepared to handle this.
329 */
330
lpc32xx_read_oob(struct mtd_info * mtd,struct nand_chip * chip,int page)331 static int lpc32xx_read_oob(struct mtd_info *mtd, struct nand_chip *chip,
332 int page)
333 {
334 unsigned int i, status, timeout, err, max_bitflips = 0;
335 struct lpc32xx_oob *oob = (struct lpc32xx_oob *)chip->oob_poi;
336
337 /* No command was sent before calling read_oob() so send one */
338
339 chip->cmdfunc(mtd, NAND_CMD_READ0, 0, page);
340
341 /* go through all four small pages */
342 for (i = 0; i < 4; i++) {
343 /* start auto decode (reads 528 NAND bytes) */
344 writel(0, &lpc32xx_nand_mlc_registers->ecc_auto_dec_reg);
345 /* wait for controller to return to ready state */
346 for (timeout = LPC32X_NAND_TIMEOUT; timeout; timeout--) {
347 status = readl(&lpc32xx_nand_mlc_registers->isr);
348 if (status & ISR_CONTROLLER_READY)
349 break;
350 udelay(1);
351 }
352 /* if decoder failure, count 'one too many' bitflips */
353 if (status & ISR_DECODER_FAILURE)
354 max_bitflips = 5;
355 /* keep count of maximum bitflips performed */
356 if (status & ISR_DECODER_ERROR) {
357 err = ISR_DECODER_ERRORS(status);
358 if (err > max_bitflips)
359 max_bitflips = err;
360 }
361 /* set read pointer to OOB area */
362 writel(0, &lpc32xx_nand_mlc_registers->robp);
363 /* copy next 6 bytes at front of OOB buffer */
364 memcpy(&oob->free[i], lpc32xx_nand_mlc_registers->buff, 6);
365 /* copy next 10 bytes (R/S ECC) at back of OOB buffer */
366 memcpy(&oob->ecc[i], lpc32xx_nand_mlc_registers->buff, 10);
367 }
368 return max_bitflips;
369 }
370
371 /**
372 * lpc32xx_write_page_hwecc - write in- and out-of-band data with ECC
373 * @mtd: mtd info structure
374 * @chip: nand chip info structure
375 * @buf: data buffer
376 * @oob_required: must write chip->oob_poi to OOB
377 *
378 * Use large block Auto Encode as per User Manual section 8.6.4.
379 *
380 * The initial Write Serial Input and final Auto Program commands are
381 * sent by the caller.
382 */
383
lpc32xx_write_page_hwecc(struct mtd_info * mtd,struct nand_chip * chip,const uint8_t * buf,int oob_required,int page)384 static int lpc32xx_write_page_hwecc(struct mtd_info *mtd,
385 struct nand_chip *chip, const uint8_t *buf, int oob_required,
386 int page)
387 {
388 unsigned int i, status, timeout;
389 struct lpc32xx_oob *oob = (struct lpc32xx_oob *)chip->oob_poi;
390
391 /* when we get here we've already had the SEQIN */
392 for (i = 0; i < 4; i++) {
393 /* start encode (expects 518 writes to buff) */
394 writel(0, &lpc32xx_nand_mlc_registers->ecc_enc_reg);
395 /* copy first 512 bytes from buffer */
396 memcpy(&lpc32xx_nand_mlc_registers->buff, buf+512*i, 512);
397 /* copy next 6 bytes from OOB buffer -- excluding ECC */
398 memcpy(&lpc32xx_nand_mlc_registers->buff, &oob->free[i], 6);
399 /* wait for ECC to return to ready state */
400 for (timeout = LPC32X_NAND_TIMEOUT; timeout; timeout--) {
401 status = readl(&lpc32xx_nand_mlc_registers->isr);
402 if (status & ISR_ECC_READY)
403 break;
404 udelay(1);
405 }
406 /* if ECC stalled, return failure */
407 if (!(status & ISR_ECC_READY))
408 return -1;
409 /* Trigger auto encode (writes 528 bytes to NAND) */
410 writel(0, &lpc32xx_nand_mlc_registers->ecc_auto_enc_reg);
411 /* wait for controller to return to ready state */
412 for (timeout = LPC32X_NAND_TIMEOUT; timeout; timeout--) {
413 status = readl(&lpc32xx_nand_mlc_registers->isr);
414 if (status & ISR_CONTROLLER_READY)
415 break;
416 udelay(1);
417 }
418 /* if controller stalled, return error */
419 if (!(status & ISR_CONTROLLER_READY))
420 return -1;
421 }
422 return 0;
423 }
424
425 /**
426 * lpc32xx_write_page_raw - write raw (in-band, out-of-band and ECC) data
427 * @mtd: mtd info structure
428 * @chip: nand chip info structure
429 * @buf: buffer to store read data
430 * @oob_required: caller requires OOB data read to chip->oob_poi
431 * @page: page number to read
432 *
433 * Use large block write but without encode.
434 *
435 * The initial Write Serial Input and final Auto Program commands are
436 * sent by the caller.
437 *
438 * This function will write the full out-of-band data, including the
439 * ECC area. Therefore, it can write pages with valid *or* invalid ECC.
440 */
441
lpc32xx_write_page_raw(struct mtd_info * mtd,struct nand_chip * chip,const uint8_t * buf,int oob_required,int page)442 static int lpc32xx_write_page_raw(struct mtd_info *mtd,
443 struct nand_chip *chip, const uint8_t *buf, int oob_required,
444 int page)
445 {
446 unsigned int i;
447 struct lpc32xx_oob *oob = (struct lpc32xx_oob *)chip->oob_poi;
448
449 /* when we get here we've already had the Read Mode(1) */
450 for (i = 0; i < 4; i++) {
451 /* copy first 512 bytes from buffer */
452 memcpy(lpc32xx_nand_mlc_registers->buff, buf+512*i, 512);
453 /* copy next 6 bytes into OOB buffer -- excluding ECC */
454 memcpy(lpc32xx_nand_mlc_registers->buff, &oob->free[i], 6);
455 /* copy next 10 bytes into OOB buffer -- that is 'ECC' */
456 memcpy(lpc32xx_nand_mlc_registers->buff, &oob->ecc[i], 10);
457 }
458 return 0;
459 }
460
461 /**
462 * lpc32xx_write_oob - write out-of-band data
463 * @mtd: mtd info structure
464 * @chip: nand chip info structure
465 * @page: page number to read
466 *
467 * Since ECC covers in- and out-of-band data, writing out-of-band data
468 * with ECC will render the page ECC wrong -- or, if the page was blank,
469 * then it will produce a good ECC but a later in-band data write will
470 * render it wrong.
471 *
472 * Therefore, do not compute or write any ECC, and always return success.
473 *
474 * This implies that we do four writes, since non-ECC out-of-band data
475 * are not contiguous in a large page.
476 */
477
lpc32xx_write_oob(struct mtd_info * mtd,struct nand_chip * chip,int page)478 static int lpc32xx_write_oob(struct mtd_info *mtd, struct nand_chip *chip,
479 int page)
480 {
481 /* update oob on all 4 subpages in sequence */
482 unsigned int i, status, timeout;
483 struct lpc32xx_oob *oob = (struct lpc32xx_oob *)chip->oob_poi;
484
485 for (i = 0; i < 4; i++) {
486 /* start data input */
487 chip->cmdfunc(mtd, NAND_CMD_SEQIN, 0x200+0x210*i, page);
488 /* copy 6 non-ECC out-of-band bytes directly into NAND */
489 memcpy(lpc32xx_nand_mlc_registers->data, &oob->free[i], 6);
490 /* program page */
491 chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1);
492 /* wait for NAND to return to ready state */
493 for (timeout = LPC32X_NAND_TIMEOUT; timeout; timeout--) {
494 status = readl(&lpc32xx_nand_mlc_registers->isr);
495 if (status & ISR_NAND_READY)
496 break;
497 udelay(1);
498 }
499 /* if NAND stalled, return error */
500 if (!(status & ISR_NAND_READY))
501 return -1;
502 }
503 return 0;
504 }
505
506 /**
507 * lpc32xx_waitfunc - wait until a command is done
508 * @mtd: MTD device structure
509 * @chip: NAND chip structure
510 *
511 * Wait for controller and FLASH to both be ready.
512 */
513
lpc32xx_waitfunc(struct mtd_info * mtd,struct nand_chip * chip)514 static int lpc32xx_waitfunc(struct mtd_info *mtd, struct nand_chip *chip)
515 {
516 int status;
517 unsigned int timeout;
518 /* wait until both controller and NAND are ready */
519 for (timeout = LPC32X_NAND_TIMEOUT; timeout; timeout--) {
520 status = readl(&lpc32xx_nand_mlc_registers->isr);
521 if ((status & (ISR_CONTROLLER_READY || ISR_NAND_READY))
522 == (ISR_CONTROLLER_READY || ISR_NAND_READY))
523 break;
524 udelay(1);
525 }
526 /* if controller or NAND stalled, return error */
527 if ((status & (ISR_CONTROLLER_READY || ISR_NAND_READY))
528 != (ISR_CONTROLLER_READY || ISR_NAND_READY))
529 return -1;
530 /* write NAND status command */
531 writel(NAND_CMD_STATUS, &lpc32xx_nand_mlc_registers->cmd);
532 /* read back status and return it */
533 return readb(&lpc32xx_nand_mlc_registers->data);
534 }
535
536 /*
537 * We are self-initializing, so we need our own chip struct
538 */
539
540 static struct nand_chip lpc32xx_chip;
541
542 /*
543 * Initialize the controller
544 */
545
board_nand_init(void)546 void board_nand_init(void)
547 {
548 struct mtd_info *mtd = nand_to_mtd(&lpc32xx_chip);
549 int ret;
550
551 /* Set all BOARDSPECIFIC (actually core-specific) fields */
552
553 lpc32xx_chip.IO_ADDR_R = &lpc32xx_nand_mlc_registers->buff;
554 lpc32xx_chip.IO_ADDR_W = &lpc32xx_nand_mlc_registers->buff;
555 lpc32xx_chip.cmd_ctrl = lpc32xx_cmd_ctrl;
556 /* do not set init_size: nand_base.c will read sizes from chip */
557 lpc32xx_chip.dev_ready = lpc32xx_dev_ready;
558 /* do not set setup_read_retry: this is NAND-chip-specific */
559 /* do not set chip_delay: we have dev_ready defined. */
560 lpc32xx_chip.options |= NAND_NO_SUBPAGE_WRITE;
561
562 /* Set needed ECC fields */
563
564 lpc32xx_chip.ecc.mode = NAND_ECC_HW;
565 lpc32xx_chip.ecc.layout = &lpc32xx_largepage_ecclayout;
566 lpc32xx_chip.ecc.size = 512;
567 lpc32xx_chip.ecc.bytes = 10;
568 lpc32xx_chip.ecc.strength = 4;
569 lpc32xx_chip.ecc.read_page = lpc32xx_read_page_hwecc;
570 lpc32xx_chip.ecc.read_page_raw = lpc32xx_read_page_raw;
571 lpc32xx_chip.ecc.write_page = lpc32xx_write_page_hwecc;
572 lpc32xx_chip.ecc.write_page_raw = lpc32xx_write_page_raw;
573 lpc32xx_chip.ecc.read_oob = lpc32xx_read_oob;
574 lpc32xx_chip.ecc.write_oob = lpc32xx_write_oob;
575 lpc32xx_chip.waitfunc = lpc32xx_waitfunc;
576
577 lpc32xx_chip.read_byte = lpc32xx_read_byte; /* FIXME: NEEDED? */
578
579 /* BBT options: read from last two pages */
580 lpc32xx_chip.bbt_options |= NAND_BBT_USE_FLASH | NAND_BBT_LASTBLOCK
581 | NAND_BBT_SCANLASTPAGE | NAND_BBT_SCAN2NDPAGE
582 | NAND_BBT_WRITE;
583
584 /* Initialize NAND interface */
585 lpc32xx_nand_init();
586
587 /* identify chip */
588 ret = nand_scan_ident(mtd, CONFIG_SYS_MAX_NAND_CHIPS, NULL);
589 if (ret) {
590 pr_err("nand_scan_ident returned %i", ret);
591 return;
592 }
593
594 /* finish scanning the chip */
595 ret = nand_scan_tail(mtd);
596 if (ret) {
597 pr_err("nand_scan_tail returned %i", ret);
598 return;
599 }
600
601 /* chip is good, register it */
602 ret = nand_register(0, mtd);
603 if (ret)
604 pr_err("nand_register returned %i", ret);
605 }
606
607 #else /* defined(CONFIG_SPL_BUILD) */
608
nand_init(void)609 void nand_init(void)
610 {
611 /* enable NAND controller */
612 lpc32xx_mlc_nand_init();
613 /* initialize NAND controller */
614 lpc32xx_nand_init();
615 }
616
nand_deselect(void)617 void nand_deselect(void)
618 {
619 /* nothing to do, but SPL requires this function */
620 }
621
read_single_page(uint8_t * dest,int page,struct lpc32xx_oob * oob)622 static int read_single_page(uint8_t *dest, int page,
623 struct lpc32xx_oob *oob)
624 {
625 int status, i, timeout, err, max_bitflips = 0;
626
627 /* enter read mode */
628 writel(NAND_CMD_READ0, &lpc32xx_nand_mlc_registers->cmd);
629 /* send column (lsb then MSB) and page (lsb to MSB) */
630 writel(0, &lpc32xx_nand_mlc_registers->addr);
631 writel(0, &lpc32xx_nand_mlc_registers->addr);
632 writel(page & 0xff, &lpc32xx_nand_mlc_registers->addr);
633 writel((page>>8) & 0xff, &lpc32xx_nand_mlc_registers->addr);
634 writel((page>>16) & 0xff, &lpc32xx_nand_mlc_registers->addr);
635 /* start reading */
636 writel(NAND_CMD_READSTART, &lpc32xx_nand_mlc_registers->cmd);
637
638 /* large page auto decode read */
639 for (i = 0; i < 4; i++) {
640 /* start auto decode (reads 528 NAND bytes) */
641 writel(0, &lpc32xx_nand_mlc_registers->ecc_auto_dec_reg);
642 /* wait for controller to return to ready state */
643 for (timeout = LPC32X_NAND_TIMEOUT; timeout; timeout--) {
644 status = readl(&lpc32xx_nand_mlc_registers->isr);
645 if (status & ISR_CONTROLLER_READY)
646 break;
647 udelay(1);
648 }
649 /* if controller stalled, return error */
650 if (!(status & ISR_CONTROLLER_READY))
651 return -1;
652 /* if decoder failure, return error */
653 if (status & ISR_DECODER_FAILURE)
654 return -1;
655 /* keep count of maximum bitflips performed */
656 if (status & ISR_DECODER_ERROR) {
657 err = ISR_DECODER_ERRORS(status);
658 if (err > max_bitflips)
659 max_bitflips = err;
660 }
661 /* copy first 512 bytes into buffer */
662 memcpy(dest+i*512, lpc32xx_nand_mlc_registers->buff, 512);
663 /* copy next 6 bytes bytes into OOB buffer */
664 memcpy(&oob->free[i], lpc32xx_nand_mlc_registers->buff, 6);
665 }
666 return max_bitflips;
667 }
668
669 /*
670 * Load U-Boot signed image.
671 * This loads an image from NAND, skipping bad blocks.
672 * A block is declared bad if at least one of its readable pages has
673 * a bad block marker in its OOB at position 0.
674 * If all pages ion a block are unreadable, the block is considered
675 * bad (i.e., assumed not to be part of the image) and skipped.
676 *
677 * IMPORTANT NOTE:
678 *
679 * If the first block of the image is fully unreadable, it will be
680 * ignored and skipped as if it had been marked bad. If it was not
681 * actually marked bad at the time of writing the image, the resulting
682 * image loaded will lack a header and magic number. It could thus be
683 * considered as a raw, headerless, image and SPL might erroneously
684 * jump into it.
685 *
686 * In order to avoid this risk, LPC32XX-based boards which use this
687 * driver MUST define CONFIG_SPL_PANIC_ON_RAW_IMAGE.
688 */
689
690 #define BYTES_PER_PAGE 2048
691 #define PAGES_PER_BLOCK 64
692 #define BYTES_PER_BLOCK (BYTES_PER_PAGE * PAGES_PER_BLOCK)
693 #define PAGES_PER_CHIP_MAX 524288
694
nand_spl_load_image(uint32_t offs,unsigned int size,void * dst)695 int nand_spl_load_image(uint32_t offs, unsigned int size, void *dst)
696 {
697 int bytes_left = size;
698 int pages_left = DIV_ROUND_UP(size, BYTES_PER_PAGE);
699 int blocks_left = DIV_ROUND_UP(size, BYTES_PER_BLOCK);
700 int block = 0;
701 int page = offs / BYTES_PER_PAGE;
702 /* perform reads block by block */
703 while (blocks_left) {
704 /* compute first page number to read */
705 void *block_page_dst = dst;
706 /* read at most one block, possibly less */
707 int block_bytes_left = bytes_left;
708 if (block_bytes_left > BYTES_PER_BLOCK)
709 block_bytes_left = BYTES_PER_BLOCK;
710 /* keep track of good, failed, and "bad" pages */
711 int block_pages_good = 0;
712 int block_pages_bad = 0;
713 int block_pages_err = 0;
714 /* we shall read a full block of pages, maybe less */
715 int block_pages_left = pages_left;
716 if (block_pages_left > PAGES_PER_BLOCK)
717 block_pages_left = PAGES_PER_BLOCK;
718 int block_pages = block_pages_left;
719 int block_page = page;
720 /* while pages are left and the block is not known as bad */
721 while ((block_pages > 0) && (block_pages_bad == 0)) {
722 /* we will read OOB, too, for bad block markers */
723 struct lpc32xx_oob oob;
724 /* read page */
725 int res = read_single_page(block_page_dst, block_page,
726 &oob);
727 /* count readable pages */
728 if (res >= 0) {
729 /* this page is good */
730 block_pages_good++;
731 /* this page is bad */
732 if ((oob.free[0].free_oob_bytes[0] != 0xff)
733 | (oob.free[0].free_oob_bytes[1] != 0xff))
734 block_pages_bad++;
735 } else
736 /* count errors */
737 block_pages_err++;
738 /* we're done with this page */
739 block_page++;
740 block_page_dst += BYTES_PER_PAGE;
741 if (block_pages)
742 block_pages--;
743 }
744 /* a fully unreadable block is considered bad */
745 if (block_pages_good == 0)
746 block_pages_bad = block_pages_err;
747 /* errors are fatal only in good blocks */
748 if ((block_pages_err > 0) && (block_pages_bad == 0))
749 return -1;
750 /* we keep reads only of good blocks */
751 if (block_pages_bad == 0) {
752 dst += block_bytes_left;
753 bytes_left -= block_bytes_left;
754 pages_left -= block_pages_left;
755 blocks_left--;
756 }
757 /* good or bad, we're done with this block */
758 block++;
759 page += PAGES_PER_BLOCK;
760 }
761
762 /* report success */
763 return 0;
764 }
765
766 #endif /* CONFIG_SPL_BUILD */
767