1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* 3 * Copyright (c) 2016 Heiko Stuebner <heiko@sntech.de> 4 */ 5 6 #ifndef _ASM_ARCH_GRF_RK3188_H 7 #define _ASM_ARCH_GRF_RK3188_H 8 9 struct rk3188_grf_gpio_lh { 10 u32 l; 11 u32 h; 12 }; 13 14 struct rk3188_grf { 15 struct rk3188_grf_gpio_lh gpio_dir[4]; 16 struct rk3188_grf_gpio_lh gpio_do[4]; 17 struct rk3188_grf_gpio_lh gpio_en[4]; 18 19 u32 reserved[2]; 20 u32 gpio0c_iomux; 21 u32 gpio0d_iomux; 22 23 u32 gpio1a_iomux; 24 u32 gpio1b_iomux; 25 u32 gpio1c_iomux; 26 u32 gpio1d_iomux; 27 28 u32 gpio2a_iomux; 29 u32 gpio2b_iomux; 30 u32 gpio2c_iomux; 31 u32 gpio2d_iomux; 32 33 u32 gpio3a_iomux; 34 u32 gpio3b_iomux; 35 u32 gpio3c_iomux; 36 u32 gpio3d_iomux; 37 38 u32 soc_con0; 39 u32 soc_con1; 40 u32 soc_con2; 41 u32 soc_status0; 42 43 u32 busdmac_con[3]; 44 u32 peridmac_con[4]; 45 46 u32 cpu_con[6]; 47 u32 reserved0[2]; 48 49 u32 ddrc_con0; 50 u32 ddrc_stat; 51 52 u32 io_con[5]; 53 u32 soc_status1; 54 55 u32 uoc0_con[4]; 56 u32 uoc1_con[4]; 57 u32 uoc2_con[2]; 58 u32 reserved1; 59 u32 uoc3_con[2]; 60 u32 hsic_stat; 61 u32 os_reg[8]; 62 63 u32 gpio0_p[3]; 64 u32 gpio1_p[3][4]; 65 66 u32 flash_data_p; 67 u32 flash_cmd_p; 68 }; 69 check_member(rk3188_grf, flash_cmd_p, 0x01a4); 70 71 /* GRF_SOC_CON0 */ 72 enum { 73 HSADC_CLK_DIR_SHIFT = 15, 74 HSADC_CLK_DIR_MASK = 1, 75 76 HSADC_SEL_SHIFT = 14, 77 HSADC_SEL_MASK = 1, 78 79 NOC_REMAP_SHIFT = 12, 80 NOC_REMAP_MASK = 1, 81 82 EMMC_FLASH_SEL_SHIFT = 11, 83 EMMC_FLASH_SEL_MASK = 1, 84 85 TZPC_REVISION_SHIFT = 7, 86 TZPC_REVISION_MASK = 0xf, 87 88 L2CACHE_ACC_SHIFT = 5, 89 L2CACHE_ACC_MASK = 3, 90 91 L2RD_WAIT_SHIFT = 3, 92 L2RD_WAIT_MASK = 3, 93 94 IMEMRD_WAIT_SHIFT = 1, 95 IMEMRD_WAIT_MASK = 3, 96 }; 97 98 /* GRF_SOC_CON1 */ 99 enum { 100 RKI2C4_SEL_SHIFT = 15, 101 RKI2C4_SEL_MASK = 1, 102 103 RKI2C3_SEL_SHIFT = 14, 104 RKI2C3_SEL_MASK = 1, 105 106 RKI2C2_SEL_SHIFT = 13, 107 RKI2C2_SEL_MASK = 1, 108 109 RKI2C1_SEL_SHIFT = 12, 110 RKI2C1_SEL_MASK = 1, 111 112 RKI2C0_SEL_SHIFT = 11, 113 RKI2C0_SEL_MASK = 1, 114 115 VCODEC_SEL_SHIFT = 10, 116 VCODEC_SEL_MASK = 1, 117 118 PERI_EMEM_PAUSE_SHIFT = 9, 119 PERI_EMEM_PAUSE_MASK = 1, 120 121 PERI_USB_PAUSE_SHIFT = 8, 122 PERI_USB_PAUSE_MASK = 1, 123 124 SMC_MUX_MODE_0_SHIFT = 6, 125 SMC_MUX_MODE_0_MASK = 1, 126 127 SMC_SRAM_MW_0_SHIFT = 4, 128 SMC_SRAM_MW_0_MASK = 3, 129 130 SMC_REMAP_0_SHIFT = 3, 131 SMC_REMAP_0_MASK = 1, 132 133 SMC_A_GT_M0_SYNC_SHIFT = 2, 134 SMC_A_GT_M0_SYNC_MASK = 1, 135 136 EMAC_SPEED_SHIFT = 1, 137 EMAC_SPEEC_MASK = 1, 138 139 EMAC_MODE_SHIFT = 0, 140 EMAC_MODE_MASK = 1, 141 }; 142 143 /* GRF_SOC_CON2 */ 144 enum { 145 SDIO_CLK_OUT_SR_SHIFT = 15, 146 SDIO_CLK_OUT_SR_MASK = 1, 147 148 MEM_EMA_L2C_SHIFT = 11, 149 MEM_EMA_L2C_MASK = 7, 150 151 MEM_EMA_A9_SHIFT = 8, 152 MEM_EMA_A9_MASK = 7, 153 154 MSCH4_MAINDDR3_SHIFT = 7, 155 MSCH4_MAINDDR3_MASK = 1, 156 MSCH4_MAINDDR3_DDR3 = 1, 157 158 EMAC_NEWRCV_EN_SHIFT = 6, 159 EMAC_NEWRCV_EN_MASK = 1, 160 161 SW_ADDR15_EN_SHIFT = 5, 162 SW_ADDR15_EN_MASK = 1, 163 164 SW_ADDR16_EN_SHIFT = 4, 165 SW_ADDR16_EN_MASK = 1, 166 167 SW_ADDR17_EN_SHIFT = 3, 168 SW_ADDR17_EN_MASK = 1, 169 170 BANK2_TO_RANK_EN_SHIFT = 2, 171 BANK2_TO_RANK_EN_MASK = 1, 172 173 RANK_TO_ROW15_EN_SHIFT = 1, 174 RANK_TO_ROW15_EN_MASK = 1, 175 176 UPCTL_C_ACTIVE_IN_SHIFT = 0, 177 UPCTL_C_ACTIVE_IN_MASK = 1, 178 UPCTL_C_ACTIVE_IN_MAY = 0, 179 UPCTL_C_ACTIVE_IN_WILL, 180 }; 181 182 /* GRF_DDRC_CON0 */ 183 enum { 184 DDR_16BIT_EN_SHIFT = 15, 185 DDR_16BIT_EN_MASK = 1, 186 187 DTO_LB_SHIFT = 11, 188 DTO_LB_MASK = 3, 189 190 DTO_TE_SHIFT = 9, 191 DTO_TE_MASK = 3, 192 193 DTO_PDR_SHIFT = 7, 194 DTO_PDR_MASK = 3, 195 196 DTO_PDD_SHIFT = 5, 197 DTO_PDD_MASK = 3, 198 199 DTO_IOM_SHIFT = 3, 200 DTO_IOM_MASK = 3, 201 202 DTO_OE_SHIFT = 1, 203 DTO_OE_MASK = 3, 204 205 ATO_AE_SHIFT = 0, 206 ATO_AE_MASK = 1, 207 }; 208 209 /* GRF_UOC_CON0 */ 210 enum { 211 SIDDQ_SHIFT = 13, 212 SIDDQ_MASK = 1 << SIDDQ_SHIFT, 213 214 BYPASSSEL_SHIFT = 9, 215 BYPASSSEL_MASK = 1 << BYPASSSEL_SHIFT, 216 217 BYPASSDMEN_SHIFT = 8, 218 BYPASSDMEN_MASK = 1 << BYPASSDMEN_SHIFT, 219 220 UOC_DISABLE_SHIFT = 4, 221 UOC_DISABLE_MASK = 1 << UOC_DISABLE_SHIFT, 222 223 COMMON_ON_N_SHIFT = 0, 224 COMMON_ON_N_MASK = 1 << COMMON_ON_N_SHIFT, 225 }; 226 227 /* GRF_UOC_CON2 */ 228 enum { 229 SOFT_CON_SEL_SHIFT = 2, 230 SOFT_CON_SEL_MASK = 1 << SOFT_CON_SEL_SHIFT, 231 }; 232 233 /* GRF_UOC0_CON3 */ 234 enum { 235 TERMSEL_FULLSPEED_SHIFT = 5, 236 TERMSEL_FULLSPEED_MASK = 1 << TERMSEL_FULLSPEED_SHIFT, 237 238 XCVRSELECT_SHIFT = 3, 239 XCVRSELECT_FSTRANSC = 1, 240 XCVRSELECT_MASK = 3 << XCVRSELECT_SHIFT, 241 242 OPMODE_SHIFT = 1, 243 OPMODE_NODRIVING = 1, 244 OPMODE_MASK = 3 << OPMODE_SHIFT, 245 246 SUSPENDN_SHIFT = 0, 247 SUSPENDN_MASK = 1 << SUSPENDN_SHIFT, 248 }; 249 250 #endif 251