1 /* SPDX-License-Identifier: BSD-3-Clause */
2 /*
3 * Cadence DDR Driver
4 *
5 * Copyright (C) 2012-2021 Cadence Design Systems, Inc.
6 * Copyright (C) 2018-2021 Texas Instruments Incorporated - https://www.ti.com/
7 */
8
9 #ifndef LPDDR4_SANITY_H
10 #define LPDDR4_SANITY_H
11
12 #include <errno.h>
13 #include <linux/types.h>
14 #include "lpddr4_if.h"
15 #ifdef __cplusplus
16 extern "C" {
17 #endif
18
19 static inline u32 lpddr4_configsf(const lpddr4_config *obj);
20 static inline u32 lpddr4_privatedatasf(const lpddr4_privatedata *obj);
21
22 static inline u32 lpddr4_sanityfunction1(const lpddr4_config *config, const u16 *configsize);
23 static inline u32 lpddr4_sanityfunction2(const lpddr4_privatedata *pd, const lpddr4_config *cfg);
24 static inline u32 lpddr4_sanityfunction3(const lpddr4_privatedata *pd);
25 static inline u32 lpddr4_sanityfunction4(const lpddr4_privatedata *pd, const lpddr4_regblock cpp, const u32 *regvalue);
26 static inline u32 lpddr4_sanityfunction5(const lpddr4_privatedata *pd, const lpddr4_regblock cpp);
27 static inline u32 lpddr4_sanityfunction6(const lpddr4_privatedata *pd, const u64 *mmrvalue, const u8 *mmrstatus);
28 static inline u32 lpddr4_sanityfunction7(const lpddr4_privatedata *pd, const u8 *mrwstatus);
29 static inline u32 lpddr4_sanityfunction14(const lpddr4_privatedata *pd, const u64 *mask);
30 static inline u32 lpddr4_sanityfunction15(const lpddr4_privatedata *pd, const u64 *mask);
31 static inline u32 lpddr4_sanityfunction16(const lpddr4_privatedata *pd, const u32 *mask);
32 static inline u32 lpddr4_sanityfunction18(const lpddr4_privatedata *pd, const lpddr4_debuginfo *debuginfo);
33 static inline u32 lpddr4_sanityfunction19(const lpddr4_privatedata *pd, const lpddr4_lpiwakeupparam *lpiwakeupparam, const lpddr4_ctlfspnum *fspnum, const u32 *cycles);
34 static inline u32 lpddr4_sanityfunction21(const lpddr4_privatedata *pd, const lpddr4_eccenable *eccparam);
35 static inline u32 lpddr4_sanityfunction22(const lpddr4_privatedata *pd, const lpddr4_eccenable *eccparam);
36 static inline u32 lpddr4_sanityfunction23(const lpddr4_privatedata *pd, const lpddr4_reducmode *mode);
37 static inline u32 lpddr4_sanityfunction24(const lpddr4_privatedata *pd, const lpddr4_reducmode *mode);
38 static inline u32 lpddr4_sanityfunction25(const lpddr4_privatedata *pd, const bool *on_off);
39 static inline u32 lpddr4_sanityfunction27(const lpddr4_privatedata *pd, const lpddr4_dbimode *mode);
40 static inline u32 lpddr4_sanityfunction28(const lpddr4_privatedata *pd, const lpddr4_ctlfspnum *fspnum, const u32 *tref, const u32 *tras_max);
41 static inline u32 lpddr4_sanityfunction29(const lpddr4_privatedata *pd, const lpddr4_ctlfspnum *fspnum, const u32 *tref, const u32 *tras_max);
42
43 #define lpddr4_probesf lpddr4_sanityfunction1
44 #define lpddr4_initsf lpddr4_sanityfunction2
45 #define lpddr4_startsf lpddr4_sanityfunction3
46 #define lpddr4_readregsf lpddr4_sanityfunction4
47 #define lpddr4_writeregsf lpddr4_sanityfunction5
48 #define lpddr4_getmmrregistersf lpddr4_sanityfunction6
49 #define lpddr4_setmmrregistersf lpddr4_sanityfunction7
50 #define lpddr4_writectlconfigsf lpddr4_sanityfunction3
51 #define lpddr4_writephyconfigsf lpddr4_sanityfunction3
52 #define lpddr4_writephyindepconfigsf lpddr4_sanityfunction3
53 #define lpddr4_readctlconfigsf lpddr4_sanityfunction3
54 #define lpddr4_readphyconfigsf lpddr4_sanityfunction3
55 #define lpddr4_readphyindepconfigsf lpddr4_sanityfunction3
56 #define lpddr4_getctlinterruptmasksf lpddr4_sanityfunction14
57 #define lpddr4_setctlinterruptmasksf lpddr4_sanityfunction15
58 #define lpddr4_getphyindepinterruptmsf lpddr4_sanityfunction16
59 #define lpddr4_setphyindepinterruptmsf lpddr4_sanityfunction16
60 #define lpddr4_getdebuginitinfosf lpddr4_sanityfunction18
61 #define lpddr4_getlpiwakeuptimesf lpddr4_sanityfunction19
62 #define lpddr4_setlpiwakeuptimesf lpddr4_sanityfunction19
63 #define lpddr4_geteccenablesf lpddr4_sanityfunction21
64 #define lpddr4_seteccenablesf lpddr4_sanityfunction22
65 #define lpddr4_getreducmodesf lpddr4_sanityfunction23
66 #define lpddr4_setreducmodesf lpddr4_sanityfunction24
67 #define lpddr4_getdbireadmodesf lpddr4_sanityfunction25
68 #define lpddr4_getdbiwritemodesf lpddr4_sanityfunction25
69 #define lpddr4_setdbimodesf lpddr4_sanityfunction27
70 #define lpddr4_getrefreshratesf lpddr4_sanityfunction28
71 #define lpddr4_setrefreshratesf lpddr4_sanityfunction29
72 #define lpddr4_refreshperchipselectsf lpddr4_sanityfunction3
73
lpddr4_configsf(const lpddr4_config * obj)74 static inline u32 lpddr4_configsf(const lpddr4_config *obj)
75 {
76 u32 ret = 0;
77
78 if (obj == NULL)
79 ret = EINVAL;
80
81 return ret;
82 }
83
lpddr4_privatedatasf(const lpddr4_privatedata * obj)84 static inline u32 lpddr4_privatedatasf(const lpddr4_privatedata *obj)
85 {
86 u32 ret = 0;
87
88 if (obj == NULL)
89 ret = EINVAL;
90
91 return ret;
92 }
93
lpddr4_sanityfunction1(const lpddr4_config * config,const u16 * configsize)94 static inline u32 lpddr4_sanityfunction1(const lpddr4_config *config, const u16 *configsize)
95 {
96 u32 ret = 0;
97
98 if (configsize == NULL) {
99 ret = EINVAL;
100 } else if (lpddr4_configsf(config) == EINVAL) {
101 ret = EINVAL;
102 } else {
103 }
104
105 return ret;
106 }
107
lpddr4_sanityfunction2(const lpddr4_privatedata * pd,const lpddr4_config * cfg)108 static inline u32 lpddr4_sanityfunction2(const lpddr4_privatedata *pd, const lpddr4_config *cfg)
109 {
110 u32 ret = 0;
111
112 if (lpddr4_privatedatasf(pd) == EINVAL) {
113 ret = EINVAL;
114 } else if (lpddr4_configsf(cfg) == EINVAL) {
115 ret = EINVAL;
116 } else {
117 }
118
119 return ret;
120 }
121
lpddr4_sanityfunction3(const lpddr4_privatedata * pd)122 static inline u32 lpddr4_sanityfunction3(const lpddr4_privatedata *pd)
123 {
124 u32 ret = 0;
125
126 if (lpddr4_privatedatasf(pd) == EINVAL)
127 ret = EINVAL;
128
129 return ret;
130 }
131
lpddr4_sanityfunction4(const lpddr4_privatedata * pd,const lpddr4_regblock cpp,const u32 * regvalue)132 static inline u32 lpddr4_sanityfunction4(const lpddr4_privatedata *pd, const lpddr4_regblock cpp, const u32 *regvalue)
133 {
134 u32 ret = 0;
135
136 if (regvalue == NULL) {
137 ret = EINVAL;
138 } else if (lpddr4_privatedatasf(pd) == EINVAL) {
139 ret = EINVAL;
140 } else if (
141 (cpp != LPDDR4_CTL_REGS) &&
142 (cpp != LPDDR4_PHY_REGS) &&
143 (cpp != LPDDR4_PHY_INDEP_REGS)
144 ) {
145 ret = EINVAL;
146 } else {
147 }
148
149 return ret;
150 }
151
lpddr4_sanityfunction5(const lpddr4_privatedata * pd,const lpddr4_regblock cpp)152 static inline u32 lpddr4_sanityfunction5(const lpddr4_privatedata *pd, const lpddr4_regblock cpp)
153 {
154 u32 ret = 0;
155
156 if (lpddr4_privatedatasf(pd) == EINVAL) {
157 ret = EINVAL;
158 } else if (
159 (cpp != LPDDR4_CTL_REGS) &&
160 (cpp != LPDDR4_PHY_REGS) &&
161 (cpp != LPDDR4_PHY_INDEP_REGS)
162 ) {
163 ret = EINVAL;
164 } else {
165 }
166
167 return ret;
168 }
169
lpddr4_sanityfunction6(const lpddr4_privatedata * pd,const u64 * mmrvalue,const u8 * mmrstatus)170 static inline u32 lpddr4_sanityfunction6(const lpddr4_privatedata *pd, const u64 *mmrvalue, const u8 *mmrstatus)
171 {
172 u32 ret = 0;
173
174 if (mmrvalue == NULL) {
175 ret = EINVAL;
176 } else if (mmrstatus == NULL) {
177 ret = EINVAL;
178 } else if (lpddr4_privatedatasf(pd) == EINVAL) {
179 ret = EINVAL;
180 } else {
181 }
182
183 return ret;
184 }
185
lpddr4_sanityfunction7(const lpddr4_privatedata * pd,const u8 * mrwstatus)186 static inline u32 lpddr4_sanityfunction7(const lpddr4_privatedata *pd, const u8 *mrwstatus)
187 {
188 u32 ret = 0;
189
190 if (mrwstatus == NULL) {
191 ret = EINVAL;
192 } else if (lpddr4_privatedatasf(pd) == EINVAL) {
193 ret = EINVAL;
194 } else {
195 }
196
197 return ret;
198 }
199
lpddr4_sanityfunction14(const lpddr4_privatedata * pd,const u64 * mask)200 static inline u32 lpddr4_sanityfunction14(const lpddr4_privatedata *pd, const u64 *mask)
201 {
202 u32 ret = 0;
203
204 if (mask == NULL) {
205 ret = EINVAL;
206 } else if (lpddr4_privatedatasf(pd) == EINVAL) {
207 ret = EINVAL;
208 } else {
209 }
210
211 return ret;
212 }
213
lpddr4_sanityfunction15(const lpddr4_privatedata * pd,const u64 * mask)214 static inline u32 lpddr4_sanityfunction15(const lpddr4_privatedata *pd, const u64 *mask)
215 {
216 u32 ret = 0;
217
218 if (mask == NULL) {
219 ret = EINVAL;
220 } else if (lpddr4_privatedatasf(pd) == EINVAL) {
221 ret = EINVAL;
222 } else {
223 }
224
225 return ret;
226 }
227
lpddr4_sanityfunction16(const lpddr4_privatedata * pd,const u32 * mask)228 static inline u32 lpddr4_sanityfunction16(const lpddr4_privatedata *pd, const u32 *mask)
229 {
230 u32 ret = 0;
231
232 if (mask == NULL) {
233 ret = EINVAL;
234 } else if (lpddr4_privatedatasf(pd) == EINVAL) {
235 ret = EINVAL;
236 } else {
237 }
238
239 return ret;
240 }
241
lpddr4_sanityfunction18(const lpddr4_privatedata * pd,const lpddr4_debuginfo * debuginfo)242 static inline u32 lpddr4_sanityfunction18(const lpddr4_privatedata *pd, const lpddr4_debuginfo *debuginfo)
243 {
244 u32 ret = 0;
245
246 if (debuginfo == NULL) {
247 ret = EINVAL;
248 } else if (lpddr4_privatedatasf(pd) == EINVAL) {
249 ret = EINVAL;
250 } else {
251 }
252
253 return ret;
254 }
255
lpddr4_sanityfunction19(const lpddr4_privatedata * pd,const lpddr4_lpiwakeupparam * lpiwakeupparam,const lpddr4_ctlfspnum * fspnum,const u32 * cycles)256 static inline u32 lpddr4_sanityfunction19(const lpddr4_privatedata *pd, const lpddr4_lpiwakeupparam *lpiwakeupparam, const lpddr4_ctlfspnum *fspnum, const u32 *cycles)
257 {
258 u32 ret = 0;
259
260 if (lpiwakeupparam == NULL) {
261 ret = EINVAL;
262 } else if (fspnum == NULL) {
263 ret = EINVAL;
264 } else if (cycles == NULL) {
265 ret = EINVAL;
266 } else if (lpddr4_privatedatasf(pd) == EINVAL) {
267 ret = EINVAL;
268 } else if (
269 (*lpiwakeupparam != LPDDR4_LPI_PD_WAKEUP_FN) &&
270 (*lpiwakeupparam != LPDDR4_LPI_SR_SHORT_WAKEUP_FN) &&
271 (*lpiwakeupparam != LPDDR4_LPI_SR_LONG_WAKEUP_FN) &&
272 (*lpiwakeupparam != LPDDR4_LPI_SR_LONG_MCCLK_GATE_WAKEUP_FN) &&
273 (*lpiwakeupparam != LPDDR4_LPI_SRPD_SHORT_WAKEUP_FN) &&
274 (*lpiwakeupparam != LPDDR4_LPI_SRPD_LONG_WAKEUP_FN) &&
275 (*lpiwakeupparam != LPDDR4_LPI_SRPD_LONG_MCCLK_GATE_WAKEUP_FN)
276 ) {
277 ret = EINVAL;
278 } else if (
279 (*fspnum != LPDDR4_FSP_0) &&
280 (*fspnum != LPDDR4_FSP_1) &&
281 (*fspnum != LPDDR4_FSP_2)
282 ) {
283 ret = EINVAL;
284 } else {
285 }
286
287 return ret;
288 }
289
lpddr4_sanityfunction21(const lpddr4_privatedata * pd,const lpddr4_eccenable * eccparam)290 static inline u32 lpddr4_sanityfunction21(const lpddr4_privatedata *pd, const lpddr4_eccenable *eccparam)
291 {
292 u32 ret = 0;
293
294 if (eccparam == NULL) {
295 ret = EINVAL;
296 } else if (lpddr4_privatedatasf(pd) == EINVAL) {
297 ret = EINVAL;
298 } else {
299 }
300
301 return ret;
302 }
303
lpddr4_sanityfunction22(const lpddr4_privatedata * pd,const lpddr4_eccenable * eccparam)304 static inline u32 lpddr4_sanityfunction22(const lpddr4_privatedata *pd, const lpddr4_eccenable *eccparam)
305 {
306 u32 ret = 0;
307
308 if (eccparam == NULL) {
309 ret = EINVAL;
310 } else if (lpddr4_privatedatasf(pd) == EINVAL) {
311 ret = EINVAL;
312 } else if (
313 (*eccparam != LPDDR4_ECC_DISABLED) &&
314 (*eccparam != LPDDR4_ECC_ENABLED) &&
315 (*eccparam != LPDDR4_ECC_ERR_DETECT) &&
316 (*eccparam != LPDDR4_ECC_ERR_DETECT_CORRECT)
317 ) {
318 ret = EINVAL;
319 } else {
320 }
321
322 return ret;
323 }
324
lpddr4_sanityfunction23(const lpddr4_privatedata * pd,const lpddr4_reducmode * mode)325 static inline u32 lpddr4_sanityfunction23(const lpddr4_privatedata *pd, const lpddr4_reducmode *mode)
326 {
327 u32 ret = 0;
328
329 if (mode == NULL) {
330 ret = EINVAL;
331 } else if (lpddr4_privatedatasf(pd) == EINVAL) {
332 ret = EINVAL;
333 } else {
334 }
335
336 return ret;
337 }
338
lpddr4_sanityfunction24(const lpddr4_privatedata * pd,const lpddr4_reducmode * mode)339 static inline u32 lpddr4_sanityfunction24(const lpddr4_privatedata *pd, const lpddr4_reducmode *mode)
340 {
341 u32 ret = 0;
342
343 if (mode == NULL) {
344 ret = EINVAL;
345 } else if (lpddr4_privatedatasf(pd) == EINVAL) {
346 ret = EINVAL;
347 } else if (
348 (*mode != LPDDR4_REDUC_ON) &&
349 (*mode != LPDDR4_REDUC_OFF)
350 ) {
351 ret = EINVAL;
352 } else {
353 }
354
355 return ret;
356 }
357
lpddr4_sanityfunction25(const lpddr4_privatedata * pd,const bool * on_off)358 static inline u32 lpddr4_sanityfunction25(const lpddr4_privatedata *pd, const bool *on_off)
359 {
360 u32 ret = 0;
361
362 if (on_off == NULL) {
363 ret = EINVAL;
364 } else if (lpddr4_privatedatasf(pd) == EINVAL) {
365 ret = EINVAL;
366 } else {
367 }
368
369 return ret;
370 }
371
lpddr4_sanityfunction27(const lpddr4_privatedata * pd,const lpddr4_dbimode * mode)372 static inline u32 lpddr4_sanityfunction27(const lpddr4_privatedata *pd, const lpddr4_dbimode *mode)
373 {
374 u32 ret = 0;
375
376 if (mode == NULL) {
377 ret = EINVAL;
378 } else if (lpddr4_privatedatasf(pd) == EINVAL) {
379 ret = EINVAL;
380 } else if (
381 (*mode != LPDDR4_DBI_RD_ON) &&
382 (*mode != LPDDR4_DBI_RD_OFF) &&
383 (*mode != LPDDR4_DBI_WR_ON) &&
384 (*mode != LPDDR4_DBI_WR_OFF)
385 ) {
386 ret = EINVAL;
387 } else {
388 }
389
390 return ret;
391 }
392
lpddr4_sanityfunction28(const lpddr4_privatedata * pd,const lpddr4_ctlfspnum * fspnum,const u32 * tref,const u32 * tras_max)393 static inline u32 lpddr4_sanityfunction28(const lpddr4_privatedata *pd, const lpddr4_ctlfspnum *fspnum, const u32 *tref, const u32 *tras_max)
394 {
395 u32 ret = 0;
396
397 if (fspnum == NULL) {
398 ret = EINVAL;
399 } else if (tref == NULL) {
400 ret = EINVAL;
401 } else if (tras_max == NULL) {
402 ret = EINVAL;
403 } else if (lpddr4_privatedatasf(pd) == EINVAL) {
404 ret = EINVAL;
405 } else if (
406 (*fspnum != LPDDR4_FSP_0) &&
407 (*fspnum != LPDDR4_FSP_1) &&
408 (*fspnum != LPDDR4_FSP_2)
409 ) {
410 ret = EINVAL;
411 } else {
412 }
413
414 return ret;
415 }
416
lpddr4_sanityfunction29(const lpddr4_privatedata * pd,const lpddr4_ctlfspnum * fspnum,const u32 * tref,const u32 * tras_max)417 static inline u32 lpddr4_sanityfunction29(const lpddr4_privatedata *pd, const lpddr4_ctlfspnum *fspnum, const u32 *tref, const u32 *tras_max)
418 {
419 u32 ret = 0;
420
421 if (fspnum == NULL) {
422 ret = EINVAL;
423 } else if (tref == NULL) {
424 ret = EINVAL;
425 } else if (tras_max == NULL) {
426 ret = EINVAL;
427 } else if (lpddr4_privatedatasf(pd) == EINVAL) {
428 ret = EINVAL;
429 } else if (
430 (*fspnum != LPDDR4_FSP_0) &&
431 (*fspnum != LPDDR4_FSP_1) &&
432 (*fspnum != LPDDR4_FSP_2)
433 ) {
434 ret = EINVAL;
435 } else {
436 }
437
438 return ret;
439 }
440
441 #ifdef __cplusplus
442 }
443 #endif
444
445 #endif /* LPDDR4_SANITY_H */
446