1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Copyright 2016 Freescale Semiconductor, Inc.
4 * Author: Hongbo Zhang <hongbo.zhang@nxp.com>
5 * This file implements LS102X platform PSCI SYSTEM-SUSPEND function
6 */
7
8 #include <config.h>
9 #include <cpu_func.h>
10 #include <asm/io.h>
11 #include <asm/psci.h>
12 #include <asm/arch/immap_ls102xa.h>
13 #include <fsl_immap.h>
14 #include "fsl_epu.h"
15
16 #define __secure __section("._secure.text")
17
18 #define CCSR_GICD_CTLR 0x1000
19 #define CCSR_GICC_CTLR 0x2000
20 #define DCSR_RCPM_CG1CR0 0x31c
21 #define DCSR_RCPM_CSTTACR0 0xb00
22 #define DCFG_CRSTSR_WDRFR 0x8
23 #define DDR_RESV_LEN 128
24
25 #ifdef CONFIG_LS1_DEEP_SLEEP
26 /*
27 * DDR controller initialization training breaks the first 128 bytes of DDR,
28 * save them so that the bootloader can restore them while resuming.
29 */
ls1_save_ddr_head(void)30 static void __secure ls1_save_ddr_head(void)
31 {
32 const char *src = (const char *)CONFIG_SYS_SDRAM_BASE;
33 char *dest = (char *)(OCRAM_BASE_S_ADDR + OCRAM_S_SIZE - DDR_RESV_LEN);
34 struct ccsr_scfg __iomem *scfg = (void *)CONFIG_SYS_FSL_SCFG_ADDR;
35 int i;
36
37 out_le32(&scfg->sparecr[2], dest);
38
39 for (i = 0; i < DDR_RESV_LEN; i++)
40 *dest++ = *src++;
41 }
42
ls1_fsm_setup(void)43 static void __secure ls1_fsm_setup(void)
44 {
45 void *dcsr_epu_base = (void *)(CONFIG_SYS_DCSRBAR + EPU_BLOCK_OFFSET);
46 void *dcsr_rcpm_base = (void *)SYS_FSL_DCSR_RCPM_ADDR;
47
48 out_be32(dcsr_rcpm_base + DCSR_RCPM_CSTTACR0, 0x00001001);
49 out_be32(dcsr_rcpm_base + DCSR_RCPM_CG1CR0, 0x00000001);
50
51 fsl_epu_setup((void *)dcsr_epu_base);
52
53 /* Pull MCKE signal low before enabling deep sleep signal in FPGA */
54 out_be32(dcsr_epu_base + EPECR0, 0x5);
55 out_be32(dcsr_epu_base + EPSMCR15, 0x76300000);
56 }
57
ls1_deepsleep_irq_cfg(void)58 static void __secure ls1_deepsleep_irq_cfg(void)
59 {
60 struct ccsr_scfg __iomem *scfg = (void *)CONFIG_SYS_FSL_SCFG_ADDR;
61 struct ccsr_rcpm __iomem *rcpm = (void *)CONFIG_SYS_FSL_RCPM_ADDR;
62 u32 ippdexpcr0, ippdexpcr1, pmcintecr = 0;
63
64 /* Mask interrupts from GIC */
65 out_be32(&rcpm->nfiqoutr, 0x0ffffffff);
66 out_be32(&rcpm->nirqoutr, 0x0ffffffff);
67 /* Mask deep sleep wake-up interrupts while entering deep sleep */
68 out_be32(&rcpm->dsimskr, 0x0ffffffff);
69
70 ippdexpcr0 = in_be32(&rcpm->ippdexpcr0);
71 /*
72 * Workaround of errata A-008646
73 * Errata states that read to register ippdexpcr1 always returns
74 * zero irrespective of what value is written into it. So its value
75 * is first saved to a spare register and then read from it
76 */
77 ippdexpcr1 = in_be32(&scfg->sparecr[7]);
78
79 /*
80 * To allow OCRAM to be used as wakeup source in deep sleep,
81 * do not power it down.
82 */
83 out_be32(&rcpm->ippdexpcr1, ippdexpcr1 | RCPM_IPPDEXPCR1_OCRAM1);
84
85 if (ippdexpcr0 & RCPM_IPPDEXPCR0_ETSEC)
86 pmcintecr |= SCFG_PMCINTECR_ETSECRXG0 |
87 SCFG_PMCINTECR_ETSECRXG1 |
88 SCFG_PMCINTECR_ETSECERRG0 |
89 SCFG_PMCINTECR_ETSECERRG1;
90
91 if (ippdexpcr0 & RCPM_IPPDEXPCR0_GPIO)
92 pmcintecr |= SCFG_PMCINTECR_GPIO;
93
94 if (ippdexpcr1 & RCPM_IPPDEXPCR1_LPUART)
95 pmcintecr |= SCFG_PMCINTECR_LPUART;
96
97 if (ippdexpcr1 & RCPM_IPPDEXPCR1_FLEXTIMER)
98 pmcintecr |= SCFG_PMCINTECR_FTM;
99
100 /* Always set external IRQ pins as wakeup source */
101 pmcintecr |= SCFG_PMCINTECR_IRQ0 | SCFG_PMCINTECR_IRQ1;
102
103 out_be32(&scfg->pmcintlecr, 0);
104 /* Clear PMC interrupt status */
105 out_be32(&scfg->pmcintsr, 0xffffffff);
106 /* Enable wakeup interrupt during deep sleep */
107 out_be32(&scfg->pmcintecr, pmcintecr);
108 }
109
ls1_delay(unsigned int loop)110 static void __secure ls1_delay(unsigned int loop)
111 {
112 while (loop--) {
113 int i = 1000;
114 while (i--)
115 ;
116 }
117 }
118
ls1_start_fsm(void)119 static void __secure ls1_start_fsm(void)
120 {
121 void *dcsr_epu_base = (void *)(CONFIG_SYS_DCSRBAR + EPU_BLOCK_OFFSET);
122 void *ccsr_gic_base = (void *)SYS_FSL_GIC_ADDR;
123 struct ccsr_scfg __iomem *scfg = (void *)CONFIG_SYS_FSL_SCFG_ADDR;
124 struct ccsr_ddr __iomem *ddr = (void *)CONFIG_SYS_FSL_DDR_ADDR;
125
126 /* Set HRSTCR */
127 setbits_be32(&scfg->hrstcr, 0x80000000);
128
129 /* Place DDR controller in self refresh mode */
130 setbits_be32(&ddr->sdram_cfg_2, 0x80000000);
131
132 ls1_delay(2000);
133
134 /* Set EVT4_B to lock the signal MCKE down */
135 out_be32(dcsr_epu_base + EPECR0, 0x0);
136
137 ls1_delay(2000);
138
139 out_be32(ccsr_gic_base + CCSR_GICD_CTLR, 0x0);
140 out_be32(ccsr_gic_base + CCSR_GICC_CTLR, 0x0);
141
142 /* Enable all EPU Counters */
143 setbits_be32(dcsr_epu_base + EPGCR, 0x80000000);
144
145 /* Enable SCU15 */
146 setbits_be32(dcsr_epu_base + EPECR15, 0x90000004);
147
148 /* Enter WFI mode, and EPU FSM will start */
149 __asm__ __volatile__ ("wfi" : : : "memory");
150
151 /* NEVER ENTER HERE */
152 while (1)
153 ;
154 }
155
ls1_deep_sleep(u32 entry_point)156 static void __secure ls1_deep_sleep(u32 entry_point)
157 {
158 struct ccsr_scfg __iomem *scfg = (void *)CONFIG_SYS_FSL_SCFG_ADDR;
159 struct ccsr_gur __iomem *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR;
160 struct ccsr_rcpm __iomem *rcpm = (void *)CONFIG_SYS_FSL_RCPM_ADDR;
161 #ifdef QIXIS_BASE
162 u32 tmp;
163 void *qixis_base = (void *)QIXIS_BASE;
164 #endif
165
166 /* Enable cluster to enter the PCL10 state */
167 out_be32(&scfg->clusterpmcr, SCFG_CLUSTERPMCR_WFIL2EN);
168
169 /* Save the first 128 bytes of DDR data */
170 ls1_save_ddr_head();
171
172 /* Save the kernel resume entry */
173 out_le32(&scfg->sparecr[3], entry_point);
174
175 /* Request to put cluster 0 in PCL10 state */
176 setbits_be32(&rcpm->clpcl10setr, RCPM_CLPCL10SETR_C0);
177
178 /* Setup the registers of the EPU FSM for deep sleep */
179 ls1_fsm_setup();
180
181 #ifdef QIXIS_BASE
182 /* Connect the EVENT button to IRQ in FPGA */
183 tmp = in_8(qixis_base + QIXIS_CTL_SYS);
184 tmp &= ~QIXIS_CTL_SYS_EVTSW_MASK;
185 tmp |= QIXIS_CTL_SYS_EVTSW_IRQ;
186 out_8(qixis_base + QIXIS_CTL_SYS, tmp);
187
188 /* Enable deep sleep signals in FPGA */
189 tmp = in_8(qixis_base + QIXIS_PWR_CTL2);
190 tmp |= QIXIS_PWR_CTL2_PCTL;
191 out_8(qixis_base + QIXIS_PWR_CTL2, tmp);
192
193 /* Pull down PCIe RST# */
194 tmp = in_8(qixis_base + QIXIS_RST_FORCE_3);
195 tmp |= QIXIS_RST_FORCE_3_PCIESLOT1;
196 out_8(qixis_base + QIXIS_RST_FORCE_3, tmp);
197 #endif
198
199 /* Enable Warm Device Reset */
200 setbits_be32(&scfg->dpslpcr, SCFG_DPSLPCR_WDRR_EN);
201 setbits_be32(&gur->crstsr, DCFG_CRSTSR_WDRFR);
202
203 /* Disable QE */
204 setbits_be32(&gur->devdisr, CCSR_DEVDISR1_QE);
205
206 ls1_deepsleep_irq_cfg();
207
208 psci_v7_flush_dcache_all();
209
210 ls1_start_fsm();
211 }
212
213 #else
ls1_sleep(void)214 static void __secure ls1_sleep(void)
215 {
216 struct ccsr_scfg __iomem *scfg = (void *)CONFIG_SYS_FSL_SCFG_ADDR;
217 struct ccsr_rcpm __iomem *rcpm = (void *)CONFIG_SYS_FSL_RCPM_ADDR;
218
219 #ifdef QIXIS_BASE
220 u32 tmp;
221 void *qixis_base = (void *)QIXIS_BASE;
222
223 /* Connect the EVENT button to IRQ in FPGA */
224 tmp = in_8(qixis_base + QIXIS_CTL_SYS);
225 tmp &= ~QIXIS_CTL_SYS_EVTSW_MASK;
226 tmp |= QIXIS_CTL_SYS_EVTSW_IRQ;
227 out_8(qixis_base + QIXIS_CTL_SYS, tmp);
228 #endif
229
230 /* Enable cluster to enter the PCL10 state */
231 out_be32(&scfg->clusterpmcr, SCFG_CLUSTERPMCR_WFIL2EN);
232
233 setbits_be32(&rcpm->powmgtcsr, RCPM_POWMGTCSR_LPM20_REQ);
234
235 __asm__ __volatile__ ("wfi" : : : "memory");
236 }
237 #endif
238
ls1_system_suspend(u32 fn,u32 entry_point,u32 context_id)239 void __secure ls1_system_suspend(u32 fn, u32 entry_point, u32 context_id)
240 {
241 #ifdef CONFIG_LS1_DEEP_SLEEP
242 ls1_deep_sleep(entry_point);
243 #else
244 ls1_sleep();
245 #endif
246 }
247