1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Copyright 2009-2012 Freescale Semiconductor, Inc.
4 *
5 * This file is derived from arch/powerpc/cpu/mpc85xx/cpu.c and
6 * arch/powerpc/cpu/mpc86xx/cpu.c. Basically this file contains
7 * cpu specific common code for 85xx/86xx processors.
8 */
9
10 #include <config.h>
11 #include <common.h>
12 #include <command.h>
13 #include <cpu_func.h>
14 #include <init.h>
15 #include <net.h>
16 #include <tsec.h>
17 #include <fm_eth.h>
18 #include <netdev.h>
19 #include <asm/cache.h>
20 #include <asm/global_data.h>
21 #include <asm/io.h>
22 #include <vsc9953.h>
23
24 DECLARE_GLOBAL_DATA_PTR;
25
26 static struct cpu_type cpu_type_list[] = {
27 #if defined(CONFIG_MPC85xx)
28 CPU_TYPE_ENTRY(8533, 8533, 1),
29 CPU_TYPE_ENTRY(8535, 8535, 1),
30 CPU_TYPE_ENTRY(8536, 8536, 1),
31 CPU_TYPE_ENTRY(8540, 8540, 1),
32 CPU_TYPE_ENTRY(8541, 8541, 1),
33 CPU_TYPE_ENTRY(8543, 8543, 1),
34 CPU_TYPE_ENTRY(8544, 8544, 1),
35 CPU_TYPE_ENTRY(8545, 8545, 1),
36 CPU_TYPE_ENTRY(8547, 8547, 1),
37 CPU_TYPE_ENTRY(8548, 8548, 1),
38 CPU_TYPE_ENTRY(8555, 8555, 1),
39 CPU_TYPE_ENTRY(8560, 8560, 1),
40 CPU_TYPE_ENTRY(8567, 8567, 1),
41 CPU_TYPE_ENTRY(8568, 8568, 1),
42 CPU_TYPE_ENTRY(8569, 8569, 1),
43 CPU_TYPE_ENTRY(8572, 8572, 2),
44 CPU_TYPE_ENTRY(P1010, P1010, 1),
45 CPU_TYPE_ENTRY(P1011, P1011, 1),
46 CPU_TYPE_ENTRY(P1012, P1012, 1),
47 CPU_TYPE_ENTRY(P1013, P1013, 1),
48 CPU_TYPE_ENTRY(P1014, P1014, 1),
49 CPU_TYPE_ENTRY(P1017, P1017, 1),
50 CPU_TYPE_ENTRY(P1020, P1020, 2),
51 CPU_TYPE_ENTRY(P1021, P1021, 2),
52 CPU_TYPE_ENTRY(P1022, P1022, 2),
53 CPU_TYPE_ENTRY(P1023, P1023, 2),
54 CPU_TYPE_ENTRY(P1024, P1024, 2),
55 CPU_TYPE_ENTRY(P1025, P1025, 2),
56 CPU_TYPE_ENTRY(P2010, P2010, 1),
57 CPU_TYPE_ENTRY(P2020, P2020, 2),
58 CPU_TYPE_ENTRY(P2040, P2040, 4),
59 CPU_TYPE_ENTRY(P2041, P2041, 4),
60 CPU_TYPE_ENTRY(P3041, P3041, 4),
61 CPU_TYPE_ENTRY(P4040, P4040, 4),
62 CPU_TYPE_ENTRY(P4080, P4080, 8),
63 CPU_TYPE_ENTRY(P5010, P5010, 1),
64 CPU_TYPE_ENTRY(P5020, P5020, 2),
65 CPU_TYPE_ENTRY(P5021, P5021, 2),
66 CPU_TYPE_ENTRY(P5040, P5040, 4),
67 CPU_TYPE_ENTRY(T4240, T4240, 0),
68 CPU_TYPE_ENTRY(T4120, T4120, 0),
69 CPU_TYPE_ENTRY(T4160, T4160, 0),
70 CPU_TYPE_ENTRY(T4080, T4080, 4),
71 CPU_TYPE_ENTRY(B4860, B4860, 0),
72 CPU_TYPE_ENTRY(G4860, G4860, 0),
73 CPU_TYPE_ENTRY(B4440, B4440, 0),
74 CPU_TYPE_ENTRY(B4460, B4460, 0),
75 CPU_TYPE_ENTRY(G4440, G4440, 0),
76 CPU_TYPE_ENTRY(B4420, B4420, 0),
77 CPU_TYPE_ENTRY(B4220, B4220, 0),
78 CPU_TYPE_ENTRY(T1040, T1040, 0),
79 CPU_TYPE_ENTRY(T1041, T1041, 0),
80 CPU_TYPE_ENTRY(T1042, T1042, 0),
81 CPU_TYPE_ENTRY(T1020, T1020, 0),
82 CPU_TYPE_ENTRY(T1021, T1021, 0),
83 CPU_TYPE_ENTRY(T1022, T1022, 0),
84 CPU_TYPE_ENTRY(T1024, T1024, 0),
85 CPU_TYPE_ENTRY(T1023, T1023, 0),
86 CPU_TYPE_ENTRY(T1014, T1014, 0),
87 CPU_TYPE_ENTRY(T1013, T1013, 0),
88 CPU_TYPE_ENTRY(T2080, T2080, 0),
89 CPU_TYPE_ENTRY(T2081, T2081, 0),
90 CPU_TYPE_ENTRY(BSC9130, 9130, 1),
91 CPU_TYPE_ENTRY(BSC9131, 9131, 1),
92 CPU_TYPE_ENTRY(BSC9132, 9132, 2),
93 CPU_TYPE_ENTRY(BSC9232, 9232, 2),
94 CPU_TYPE_ENTRY(C291, C291, 1),
95 CPU_TYPE_ENTRY(C292, C292, 1),
96 CPU_TYPE_ENTRY(C293, C293, 1),
97 #elif defined(CONFIG_MPC86xx)
98 CPU_TYPE_ENTRY(8610, 8610, 1),
99 CPU_TYPE_ENTRY(8641, 8641, 2),
100 CPU_TYPE_ENTRY(8641D, 8641D, 2),
101 #endif
102 };
103
104 #ifdef CONFIG_SYS_FSL_QORIQ_CHASSIS2
init_type(u32 cluster,int init_id)105 static inline u32 init_type(u32 cluster, int init_id)
106 {
107 ccsr_gur_t *gur = (void __iomem *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
108 u32 idx = (cluster >> (init_id * 8)) & TP_CLUSTER_INIT_MASK;
109 u32 type = in_be32(&gur->tp_ityp[idx]);
110
111 if (type & TP_ITYP_AV)
112 return type;
113
114 return 0;
115 }
116
compute_ppc_cpumask(void)117 u32 compute_ppc_cpumask(void)
118 {
119 ccsr_gur_t *gur = (void __iomem *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
120 int i = 0, count = 0;
121 u32 cluster, type, mask = 0;
122
123 do {
124 int j;
125 cluster = in_be32(&gur->tp_cluster[i].lower);
126 for (j = 0; j < TP_INIT_PER_CLUSTER; j++) {
127 type = init_type(cluster, j);
128 if (type) {
129 if (TP_ITYP_TYPE(type) == TP_ITYP_TYPE_PPC)
130 mask |= 1 << count;
131 count++;
132 }
133 }
134 i++;
135 } while ((cluster & TP_CLUSTER_EOC) != TP_CLUSTER_EOC);
136
137 return mask;
138 }
139
140 #ifdef CONFIG_HETROGENOUS_CLUSTERS
compute_dsp_cpumask(void)141 u32 compute_dsp_cpumask(void)
142 {
143 ccsr_gur_t *gur = (void __iomem *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
144 int i = CONFIG_DSP_CLUSTER_START, count = 0;
145 u32 cluster, type, dsp_mask = 0;
146
147 do {
148 int j;
149 cluster = in_be32(&gur->tp_cluster[i].lower);
150 for (j = 0; j < TP_INIT_PER_CLUSTER; j++) {
151 type = init_type(cluster, j);
152 if (type) {
153 if (TP_ITYP_TYPE(type) == TP_ITYP_TYPE_SC)
154 dsp_mask |= 1 << count;
155 count++;
156 }
157 }
158 i++;
159 } while ((cluster & TP_CLUSTER_EOC) != TP_CLUSTER_EOC);
160
161 return dsp_mask;
162 }
163
fsl_qoriq_dsp_core_to_cluster(unsigned int core)164 int fsl_qoriq_dsp_core_to_cluster(unsigned int core)
165 {
166 ccsr_gur_t *gur = (void __iomem *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
167 int count = 0, i = CONFIG_DSP_CLUSTER_START;
168 u32 cluster;
169
170 do {
171 int j;
172 cluster = in_be32(&gur->tp_cluster[i].lower);
173 for (j = 0; j < TP_INIT_PER_CLUSTER; j++) {
174 if (init_type(cluster, j)) {
175 if (count == core)
176 return i;
177 count++;
178 }
179 }
180 i++;
181 } while ((cluster & TP_CLUSTER_EOC) != TP_CLUSTER_EOC);
182
183 return -1; /* cannot identify the cluster */
184 }
185 #endif
186
fsl_qoriq_core_to_cluster(unsigned int core)187 int fsl_qoriq_core_to_cluster(unsigned int core)
188 {
189 ccsr_gur_t *gur = (void __iomem *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
190 int i = 0, count = 0;
191 u32 cluster;
192
193 do {
194 int j;
195 cluster = in_be32(&gur->tp_cluster[i].lower);
196 for (j = 0; j < TP_INIT_PER_CLUSTER; j++) {
197 if (init_type(cluster, j)) {
198 if (count == core)
199 return i;
200 count++;
201 }
202 }
203 i++;
204 } while ((cluster & TP_CLUSTER_EOC) != TP_CLUSTER_EOC);
205
206 return -1; /* cannot identify the cluster */
207 }
208
209 #else /* CONFIG_SYS_FSL_QORIQ_CHASSIS2 */
210 /*
211 * Before chassis genenration 2, the cpumask should be hard-coded.
212 * In case of cpu type unknown or cpumask unset, use 1 as fail save.
213 */
214 #define compute_ppc_cpumask() 1
215 #define fsl_qoriq_core_to_cluster(x) x
216 #endif /* CONFIG_SYS_FSL_QORIQ_CHASSIS2 */
217
218 static struct cpu_type cpu_type_unknown = CPU_TYPE_ENTRY(Unknown, Unknown, 0);
219
identify_cpu(u32 ver)220 struct cpu_type *identify_cpu(u32 ver)
221 {
222 int i;
223 for (i = 0; i < ARRAY_SIZE(cpu_type_list); i++) {
224 if (cpu_type_list[i].soc_ver == ver)
225 return &cpu_type_list[i];
226 }
227 return &cpu_type_unknown;
228 }
229
230 #define MPC8xxx_PICFRR_NCPU_MASK 0x00001f00
231 #define MPC8xxx_PICFRR_NCPU_SHIFT 8
232
233 /*
234 * Return a 32-bit mask indicating which cores are present on this SOC.
235 */
cpu_mask(void)236 __weak u32 cpu_mask(void)
237 {
238 ccsr_pic_t __iomem *pic = (void *)CONFIG_SYS_MPC8xxx_PIC_ADDR;
239 struct cpu_type *cpu = gd->arch.cpu;
240
241 /* better to query feature reporting register than just assume 1 */
242 if (cpu == &cpu_type_unknown)
243 return ((in_be32(&pic->frr) & MPC8xxx_PICFRR_NCPU_MASK) >>
244 MPC8xxx_PICFRR_NCPU_SHIFT) + 1;
245
246 if (cpu->num_cores == 0)
247 return compute_ppc_cpumask();
248
249 return cpu->mask;
250 }
251
252 #ifdef CONFIG_HETROGENOUS_CLUSTERS
cpu_dsp_mask(void)253 __weak u32 cpu_dsp_mask(void)
254 {
255 ccsr_pic_t __iomem *pic = (void *)CONFIG_SYS_MPC8xxx_PIC_ADDR;
256 struct cpu_type *cpu = gd->arch.cpu;
257
258 /* better to query feature reporting register than just assume 1 */
259 if (cpu == &cpu_type_unknown)
260 return ((in_be32(&pic->frr) & MPC8xxx_PICFRR_NCPU_MASK) >>
261 MPC8xxx_PICFRR_NCPU_SHIFT) + 1;
262
263 if (cpu->dsp_num_cores == 0)
264 return compute_dsp_cpumask();
265
266 return cpu->dsp_mask;
267 }
268
269 /*
270 * Return the number of SC/DSP cores on this SOC.
271 */
cpu_num_dspcores(void)272 __weak int cpu_num_dspcores(void)
273 {
274 struct cpu_type *cpu = gd->arch.cpu;
275
276 /*
277 * Report # of cores in terms of the cpu_mask if we haven't
278 * figured out how many there are yet
279 */
280 if (cpu->dsp_num_cores == 0)
281 return hweight32(cpu_dsp_mask());
282
283 return cpu->dsp_num_cores;
284 }
285 #endif
286
287 /*
288 * Return the number of PPC cores on this SOC.
289 */
cpu_numcores(void)290 __weak int cpu_numcores(void)
291 {
292 struct cpu_type *cpu = gd->arch.cpu;
293
294 /*
295 * Report # of cores in terms of the cpu_mask if we haven't
296 * figured out how many there are yet
297 */
298 if (cpu->num_cores == 0)
299 return hweight32(cpu_mask());
300
301 return cpu->num_cores;
302 }
303
304
305 /*
306 * Check if the given core ID is valid
307 *
308 * Returns zero if it isn't, 1 if it is.
309 */
is_core_valid(unsigned int core)310 int is_core_valid(unsigned int core)
311 {
312 return !!((1 << core) & cpu_mask());
313 }
314
arch_cpu_init(void)315 int arch_cpu_init(void)
316 {
317 uint svr;
318 uint ver;
319
320 svr = get_svr();
321 ver = SVR_SOC_VER(svr);
322
323 gd->arch.cpu = identify_cpu(ver);
324
325 return 0;
326 }
327
328 /* Once in memory, compute mask & # cores once and save them off */
fixup_cpu(void)329 int fixup_cpu(void)
330 {
331 struct cpu_type *cpu = gd->arch.cpu;
332
333 if (cpu->num_cores == 0) {
334 cpu->mask = cpu_mask();
335 cpu->num_cores = cpu_numcores();
336 }
337
338 #ifdef CONFIG_HETROGENOUS_CLUSTERS
339 if (cpu->dsp_num_cores == 0) {
340 cpu->dsp_mask = cpu_dsp_mask();
341 cpu->dsp_num_cores = cpu_num_dspcores();
342 }
343 #endif
344 return 0;
345 }
346
347 #ifndef CONFIG_DM_ETH
348 /*
349 * Initializes on-chip ethernet controllers.
350 * to override, implement board_eth_init()
351 */
cpu_eth_init(struct bd_info * bis)352 int cpu_eth_init(struct bd_info *bis)
353 {
354 #if defined(CONFIG_ETHER_ON_FCC)
355 fec_initialize(bis);
356 #endif
357
358 #if defined(CONFIG_UEC_ETH)
359 uec_standard_init(bis);
360 #endif
361
362 #if defined(CONFIG_TSEC_ENET) || defined(CONFIG_MPC85XX_FEC)
363 tsec_standard_init(bis);
364 #endif
365
366 #ifdef CONFIG_FMAN_ENET
367 fm_standard_init(bis);
368 #endif
369
370 #ifdef CONFIG_VSC9953
371 vsc9953_init(bis);
372 #endif
373 return 0;
374 }
375 #endif
376