1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Driver for the TWSI (i2c) controller found on the Marvell
4 * orion5x and kirkwood SoC families.
5 *
6 * Author: Albert Aribaud <albert.u.boot@aribaud.net>
7 * Copyright (c) 2010 Albert Aribaud.
8 */
9
10 #include <common.h>
11 #include <i2c.h>
12 #include <log.h>
13 #include <asm/global_data.h>
14 #include <linux/delay.h>
15 #include <linux/errno.h>
16 #include <asm/io.h>
17 #include <linux/bitops.h>
18 #include <linux/compat.h>
19 #if CONFIG_IS_ENABLED(DM_I2C)
20 #include <dm.h>
21 #endif
22
23 DECLARE_GLOBAL_DATA_PTR;
24
25 /*
26 * Include a file that will provide CONFIG_I2C_MVTWSI_BASE*, and possibly other
27 * settings
28 */
29
30 #if !CONFIG_IS_ENABLED(DM_I2C)
31 #if defined(CONFIG_ARCH_ORION5X)
32 #include <asm/arch/orion5x.h>
33 #elif (defined(CONFIG_ARCH_KIRKWOOD) || defined(CONFIG_ARCH_MVEBU))
34 #include <asm/arch/soc.h>
35 #elif defined(CONFIG_ARCH_SUNXI)
36 #include <asm/arch/i2c.h>
37 #else
38 #error Driver mvtwsi not supported by SoC or board
39 #endif
40 #endif /* CONFIG_DM_I2C */
41
42 /*
43 * On SUNXI, we get CONFIG_SYS_TCLK from this include, so we want to
44 * always have it.
45 */
46 #if CONFIG_IS_ENABLED(DM_I2C) && defined(CONFIG_ARCH_SUNXI)
47 #include <asm/arch/i2c.h>
48 #endif
49
50 /*
51 * TWSI register structure
52 */
53
54 #ifdef CONFIG_ARCH_SUNXI
55
56 struct mvtwsi_registers {
57 u32 slave_address;
58 u32 xtnd_slave_addr;
59 u32 data;
60 u32 control;
61 u32 status;
62 u32 baudrate;
63 u32 soft_reset;
64 u32 debug; /* Dummy field for build compatibility with mvebu */
65 };
66
67 #else
68
69 struct mvtwsi_registers {
70 u32 slave_address;
71 u32 data;
72 u32 control;
73 union {
74 u32 status; /* When reading */
75 u32 baudrate; /* When writing */
76 };
77 u32 xtnd_slave_addr;
78 u32 reserved0[2];
79 u32 soft_reset;
80 u32 reserved1[27];
81 u32 debug;
82 };
83
84 #endif
85
86 #if CONFIG_IS_ENABLED(DM_I2C)
87 struct mvtwsi_i2c_dev {
88 /* TWSI Register base for the device */
89 struct mvtwsi_registers *base;
90 /* Number of the device (determined from cell-index property) */
91 int index;
92 /* The I2C slave address for the device */
93 u8 slaveadd;
94 /* The configured I2C speed in Hz */
95 uint speed;
96 /* The current length of a clock period (depending on speed) */
97 uint tick;
98 };
99 #endif /* CONFIG_DM_I2C */
100
101 /*
102 * enum mvtwsi_ctrl_register_fields - Bit masks for flags in the control
103 * register
104 */
105 enum mvtwsi_ctrl_register_fields {
106 /* Acknowledge bit */
107 MVTWSI_CONTROL_ACK = 0x00000004,
108 /* Interrupt flag */
109 MVTWSI_CONTROL_IFLG = 0x00000008,
110 /* Stop bit */
111 MVTWSI_CONTROL_STOP = 0x00000010,
112 /* Start bit */
113 MVTWSI_CONTROL_START = 0x00000020,
114 /* I2C enable */
115 MVTWSI_CONTROL_TWSIEN = 0x00000040,
116 /* Interrupt enable */
117 MVTWSI_CONTROL_INTEN = 0x00000080,
118 };
119
120 /*
121 * On sun6i and newer, IFLG is a write-clear bit, which is cleared by writing 1;
122 * on other platforms, it is a normal r/w bit, which is cleared by writing 0.
123 */
124
125 #if defined(CONFIG_SUNXI_GEN_SUN6I) || defined(CONFIG_SUN50I_GEN_H6)
126 #define MVTWSI_CONTROL_CLEAR_IFLG 0x00000008
127 #else
128 #define MVTWSI_CONTROL_CLEAR_IFLG 0x00000000
129 #endif
130
131 /*
132 * enum mvstwsi_status_values - Possible values of I2C controller's status
133 * register
134 *
135 * Only those statuses expected in normal master operation on
136 * non-10-bit-address devices are specified.
137 *
138 * Every status that's unexpected during normal operation (bus errors,
139 * arbitration losses, missing ACKs...) is passed back to the caller as an error
140 * code.
141 */
142 enum mvstwsi_status_values {
143 /* START condition transmitted */
144 MVTWSI_STATUS_START = 0x08,
145 /* Repeated START condition transmitted */
146 MVTWSI_STATUS_REPEATED_START = 0x10,
147 /* Address + write bit transmitted, ACK received */
148 MVTWSI_STATUS_ADDR_W_ACK = 0x18,
149 /* Data transmitted, ACK received */
150 MVTWSI_STATUS_DATA_W_ACK = 0x28,
151 /* Address + read bit transmitted, ACK received */
152 MVTWSI_STATUS_ADDR_R_ACK = 0x40,
153 /* Address + read bit transmitted, ACK not received */
154 MVTWSI_STATUS_ADDR_R_NAK = 0x48,
155 /* Data received, ACK transmitted */
156 MVTWSI_STATUS_DATA_R_ACK = 0x50,
157 /* Data received, ACK not transmitted */
158 MVTWSI_STATUS_DATA_R_NAK = 0x58,
159 /* No relevant status */
160 MVTWSI_STATUS_IDLE = 0xF8,
161 };
162
163 /*
164 * enum mvstwsi_ack_flags - Determine whether a read byte should be
165 * acknowledged or not.
166 */
167 enum mvtwsi_ack_flags {
168 /* Send NAK after received byte */
169 MVTWSI_READ_NAK = 0,
170 /* Send ACK after received byte */
171 MVTWSI_READ_ACK = 1,
172 };
173
174 /*
175 * calc_tick() - Calculate the duration of a clock cycle from the I2C speed
176 *
177 * @speed: The speed in Hz to calculate the clock cycle duration for.
178 * @return The duration of a clock cycle in ns.
179 */
calc_tick(uint speed)180 inline uint calc_tick(uint speed)
181 {
182 /* One tick = the duration of a period at the specified speed in ns (we
183 * add 100 ns to be on the safe side) */
184 return (1000000000u / speed) + 100;
185 }
186
187 #if !CONFIG_IS_ENABLED(DM_I2C)
188
189 /*
190 * twsi_get_base() - Get controller register base for specified adapter
191 *
192 * @adap: Adapter to get the register base for.
193 * @return Register base for the specified adapter.
194 */
twsi_get_base(struct i2c_adapter * adap)195 static struct mvtwsi_registers *twsi_get_base(struct i2c_adapter *adap)
196 {
197 switch (adap->hwadapnr) {
198 #ifdef CONFIG_I2C_MVTWSI_BASE0
199 case 0:
200 return (struct mvtwsi_registers *)CONFIG_I2C_MVTWSI_BASE0;
201 #endif
202 #ifdef CONFIG_I2C_MVTWSI_BASE1
203 case 1:
204 return (struct mvtwsi_registers *)CONFIG_I2C_MVTWSI_BASE1;
205 #endif
206 #ifdef CONFIG_I2C_MVTWSI_BASE2
207 case 2:
208 return (struct mvtwsi_registers *)CONFIG_I2C_MVTWSI_BASE2;
209 #endif
210 #ifdef CONFIG_I2C_MVTWSI_BASE3
211 case 3:
212 return (struct mvtwsi_registers *)CONFIG_I2C_MVTWSI_BASE3;
213 #endif
214 #ifdef CONFIG_I2C_MVTWSI_BASE4
215 case 4:
216 return (struct mvtwsi_registers *)CONFIG_I2C_MVTWSI_BASE4;
217 #endif
218 #ifdef CONFIG_I2C_MVTWSI_BASE5
219 case 5:
220 return (struct mvtwsi_registers *)CONFIG_I2C_MVTWSI_BASE5;
221 #endif
222 default:
223 printf("Missing mvtwsi controller %d base\n", adap->hwadapnr);
224 break;
225 }
226
227 return NULL;
228 }
229 #endif
230
231 /*
232 * enum mvtwsi_error_class - types of I2C errors
233 */
234 enum mvtwsi_error_class {
235 /* The controller returned a different status than expected */
236 MVTWSI_ERROR_WRONG_STATUS = 0x01,
237 /* The controller timed out */
238 MVTWSI_ERROR_TIMEOUT = 0x02,
239 };
240
241 /*
242 * mvtwsi_error() - Build I2C return code from error information
243 *
244 * For debugging purposes, this function packs some information of an occurred
245 * error into a return code. These error codes are returned from I2C API
246 * functions (i2c_{read,write}, dm_i2c_{read,write}, etc.).
247 *
248 * @ec: The error class of the error (enum mvtwsi_error_class).
249 * @lc: The last value of the control register.
250 * @ls: The last value of the status register.
251 * @es: The expected value of the status register.
252 * @return The generated error code.
253 */
mvtwsi_error(uint ec,uint lc,uint ls,uint es)254 inline uint mvtwsi_error(uint ec, uint lc, uint ls, uint es)
255 {
256 return ((ec << 24) & 0xFF000000)
257 | ((lc << 16) & 0x00FF0000)
258 | ((ls << 8) & 0x0000FF00)
259 | (es & 0xFF);
260 }
261
262 /*
263 * twsi_wait() - Wait for I2C bus interrupt flag and check status, or time out.
264 *
265 * @return Zero if status is as expected, or a non-zero code if either a time
266 * out occurred, or the status was not the expected one.
267 */
twsi_wait(struct mvtwsi_registers * twsi,int expected_status,uint tick)268 static int twsi_wait(struct mvtwsi_registers *twsi, int expected_status,
269 uint tick)
270 {
271 int control, status;
272 int timeout = 1000;
273
274 do {
275 control = readl(&twsi->control);
276 if (control & MVTWSI_CONTROL_IFLG) {
277 /*
278 * On Armada 38x it seems that the controller works as
279 * if it first set the MVTWSI_CONTROL_IFLAG in the
280 * control register and only after that it changed the
281 * status register.
282 * This sometimes caused weird bugs which only appeared
283 * on selected I2C speeds and even then only sometimes.
284 * We therefore add here a simple ndealy(100), which
285 * seems to fix this weird bug.
286 */
287 ndelay(100);
288 status = readl(&twsi->status);
289 if (status == expected_status)
290 return 0;
291 else
292 return mvtwsi_error(
293 MVTWSI_ERROR_WRONG_STATUS,
294 control, status, expected_status);
295 }
296 ndelay(tick); /* One clock cycle */
297 } while (timeout--);
298 status = readl(&twsi->status);
299 return mvtwsi_error(MVTWSI_ERROR_TIMEOUT, control, status,
300 expected_status);
301 }
302
303 /*
304 * twsi_start() - Assert a START condition on the bus.
305 *
306 * This function is used in both single I2C transactions and inside
307 * back-to-back transactions (repeated starts).
308 *
309 * @twsi: The MVTWSI register structure to use.
310 * @expected_status: The I2C bus status expected to be asserted after the
311 * operation completion.
312 * @tick: The duration of a clock cycle at the current I2C speed.
313 * @return Zero if status is as expected, or a non-zero code if either a time
314 * out occurred or the status was not the expected one.
315 */
twsi_start(struct mvtwsi_registers * twsi,int expected_status,uint tick)316 static int twsi_start(struct mvtwsi_registers *twsi, int expected_status,
317 uint tick)
318 {
319 /* Assert START */
320 writel(MVTWSI_CONTROL_TWSIEN | MVTWSI_CONTROL_START |
321 MVTWSI_CONTROL_CLEAR_IFLG, &twsi->control);
322 /* Wait for controller to process START */
323 return twsi_wait(twsi, expected_status, tick);
324 }
325
326 /*
327 * twsi_send() - Send a byte on the I2C bus.
328 *
329 * The byte may be part of an address byte or data.
330 *
331 * @twsi: The MVTWSI register structure to use.
332 * @byte: The byte to send.
333 * @expected_status: The I2C bus status expected to be asserted after the
334 * operation completion.
335 * @tick: The duration of a clock cycle at the current I2C speed.
336 * @return Zero if status is as expected, or a non-zero code if either a time
337 * out occurred or the status was not the expected one.
338 */
twsi_send(struct mvtwsi_registers * twsi,u8 byte,int expected_status,uint tick)339 static int twsi_send(struct mvtwsi_registers *twsi, u8 byte,
340 int expected_status, uint tick)
341 {
342 /* Write byte to data register for sending */
343 writel(byte, &twsi->data);
344 /* Clear any pending interrupt -- that will cause sending */
345 writel(MVTWSI_CONTROL_TWSIEN | MVTWSI_CONTROL_CLEAR_IFLG,
346 &twsi->control);
347 /* Wait for controller to receive byte, and check ACK */
348 return twsi_wait(twsi, expected_status, tick);
349 }
350
351 /*
352 * twsi_recv() - Receive a byte on the I2C bus.
353 *
354 * The static variable mvtwsi_control_flags controls whether we ack or nak.
355 *
356 * @twsi: The MVTWSI register structure to use.
357 * @byte: The byte to send.
358 * @ack_flag: Flag that determines whether the received byte should
359 * be acknowledged by the controller or not (sent ACK/NAK).
360 * @tick: The duration of a clock cycle at the current I2C speed.
361 * @return Zero if status is as expected, or a non-zero code if either a time
362 * out occurred or the status was not the expected one.
363 */
twsi_recv(struct mvtwsi_registers * twsi,u8 * byte,int ack_flag,uint tick)364 static int twsi_recv(struct mvtwsi_registers *twsi, u8 *byte, int ack_flag,
365 uint tick)
366 {
367 int expected_status, status, control;
368
369 /* Compute expected status based on passed ACK flag */
370 expected_status = ack_flag ? MVTWSI_STATUS_DATA_R_ACK :
371 MVTWSI_STATUS_DATA_R_NAK;
372 /* Acknowledge *previous state*, and launch receive */
373 control = MVTWSI_CONTROL_TWSIEN;
374 control |= ack_flag == MVTWSI_READ_ACK ? MVTWSI_CONTROL_ACK : 0;
375 writel(control | MVTWSI_CONTROL_CLEAR_IFLG, &twsi->control);
376 /* Wait for controller to receive byte, and assert ACK or NAK */
377 status = twsi_wait(twsi, expected_status, tick);
378 /* If we did receive the expected byte, store it */
379 if (status == 0)
380 *byte = readl(&twsi->data);
381 return status;
382 }
383
384 /*
385 * twsi_stop() - Assert a STOP condition on the bus.
386 *
387 * This function is also used to force the bus back to idle state (SDA =
388 * SCL = 1).
389 *
390 * @twsi: The MVTWSI register structure to use.
391 * @tick: The duration of a clock cycle at the current I2C speed.
392 * @return Zero if the operation succeeded, or a non-zero code if a time out
393 * occurred.
394 */
twsi_stop(struct mvtwsi_registers * twsi,uint tick)395 static int twsi_stop(struct mvtwsi_registers *twsi, uint tick)
396 {
397 int control, stop_status;
398 int status = 0;
399 int timeout = 1000;
400
401 /* Assert STOP */
402 control = MVTWSI_CONTROL_TWSIEN | MVTWSI_CONTROL_STOP;
403 writel(control | MVTWSI_CONTROL_CLEAR_IFLG, &twsi->control);
404 /* Wait for IDLE; IFLG won't rise, so we can't use twsi_wait() */
405 do {
406 stop_status = readl(&twsi->status);
407 if (stop_status == MVTWSI_STATUS_IDLE)
408 break;
409 ndelay(tick); /* One clock cycle */
410 } while (timeout--);
411 control = readl(&twsi->control);
412 if (stop_status != MVTWSI_STATUS_IDLE)
413 status = mvtwsi_error(MVTWSI_ERROR_TIMEOUT,
414 control, status, MVTWSI_STATUS_IDLE);
415 return status;
416 }
417
418 /*
419 * twsi_calc_freq() - Compute I2C frequency depending on m and n parameters.
420 *
421 * @n: Parameter 'n' for the frequency calculation algorithm.
422 * @m: Parameter 'm' for the frequency calculation algorithm.
423 * @return The I2C frequency corresponding to the passed m and n parameters.
424 */
twsi_calc_freq(const int n,const int m)425 static uint twsi_calc_freq(const int n, const int m)
426 {
427 #ifdef CONFIG_ARCH_SUNXI
428 return CONFIG_SYS_TCLK / (10 * (m + 1) * (1 << n));
429 #else
430 return CONFIG_SYS_TCLK / (10 * (m + 1) * (2 << n));
431 #endif
432 }
433
434 /*
435 * twsi_reset() - Reset the I2C controller.
436 *
437 * Resetting the controller also resets the baud rate and slave address, hence
438 * they must be re-established after the reset.
439 *
440 * @twsi: The MVTWSI register structure to use.
441 */
twsi_reset(struct mvtwsi_registers * twsi)442 static void twsi_reset(struct mvtwsi_registers *twsi)
443 {
444 /* Reset controller */
445 writel(0, &twsi->soft_reset);
446 /* Wait 2 ms -- this is what the Marvell LSP does */
447 udelay(20000);
448 }
449
450 /*
451 * __twsi_i2c_set_bus_speed() - Set the speed of the I2C controller.
452 *
453 * This function sets baud rate to the highest possible value that does not
454 * exceed the requested rate.
455 *
456 * @twsi: The MVTWSI register structure to use.
457 * @requested_speed: The desired frequency the controller should run at
458 * in Hz.
459 * @return The actual frequency the controller was configured to.
460 */
__twsi_i2c_set_bus_speed(struct mvtwsi_registers * twsi,uint requested_speed)461 static uint __twsi_i2c_set_bus_speed(struct mvtwsi_registers *twsi,
462 uint requested_speed)
463 {
464 uint tmp_speed, highest_speed, n, m;
465 uint baud = 0x44; /* Baud rate after controller reset */
466
467 highest_speed = 0;
468 /* Successively try m, n combinations, and use the combination
469 * resulting in the largest speed that's not above the requested
470 * speed */
471 for (n = 0; n < 8; n++) {
472 for (m = 0; m < 16; m++) {
473 tmp_speed = twsi_calc_freq(n, m);
474 if ((tmp_speed <= requested_speed) &&
475 (tmp_speed > highest_speed)) {
476 highest_speed = tmp_speed;
477 baud = (m << 3) | n;
478 }
479 }
480 }
481 writel(baud, &twsi->baudrate);
482
483 /* Wait for controller for one tick */
484 #if CONFIG_IS_ENABLED(DM_I2C)
485 ndelay(calc_tick(highest_speed));
486 #else
487 ndelay(10000);
488 #endif
489 return highest_speed;
490 }
491
492 /*
493 * __twsi_i2c_init() - Initialize the I2C controller.
494 *
495 * @twsi: The MVTWSI register structure to use.
496 * @speed: The initial frequency the controller should run at
497 * in Hz.
498 * @slaveadd: The I2C address to be set for the I2C master.
499 * @actual_speed: A output parameter that receives the actual frequency
500 * in Hz the controller was set to by the function.
501 * @return Zero if the operation succeeded, or a non-zero code if a time out
502 * occurred.
503 */
__twsi_i2c_init(struct mvtwsi_registers * twsi,int speed,int slaveadd,uint * actual_speed)504 static void __twsi_i2c_init(struct mvtwsi_registers *twsi, int speed,
505 int slaveadd, uint *actual_speed)
506 {
507 uint tmp_speed;
508
509 /* Reset controller */
510 twsi_reset(twsi);
511 /* Set speed */
512 tmp_speed = __twsi_i2c_set_bus_speed(twsi, speed);
513 if (actual_speed)
514 *actual_speed = tmp_speed;
515 /* Set slave address; even though we don't use it */
516 writel(slaveadd, &twsi->slave_address);
517 writel(0, &twsi->xtnd_slave_addr);
518 /* Assert STOP, but don't care for the result */
519 #if CONFIG_IS_ENABLED(DM_I2C)
520 (void) twsi_stop(twsi, calc_tick(*actual_speed));
521 #else
522 (void) twsi_stop(twsi, 10000);
523 #endif
524 }
525
526 /*
527 * i2c_begin() - Start a I2C transaction.
528 *
529 * Begin a I2C transaction with a given expected start status and chip address.
530 * A START is asserted, and the address byte is sent to the I2C controller. The
531 * expected address status will be derived from the direction bit (bit 0) of
532 * the address byte.
533 *
534 * @twsi: The MVTWSI register structure to use.
535 * @expected_start_status: The I2C status the controller is expected to
536 * assert after the address byte was sent.
537 * @addr: The address byte to be sent.
538 * @tick: The duration of a clock cycle at the current
539 * I2C speed.
540 * @return Zero if the operation succeeded, or a non-zero code if a time out or
541 * unexpected I2C status occurred.
542 */
i2c_begin(struct mvtwsi_registers * twsi,int expected_start_status,u8 addr,uint tick)543 static int i2c_begin(struct mvtwsi_registers *twsi, int expected_start_status,
544 u8 addr, uint tick)
545 {
546 int status, expected_addr_status;
547
548 /* Compute the expected address status from the direction bit in
549 * the address byte */
550 if (addr & 1) /* Reading */
551 expected_addr_status = MVTWSI_STATUS_ADDR_R_ACK;
552 else /* Writing */
553 expected_addr_status = MVTWSI_STATUS_ADDR_W_ACK;
554 /* Assert START */
555 status = twsi_start(twsi, expected_start_status, tick);
556 /* Send out the address if the start went well */
557 if (status == 0)
558 status = twsi_send(twsi, addr, expected_addr_status, tick);
559 /* Return 0, or the status of the first failure */
560 return status;
561 }
562
563 /*
564 * __twsi_i2c_probe_chip() - Probe the given I2C chip address.
565 *
566 * This function begins a I2C read transaction, does a dummy read and NAKs; if
567 * the procedure succeeds, the chip is considered to be present.
568 *
569 * @twsi: The MVTWSI register structure to use.
570 * @chip: The chip address to probe.
571 * @tick: The duration of a clock cycle at the current I2C speed.
572 * @return Zero if the operation succeeded, or a non-zero code if a time out or
573 * unexpected I2C status occurred.
574 */
__twsi_i2c_probe_chip(struct mvtwsi_registers * twsi,uchar chip,uint tick)575 static int __twsi_i2c_probe_chip(struct mvtwsi_registers *twsi, uchar chip,
576 uint tick)
577 {
578 u8 dummy_byte;
579 int status;
580
581 /* Begin i2c read */
582 status = i2c_begin(twsi, MVTWSI_STATUS_START, (chip << 1) | 1, tick);
583 /* Dummy read was accepted: receive byte, but NAK it. */
584 if (status == 0)
585 status = twsi_recv(twsi, &dummy_byte, MVTWSI_READ_NAK, tick);
586 /* Stop transaction */
587 twsi_stop(twsi, tick);
588 /* Return 0, or the status of the first failure */
589 return status;
590 }
591
592 /*
593 * __twsi_i2c_read() - Read data from a I2C chip.
594 *
595 * This function begins a I2C write transaction, and transmits the address
596 * bytes; then begins a I2C read transaction, and receives the data bytes.
597 *
598 * NOTE: Some devices want a stop right before the second start, while some
599 * will choke if it is there. Since deciding this is not yet supported in
600 * higher level APIs, we need to make a decision here, and for the moment that
601 * will be a repeated start without a preceding stop.
602 *
603 * @twsi: The MVTWSI register structure to use.
604 * @chip: The chip address to read from.
605 * @addr: The address bytes to send.
606 * @alen: The length of the address bytes in bytes.
607 * @data: The buffer to receive the data read from the chip (has to have
608 * a size of at least 'length' bytes).
609 * @length: The amount of data to be read from the chip in bytes.
610 * @tick: The duration of a clock cycle at the current I2C speed.
611 * @return Zero if the operation succeeded, or a non-zero code if a time out or
612 * unexpected I2C status occurred.
613 */
__twsi_i2c_read(struct mvtwsi_registers * twsi,uchar chip,u8 * addr,int alen,uchar * data,int length,uint tick)614 static int __twsi_i2c_read(struct mvtwsi_registers *twsi, uchar chip,
615 u8 *addr, int alen, uchar *data, int length,
616 uint tick)
617 {
618 int status = 0;
619 int stop_status;
620 int expected_start = MVTWSI_STATUS_START;
621
622 if (alen > 0) {
623 /* Begin i2c write to send the address bytes */
624 status = i2c_begin(twsi, expected_start, (chip << 1), tick);
625 /* Send address bytes */
626 while ((status == 0) && alen--)
627 status = twsi_send(twsi, addr[alen],
628 MVTWSI_STATUS_DATA_W_ACK, tick);
629 /* Send repeated STARTs after the initial START */
630 expected_start = MVTWSI_STATUS_REPEATED_START;
631 }
632 /* Begin i2c read to receive data bytes */
633 if (status == 0)
634 status = i2c_begin(twsi, expected_start, (chip << 1) | 1, tick);
635 /* Receive actual data bytes; set NAK if we if we have nothing more to
636 * read */
637 while ((status == 0) && length--)
638 status = twsi_recv(twsi, data++,
639 length > 0 ?
640 MVTWSI_READ_ACK : MVTWSI_READ_NAK, tick);
641 /* Stop transaction */
642 stop_status = twsi_stop(twsi, tick);
643 /* Return 0, or the status of the first failure */
644 return status != 0 ? status : stop_status;
645 }
646
647 /*
648 * __twsi_i2c_write() - Send data to a I2C chip.
649 *
650 * This function begins a I2C write transaction, and transmits the address
651 * bytes; then begins a new I2C write transaction, and sends the data bytes.
652 *
653 * @twsi: The MVTWSI register structure to use.
654 * @chip: The chip address to read from.
655 * @addr: The address bytes to send.
656 * @alen: The length of the address bytes in bytes.
657 * @data: The buffer containing the data to be sent to the chip.
658 * @length: The length of data to be sent to the chip in bytes.
659 * @tick: The duration of a clock cycle at the current I2C speed.
660 * @return Zero if the operation succeeded, or a non-zero code if a time out or
661 * unexpected I2C status occurred.
662 */
__twsi_i2c_write(struct mvtwsi_registers * twsi,uchar chip,u8 * addr,int alen,uchar * data,int length,uint tick)663 static int __twsi_i2c_write(struct mvtwsi_registers *twsi, uchar chip,
664 u8 *addr, int alen, uchar *data, int length,
665 uint tick)
666 {
667 int status, stop_status;
668
669 /* Begin i2c write to send first the address bytes, then the
670 * data bytes */
671 status = i2c_begin(twsi, MVTWSI_STATUS_START, (chip << 1), tick);
672 /* Send address bytes */
673 while ((status == 0) && (alen-- > 0))
674 status = twsi_send(twsi, addr[alen], MVTWSI_STATUS_DATA_W_ACK,
675 tick);
676 /* Send data bytes */
677 while ((status == 0) && (length-- > 0))
678 status = twsi_send(twsi, *(data++), MVTWSI_STATUS_DATA_W_ACK,
679 tick);
680 /* Stop transaction */
681 stop_status = twsi_stop(twsi, tick);
682 /* Return 0, or the status of the first failure */
683 return status != 0 ? status : stop_status;
684 }
685
686 #if !CONFIG_IS_ENABLED(DM_I2C)
twsi_i2c_init(struct i2c_adapter * adap,int speed,int slaveadd)687 static void twsi_i2c_init(struct i2c_adapter *adap, int speed,
688 int slaveadd)
689 {
690 struct mvtwsi_registers *twsi = twsi_get_base(adap);
691 __twsi_i2c_init(twsi, speed, slaveadd, NULL);
692 }
693
twsi_i2c_set_bus_speed(struct i2c_adapter * adap,uint requested_speed)694 static uint twsi_i2c_set_bus_speed(struct i2c_adapter *adap,
695 uint requested_speed)
696 {
697 struct mvtwsi_registers *twsi = twsi_get_base(adap);
698 __twsi_i2c_set_bus_speed(twsi, requested_speed);
699 return 0;
700 }
701
twsi_i2c_probe(struct i2c_adapter * adap,uchar chip)702 static int twsi_i2c_probe(struct i2c_adapter *adap, uchar chip)
703 {
704 struct mvtwsi_registers *twsi = twsi_get_base(adap);
705 return __twsi_i2c_probe_chip(twsi, chip, 10000);
706 }
707
twsi_i2c_read(struct i2c_adapter * adap,uchar chip,uint addr,int alen,uchar * data,int length)708 static int twsi_i2c_read(struct i2c_adapter *adap, uchar chip, uint addr,
709 int alen, uchar *data, int length)
710 {
711 struct mvtwsi_registers *twsi = twsi_get_base(adap);
712 u8 addr_bytes[4];
713
714 addr_bytes[0] = (addr >> 0) & 0xFF;
715 addr_bytes[1] = (addr >> 8) & 0xFF;
716 addr_bytes[2] = (addr >> 16) & 0xFF;
717 addr_bytes[3] = (addr >> 24) & 0xFF;
718
719 return __twsi_i2c_read(twsi, chip, addr_bytes, alen, data, length,
720 10000);
721 }
722
twsi_i2c_write(struct i2c_adapter * adap,uchar chip,uint addr,int alen,uchar * data,int length)723 static int twsi_i2c_write(struct i2c_adapter *adap, uchar chip, uint addr,
724 int alen, uchar *data, int length)
725 {
726 struct mvtwsi_registers *twsi = twsi_get_base(adap);
727 u8 addr_bytes[4];
728
729 addr_bytes[0] = (addr >> 0) & 0xFF;
730 addr_bytes[1] = (addr >> 8) & 0xFF;
731 addr_bytes[2] = (addr >> 16) & 0xFF;
732 addr_bytes[3] = (addr >> 24) & 0xFF;
733
734 return __twsi_i2c_write(twsi, chip, addr_bytes, alen, data, length,
735 10000);
736 }
737
738 #ifdef CONFIG_I2C_MVTWSI_BASE0
739 U_BOOT_I2C_ADAP_COMPLETE(twsi0, twsi_i2c_init, twsi_i2c_probe,
740 twsi_i2c_read, twsi_i2c_write,
741 twsi_i2c_set_bus_speed,
742 CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE, 0)
743 #endif
744 #ifdef CONFIG_I2C_MVTWSI_BASE1
745 U_BOOT_I2C_ADAP_COMPLETE(twsi1, twsi_i2c_init, twsi_i2c_probe,
746 twsi_i2c_read, twsi_i2c_write,
747 twsi_i2c_set_bus_speed,
748 CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE, 1)
749
750 #endif
751 #ifdef CONFIG_I2C_MVTWSI_BASE2
752 U_BOOT_I2C_ADAP_COMPLETE(twsi2, twsi_i2c_init, twsi_i2c_probe,
753 twsi_i2c_read, twsi_i2c_write,
754 twsi_i2c_set_bus_speed,
755 CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE, 2)
756
757 #endif
758 #ifdef CONFIG_I2C_MVTWSI_BASE3
759 U_BOOT_I2C_ADAP_COMPLETE(twsi3, twsi_i2c_init, twsi_i2c_probe,
760 twsi_i2c_read, twsi_i2c_write,
761 twsi_i2c_set_bus_speed,
762 CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE, 3)
763
764 #endif
765 #ifdef CONFIG_I2C_MVTWSI_BASE4
766 U_BOOT_I2C_ADAP_COMPLETE(twsi4, twsi_i2c_init, twsi_i2c_probe,
767 twsi_i2c_read, twsi_i2c_write,
768 twsi_i2c_set_bus_speed,
769 CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE, 4)
770
771 #endif
772 #ifdef CONFIG_I2C_MVTWSI_BASE5
773 U_BOOT_I2C_ADAP_COMPLETE(twsi5, twsi_i2c_init, twsi_i2c_probe,
774 twsi_i2c_read, twsi_i2c_write,
775 twsi_i2c_set_bus_speed,
776 CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE, 5)
777
778 #endif
779 #else /* CONFIG_DM_I2C */
780
781 static int mvtwsi_i2c_probe_chip(struct udevice *bus, u32 chip_addr,
782 u32 chip_flags)
783 {
784 struct mvtwsi_i2c_dev *dev = dev_get_priv(bus);
785 return __twsi_i2c_probe_chip(dev->base, chip_addr, dev->tick);
786 }
787
788 static int mvtwsi_i2c_set_bus_speed(struct udevice *bus, uint speed)
789 {
790 struct mvtwsi_i2c_dev *dev = dev_get_priv(bus);
791
792 dev->speed = __twsi_i2c_set_bus_speed(dev->base, speed);
793 dev->tick = calc_tick(dev->speed);
794
795 return 0;
796 }
797
798 static int mvtwsi_i2c_of_to_plat(struct udevice *bus)
799 {
800 struct mvtwsi_i2c_dev *dev = dev_get_priv(bus);
801
802 dev->base = dev_read_addr_ptr(bus);
803
804 if (!dev->base)
805 return -ENOMEM;
806
807 dev->index = fdtdec_get_int(gd->fdt_blob, dev_of_offset(bus),
808 "cell-index", -1);
809 dev->slaveadd = fdtdec_get_int(gd->fdt_blob, dev_of_offset(bus),
810 "u-boot,i2c-slave-addr", 0x0);
811 dev->speed = dev_read_u32_default(bus, "clock-frequency",
812 I2C_SPEED_STANDARD_RATE);
813
814 return 0;
815 }
816
817 static void twsi_disable_i2c_slave(struct mvtwsi_registers *twsi)
818 {
819 clrbits_le32(&twsi->debug, BIT(18));
820 }
821
822 static int mvtwsi_i2c_bind(struct udevice *bus)
823 {
824 struct mvtwsi_registers *twsi = dev_read_addr_ptr(bus);
825
826 /* Disable the hidden slave in i2c0 of these platforms */
827 if ((IS_ENABLED(CONFIG_ARMADA_38X) ||
828 IS_ENABLED(CONFIG_ARCH_KIRKWOOD) ||
829 IS_ENABLED(CONFIG_ARMADA_8K)) && !dev_seq(bus))
830 twsi_disable_i2c_slave(twsi);
831
832 return 0;
833 }
834
835 static int mvtwsi_i2c_probe(struct udevice *bus)
836 {
837 struct mvtwsi_i2c_dev *dev = dev_get_priv(bus);
838 uint actual_speed;
839
840 __twsi_i2c_init(dev->base, dev->speed, dev->slaveadd, &actual_speed);
841 dev->speed = actual_speed;
842 dev->tick = calc_tick(dev->speed);
843 return 0;
844 }
845
846 static int mvtwsi_i2c_xfer(struct udevice *bus, struct i2c_msg *msg, int nmsgs)
847 {
848 struct mvtwsi_i2c_dev *dev = dev_get_priv(bus);
849 struct i2c_msg *dmsg, *omsg, dummy;
850
851 memset(&dummy, 0, sizeof(struct i2c_msg));
852
853 /* We expect either two messages (one with an offset and one with the
854 * actual data) or one message (just data or offset/data combined) */
855 if (nmsgs > 2 || nmsgs == 0) {
856 debug("%s: Only one or two messages are supported.", __func__);
857 return -1;
858 }
859
860 omsg = nmsgs == 1 ? &dummy : msg;
861 dmsg = nmsgs == 1 ? msg : msg + 1;
862
863 if (dmsg->flags & I2C_M_RD)
864 return __twsi_i2c_read(dev->base, dmsg->addr, omsg->buf,
865 omsg->len, dmsg->buf, dmsg->len,
866 dev->tick);
867 else
868 return __twsi_i2c_write(dev->base, dmsg->addr, omsg->buf,
869 omsg->len, dmsg->buf, dmsg->len,
870 dev->tick);
871 }
872
873 static const struct dm_i2c_ops mvtwsi_i2c_ops = {
874 .xfer = mvtwsi_i2c_xfer,
875 .probe_chip = mvtwsi_i2c_probe_chip,
876 .set_bus_speed = mvtwsi_i2c_set_bus_speed,
877 };
878
879 static const struct udevice_id mvtwsi_i2c_ids[] = {
880 { .compatible = "marvell,mv64xxx-i2c", },
881 { .compatible = "marvell,mv78230-i2c", },
882 { .compatible = "allwinner,sun6i-a31-i2c", },
883 { /* sentinel */ }
884 };
885
886 U_BOOT_DRIVER(i2c_mvtwsi) = {
887 .name = "i2c_mvtwsi",
888 .id = UCLASS_I2C,
889 .of_match = mvtwsi_i2c_ids,
890 .bind = mvtwsi_i2c_bind,
891 .probe = mvtwsi_i2c_probe,
892 .of_to_plat = mvtwsi_i2c_of_to_plat,
893 .priv_auto = sizeof(struct mvtwsi_i2c_dev),
894 .ops = &mvtwsi_i2c_ops,
895 };
896 #endif /* CONFIG_DM_I2C */
897