1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Copyright 2007, 2010-2011 Freescale Semiconductor, Inc
4 * Copyright 2019, 2021 NXP
5 * Andy Fleming
6 * Yangbo Lu <yangbo.lu@nxp.com>
7 *
8 * Based vaguely on the pxa mmc code:
9 * (C) Copyright 2003
10 * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net
11 */
12
13 #include <config.h>
14 #include <common.h>
15 #include <command.h>
16 #include <clk.h>
17 #include <cpu_func.h>
18 #include <errno.h>
19 #include <hwconfig.h>
20 #include <log.h>
21 #include <mmc.h>
22 #include <part.h>
23 #include <asm/cache.h>
24 #include <asm/global_data.h>
25 #include <dm/device_compat.h>
26 #include <linux/bitops.h>
27 #include <linux/delay.h>
28 #include <linux/err.h>
29 #include <power/regulator.h>
30 #include <malloc.h>
31 #include <fsl_esdhc_imx.h>
32 #include <fdt_support.h>
33 #include <asm/io.h>
34 #include <dm.h>
35 #include <asm-generic/gpio.h>
36 #include <dm/pinctrl.h>
37 #include <dt-structs.h>
38 #include <mapmem.h>
39 #include <dm/ofnode.h>
40 #include <linux/iopoll.h>
41
42 #if !CONFIG_IS_ENABLED(BLK)
43 #include "mmc_private.h"
44 #endif
45
46 #ifndef ESDHCI_QUIRK_BROKEN_TIMEOUT_VALUE
47 #ifdef CONFIG_FSL_USDHC
48 #define ESDHCI_QUIRK_BROKEN_TIMEOUT_VALUE 1
49 #endif
50 #endif
51
52 DECLARE_GLOBAL_DATA_PTR;
53
54 #define SDHCI_IRQ_EN_BITS (IRQSTATEN_CC | IRQSTATEN_TC | \
55 IRQSTATEN_CINT | \
56 IRQSTATEN_CTOE | IRQSTATEN_CCE | IRQSTATEN_CEBE | \
57 IRQSTATEN_CIE | IRQSTATEN_DTOE | IRQSTATEN_DCE | \
58 IRQSTATEN_DEBE | IRQSTATEN_BRR | IRQSTATEN_BWR | \
59 IRQSTATEN_DINT)
60 #define MAX_TUNING_LOOP 40
61 #define ESDHC_DRIVER_STAGE_VALUE 0xffffffff
62
63 struct fsl_esdhc {
64 uint dsaddr; /* SDMA system address register */
65 uint blkattr; /* Block attributes register */
66 uint cmdarg; /* Command argument register */
67 uint xfertyp; /* Transfer type register */
68 uint cmdrsp0; /* Command response 0 register */
69 uint cmdrsp1; /* Command response 1 register */
70 uint cmdrsp2; /* Command response 2 register */
71 uint cmdrsp3; /* Command response 3 register */
72 uint datport; /* Buffer data port register */
73 uint prsstat; /* Present state register */
74 uint proctl; /* Protocol control register */
75 uint sysctl; /* System Control Register */
76 uint irqstat; /* Interrupt status register */
77 uint irqstaten; /* Interrupt status enable register */
78 uint irqsigen; /* Interrupt signal enable register */
79 uint autoc12err; /* Auto CMD error status register */
80 uint hostcapblt; /* Host controller capabilities register */
81 uint wml; /* Watermark level register */
82 uint mixctrl; /* For USDHC */
83 char reserved1[4]; /* reserved */
84 uint fevt; /* Force event register */
85 uint admaes; /* ADMA error status register */
86 uint adsaddr; /* ADMA system address register */
87 char reserved2[4];
88 uint dllctrl;
89 uint dllstat;
90 uint clktunectrlstatus;
91 char reserved3[4];
92 uint strobe_dllctrl;
93 uint strobe_dllstat;
94 char reserved4[72];
95 uint vendorspec;
96 uint mmcboot;
97 uint vendorspec2;
98 uint tuning_ctrl; /* on i.MX6/7/8/RT */
99 char reserved5[44];
100 uint hostver; /* Host controller version register */
101 char reserved6[4]; /* reserved */
102 uint dmaerraddr; /* DMA error address register */
103 char reserved7[4]; /* reserved */
104 uint dmaerrattr; /* DMA error attribute register */
105 char reserved8[4]; /* reserved */
106 uint hostcapblt2; /* Host controller capabilities register 2 */
107 char reserved9[8]; /* reserved */
108 uint tcr; /* Tuning control register */
109 char reserved10[28]; /* reserved */
110 uint sddirctl; /* SD direction control register */
111 char reserved11[712];/* reserved */
112 uint scr; /* eSDHC control register */
113 };
114
115 struct fsl_esdhc_plat {
116 #if CONFIG_IS_ENABLED(OF_PLATDATA)
117 /* Put this first since driver model will copy the data here */
118 struct dtd_fsl_esdhc dtplat;
119 #endif
120
121 struct mmc_config cfg;
122 struct mmc mmc;
123 };
124
125 struct esdhc_soc_data {
126 u32 flags;
127 };
128
129 /**
130 * struct fsl_esdhc_priv
131 *
132 * @esdhc_regs: registers of the sdhc controller
133 * @sdhc_clk: Current clk of the sdhc controller
134 * @bus_width: bus width, 1bit, 4bit or 8bit
135 * @cfg: mmc config
136 * @mmc: mmc
137 * Following is used when Driver Model is enabled for MMC
138 * @dev: pointer for the device
139 * @non_removable: 0: removable; 1: non-removable
140 * @broken_cd: 0: use GPIO for card detect; 1: Do not use GPIO for card detect
141 * @wp_enable: 1: enable checking wp; 0: no check
142 * @vs18_enable: 1: use 1.8V voltage; 0: use 3.3V
143 * @flags: ESDHC_FLAG_xx in include/fsl_esdhc_imx.h
144 * @caps: controller capabilities
145 * @tuning_step: tuning step setting in tuning_ctrl register
146 * @start_tuning_tap: the start point for tuning in tuning_ctrl register
147 * @strobe_dll_delay_target: settings in strobe_dllctrl
148 * @signal_voltage: indicating the current voltage
149 * @signal_voltage_switch_extra_delay_ms: extra delay for IO voltage switch
150 * @cd_gpio: gpio for card detection
151 * @wp_gpio: gpio for write protection
152 */
153 struct fsl_esdhc_priv {
154 struct fsl_esdhc *esdhc_regs;
155 unsigned int sdhc_clk;
156 struct clk per_clk;
157 unsigned int clock;
158 unsigned int mode;
159 unsigned int bus_width;
160 #if !CONFIG_IS_ENABLED(BLK)
161 struct mmc *mmc;
162 #endif
163 struct udevice *dev;
164 int non_removable;
165 int broken_cd;
166 int wp_enable;
167 int vs18_enable;
168 u32 flags;
169 u32 caps;
170 u32 tuning_step;
171 u32 tuning_start_tap;
172 u32 strobe_dll_delay_target;
173 u32 signal_voltage;
174 u32 signal_voltage_switch_extra_delay_ms;
175 #if CONFIG_IS_ENABLED(DM_REGULATOR)
176 struct udevice *vqmmc_dev;
177 struct udevice *vmmc_dev;
178 #endif
179 #if CONFIG_IS_ENABLED(DM_GPIO)
180 struct gpio_desc cd_gpio;
181 struct gpio_desc wp_gpio;
182 #endif
183 };
184
185 /* Return the XFERTYP flags for a given command and data packet */
esdhc_xfertyp(struct mmc_cmd * cmd,struct mmc_data * data)186 static uint esdhc_xfertyp(struct mmc_cmd *cmd, struct mmc_data *data)
187 {
188 uint xfertyp = 0;
189
190 if (data) {
191 xfertyp |= XFERTYP_DPSEL;
192 #ifndef CONFIG_SYS_FSL_ESDHC_USE_PIO
193 xfertyp |= XFERTYP_DMAEN;
194 #endif
195 if (data->blocks > 1) {
196 xfertyp |= XFERTYP_MSBSEL;
197 xfertyp |= XFERTYP_BCEN;
198 #ifdef CONFIG_SYS_FSL_ERRATUM_ESDHC111
199 xfertyp |= XFERTYP_AC12EN;
200 #endif
201 }
202
203 if (data->flags & MMC_DATA_READ)
204 xfertyp |= XFERTYP_DTDSEL;
205 }
206
207 if (cmd->resp_type & MMC_RSP_CRC)
208 xfertyp |= XFERTYP_CCCEN;
209 if (cmd->resp_type & MMC_RSP_OPCODE)
210 xfertyp |= XFERTYP_CICEN;
211 if (cmd->resp_type & MMC_RSP_136)
212 xfertyp |= XFERTYP_RSPTYP_136;
213 else if (cmd->resp_type & MMC_RSP_BUSY)
214 xfertyp |= XFERTYP_RSPTYP_48_BUSY;
215 else if (cmd->resp_type & MMC_RSP_PRESENT)
216 xfertyp |= XFERTYP_RSPTYP_48;
217
218 if (cmd->cmdidx == MMC_CMD_STOP_TRANSMISSION)
219 xfertyp |= XFERTYP_CMDTYP_ABORT;
220
221 return XFERTYP_CMD(cmd->cmdidx) | xfertyp;
222 }
223
224 #ifdef CONFIG_SYS_FSL_ESDHC_USE_PIO
225 /*
226 * PIO Read/Write Mode reduce the performace as DMA is not used in this mode.
227 */
esdhc_pio_read_write(struct fsl_esdhc_priv * priv,struct mmc_data * data)228 static void esdhc_pio_read_write(struct fsl_esdhc_priv *priv,
229 struct mmc_data *data)
230 {
231 struct fsl_esdhc *regs = priv->esdhc_regs;
232 uint blocks;
233 char *buffer;
234 uint databuf;
235 uint size;
236 uint irqstat;
237 ulong start;
238
239 if (data->flags & MMC_DATA_READ) {
240 blocks = data->blocks;
241 buffer = data->dest;
242 while (blocks) {
243 start = get_timer(0);
244 size = data->blocksize;
245 irqstat = esdhc_read32(®s->irqstat);
246 while (!(esdhc_read32(®s->prsstat) & PRSSTAT_BREN)) {
247 if (get_timer(start) > PIO_TIMEOUT) {
248 printf("\nData Read Failed in PIO Mode.");
249 return;
250 }
251 }
252 while (size && (!(irqstat & IRQSTAT_TC))) {
253 udelay(100); /* Wait before last byte transfer complete */
254 irqstat = esdhc_read32(®s->irqstat);
255 databuf = in_le32(®s->datport);
256 *((uint *)buffer) = databuf;
257 buffer += 4;
258 size -= 4;
259 }
260 blocks--;
261 }
262 } else {
263 blocks = data->blocks;
264 buffer = (char *)data->src;
265 while (blocks) {
266 start = get_timer(0);
267 size = data->blocksize;
268 irqstat = esdhc_read32(®s->irqstat);
269 while (!(esdhc_read32(®s->prsstat) & PRSSTAT_BWEN)) {
270 if (get_timer(start) > PIO_TIMEOUT) {
271 printf("\nData Write Failed in PIO Mode.");
272 return;
273 }
274 }
275 while (size && (!(irqstat & IRQSTAT_TC))) {
276 udelay(100); /* Wait before last byte transfer complete */
277 databuf = *((uint *)buffer);
278 buffer += 4;
279 size -= 4;
280 irqstat = esdhc_read32(®s->irqstat);
281 out_le32(®s->datport, databuf);
282 }
283 blocks--;
284 }
285 }
286 }
287 #endif
288
esdhc_setup_data(struct fsl_esdhc_priv * priv,struct mmc * mmc,struct mmc_data * data)289 static int esdhc_setup_data(struct fsl_esdhc_priv *priv, struct mmc *mmc,
290 struct mmc_data *data)
291 {
292 int timeout;
293 struct fsl_esdhc *regs = priv->esdhc_regs;
294 #if defined(CONFIG_S32V234) || defined(CONFIG_IMX8) || defined(CONFIG_IMX8M)
295 dma_addr_t addr;
296 #endif
297 uint wml_value;
298
299 wml_value = data->blocksize/4;
300
301 if (data->flags & MMC_DATA_READ) {
302 if (wml_value > WML_RD_WML_MAX)
303 wml_value = WML_RD_WML_MAX_VAL;
304
305 esdhc_clrsetbits32(®s->wml, WML_RD_WML_MASK, wml_value);
306 #ifndef CONFIG_SYS_FSL_ESDHC_USE_PIO
307 #if defined(CONFIG_S32V234) || defined(CONFIG_IMX8) || defined(CONFIG_IMX8M)
308 addr = virt_to_phys((void *)(data->dest));
309 if (upper_32_bits(addr))
310 printf("Error found for upper 32 bits\n");
311 else
312 esdhc_write32(®s->dsaddr, lower_32_bits(addr));
313 #else
314 esdhc_write32(®s->dsaddr, (u32)data->dest);
315 #endif
316 #endif
317 } else {
318 #ifndef CONFIG_SYS_FSL_ESDHC_USE_PIO
319 flush_dcache_range((ulong)data->src,
320 (ulong)data->src+data->blocks
321 *data->blocksize);
322 #endif
323 if (wml_value > WML_WR_WML_MAX)
324 wml_value = WML_WR_WML_MAX_VAL;
325 if (priv->wp_enable) {
326 if ((esdhc_read32(®s->prsstat) &
327 PRSSTAT_WPSPL) == 0) {
328 printf("\nThe SD card is locked. Can not write to a locked card.\n\n");
329 return -ETIMEDOUT;
330 }
331 } else {
332 #if CONFIG_IS_ENABLED(DM_GPIO)
333 if (dm_gpio_is_valid(&priv->wp_gpio) &&
334 dm_gpio_get_value(&priv->wp_gpio)) {
335 printf("\nThe SD card is locked. Can not write to a locked card.\n\n");
336 return -ETIMEDOUT;
337 }
338 #endif
339 }
340
341 esdhc_clrsetbits32(®s->wml, WML_WR_WML_MASK,
342 wml_value << 16);
343 #ifndef CONFIG_SYS_FSL_ESDHC_USE_PIO
344 #if defined(CONFIG_S32V234) || defined(CONFIG_IMX8) || defined(CONFIG_IMX8M)
345 addr = virt_to_phys((void *)(data->src));
346 if (upper_32_bits(addr))
347 printf("Error found for upper 32 bits\n");
348 else
349 esdhc_write32(®s->dsaddr, lower_32_bits(addr));
350 #else
351 esdhc_write32(®s->dsaddr, (u32)data->src);
352 #endif
353 #endif
354 }
355
356 esdhc_write32(®s->blkattr, data->blocks << 16 | data->blocksize);
357
358 /* Calculate the timeout period for data transactions */
359 /*
360 * 1)Timeout period = (2^(timeout+13)) SD Clock cycles
361 * 2)Timeout period should be minimum 0.250sec as per SD Card spec
362 * So, Number of SD Clock cycles for 0.25sec should be minimum
363 * (SD Clock/sec * 0.25 sec) SD Clock cycles
364 * = (mmc->clock * 1/4) SD Clock cycles
365 * As 1) >= 2)
366 * => (2^(timeout+13)) >= mmc->clock * 1/4
367 * Taking log2 both the sides
368 * => timeout + 13 >= log2(mmc->clock/4)
369 * Rounding up to next power of 2
370 * => timeout + 13 = log2(mmc->clock/4) + 1
371 * => timeout + 13 = fls(mmc->clock/4)
372 *
373 * However, the MMC spec "It is strongly recommended for hosts to
374 * implement more than 500ms timeout value even if the card
375 * indicates the 250ms maximum busy length." Even the previous
376 * value of 300ms is known to be insufficient for some cards.
377 * So, we use
378 * => timeout + 13 = fls(mmc->clock/2)
379 */
380 timeout = fls(mmc->clock/2);
381 timeout -= 13;
382
383 if (timeout > 14)
384 timeout = 14;
385
386 if (timeout < 0)
387 timeout = 0;
388
389 #ifdef CONFIG_SYS_FSL_ERRATUM_ESDHC_A001
390 if ((timeout == 4) || (timeout == 8) || (timeout == 12))
391 timeout++;
392 #endif
393
394 #ifdef ESDHCI_QUIRK_BROKEN_TIMEOUT_VALUE
395 timeout = 0xE;
396 #endif
397 esdhc_clrsetbits32(®s->sysctl, SYSCTL_TIMEOUT_MASK, timeout << 16);
398
399 return 0;
400 }
401
check_and_invalidate_dcache_range(struct mmc_cmd * cmd,struct mmc_data * data)402 static void check_and_invalidate_dcache_range
403 (struct mmc_cmd *cmd,
404 struct mmc_data *data) {
405 unsigned start = 0;
406 unsigned end = 0;
407 unsigned size = roundup(ARCH_DMA_MINALIGN,
408 data->blocks*data->blocksize);
409 #if defined(CONFIG_S32V234) || defined(CONFIG_IMX8) || defined(CONFIG_IMX8M)
410 dma_addr_t addr;
411
412 addr = virt_to_phys((void *)(data->dest));
413 if (upper_32_bits(addr))
414 printf("Error found for upper 32 bits\n");
415 else
416 start = lower_32_bits(addr);
417 #else
418 start = (unsigned)data->dest;
419 #endif
420 end = start + size;
421 invalidate_dcache_range(start, end);
422 }
423
424 #ifdef CONFIG_MCF5441x
425 /*
426 * Swaps 32-bit words to little-endian byte order.
427 */
sd_swap_dma_buff(struct mmc_data * data)428 static inline void sd_swap_dma_buff(struct mmc_data *data)
429 {
430 int i, size = data->blocksize >> 2;
431 u32 *buffer = (u32 *)data->dest;
432 u32 sw;
433
434 while (data->blocks--) {
435 for (i = 0; i < size; i++) {
436 sw = __sw32(*buffer);
437 *buffer++ = sw;
438 }
439 }
440 }
441 #endif
442
443 /*
444 * Sends a command out on the bus. Takes the mmc pointer,
445 * a command pointer, and an optional data pointer.
446 */
esdhc_send_cmd_common(struct fsl_esdhc_priv * priv,struct mmc * mmc,struct mmc_cmd * cmd,struct mmc_data * data)447 static int esdhc_send_cmd_common(struct fsl_esdhc_priv *priv, struct mmc *mmc,
448 struct mmc_cmd *cmd, struct mmc_data *data)
449 {
450 int err = 0;
451 uint xfertyp;
452 uint irqstat;
453 u32 flags = IRQSTAT_CC | IRQSTAT_CTOE;
454 struct fsl_esdhc *regs = priv->esdhc_regs;
455 unsigned long start;
456
457 #ifdef CONFIG_SYS_FSL_ERRATUM_ESDHC111
458 if (cmd->cmdidx == MMC_CMD_STOP_TRANSMISSION)
459 return 0;
460 #endif
461
462 esdhc_write32(®s->irqstat, -1);
463
464 sync();
465
466 /* Wait for the bus to be idle */
467 while ((esdhc_read32(®s->prsstat) & PRSSTAT_CICHB) ||
468 (esdhc_read32(®s->prsstat) & PRSSTAT_CIDHB))
469 ;
470
471 while (esdhc_read32(®s->prsstat) & PRSSTAT_DLA)
472 ;
473
474 /* Set up for a data transfer if we have one */
475 if (data) {
476 err = esdhc_setup_data(priv, mmc, data);
477 if(err)
478 return err;
479
480 if (data->flags & MMC_DATA_READ)
481 check_and_invalidate_dcache_range(cmd, data);
482 }
483
484 /* Figure out the transfer arguments */
485 xfertyp = esdhc_xfertyp(cmd, data);
486
487 /* Mask all irqs */
488 esdhc_write32(®s->irqsigen, 0);
489
490 /* Send the command */
491 esdhc_write32(®s->cmdarg, cmd->cmdarg);
492 #if defined(CONFIG_FSL_USDHC)
493 esdhc_write32(®s->mixctrl,
494 (esdhc_read32(®s->mixctrl) & 0xFFFFFF80) | (xfertyp & 0x7F)
495 | (mmc->ddr_mode ? XFERTYP_DDREN : 0));
496 esdhc_write32(®s->xfertyp, xfertyp & 0xFFFF0000);
497 #else
498 esdhc_write32(®s->xfertyp, xfertyp);
499 #endif
500
501 if ((cmd->cmdidx == MMC_CMD_SEND_TUNING_BLOCK) ||
502 (cmd->cmdidx == MMC_CMD_SEND_TUNING_BLOCK_HS200))
503 flags = IRQSTAT_BRR;
504
505 /* Wait for the command to complete */
506 start = get_timer(0);
507 while (!(esdhc_read32(®s->irqstat) & flags)) {
508 if (get_timer(start) > 1000) {
509 err = -ETIMEDOUT;
510 goto out;
511 }
512 }
513
514 irqstat = esdhc_read32(®s->irqstat);
515
516 if (irqstat & CMD_ERR) {
517 err = -ECOMM;
518 goto out;
519 }
520
521 if (irqstat & IRQSTAT_CTOE) {
522 err = -ETIMEDOUT;
523 goto out;
524 }
525
526 /* Workaround for ESDHC errata ENGcm03648 */
527 if (!data && (cmd->resp_type & MMC_RSP_BUSY)) {
528 int timeout = 50000;
529
530 /* Poll on DATA0 line for cmd with busy signal for 5000 ms */
531 while (timeout > 0 && !(esdhc_read32(®s->prsstat) &
532 PRSSTAT_DAT0)) {
533 udelay(100);
534 timeout--;
535 }
536
537 if (timeout <= 0) {
538 printf("Timeout waiting for DAT0 to go high!\n");
539 err = -ETIMEDOUT;
540 goto out;
541 }
542 }
543
544 /* Copy the response to the response buffer */
545 if (cmd->resp_type & MMC_RSP_136) {
546 u32 cmdrsp3, cmdrsp2, cmdrsp1, cmdrsp0;
547
548 cmdrsp3 = esdhc_read32(®s->cmdrsp3);
549 cmdrsp2 = esdhc_read32(®s->cmdrsp2);
550 cmdrsp1 = esdhc_read32(®s->cmdrsp1);
551 cmdrsp0 = esdhc_read32(®s->cmdrsp0);
552 cmd->response[0] = (cmdrsp3 << 8) | (cmdrsp2 >> 24);
553 cmd->response[1] = (cmdrsp2 << 8) | (cmdrsp1 >> 24);
554 cmd->response[2] = (cmdrsp1 << 8) | (cmdrsp0 >> 24);
555 cmd->response[3] = (cmdrsp0 << 8);
556 } else
557 cmd->response[0] = esdhc_read32(®s->cmdrsp0);
558
559 /* Wait until all of the blocks are transferred */
560 if (data) {
561 #ifdef CONFIG_SYS_FSL_ESDHC_USE_PIO
562 esdhc_pio_read_write(priv, data);
563 #else
564 flags = DATA_COMPLETE;
565 if ((cmd->cmdidx == MMC_CMD_SEND_TUNING_BLOCK) ||
566 (cmd->cmdidx == MMC_CMD_SEND_TUNING_BLOCK_HS200)) {
567 flags = IRQSTAT_BRR;
568 }
569
570 do {
571 irqstat = esdhc_read32(®s->irqstat);
572
573 if (irqstat & IRQSTAT_DTOE) {
574 err = -ETIMEDOUT;
575 goto out;
576 }
577
578 if (irqstat & DATA_ERR) {
579 err = -ECOMM;
580 goto out;
581 }
582 } while ((irqstat & flags) != flags);
583
584 /*
585 * Need invalidate the dcache here again to avoid any
586 * cache-fill during the DMA operations such as the
587 * speculative pre-fetching etc.
588 */
589 if (data->flags & MMC_DATA_READ) {
590 check_and_invalidate_dcache_range(cmd, data);
591 #ifdef CONFIG_MCF5441x
592 sd_swap_dma_buff(data);
593 #endif
594 }
595 #endif
596 }
597
598 out:
599 /* Reset CMD and DATA portions on error */
600 if (err) {
601 esdhc_write32(®s->sysctl, esdhc_read32(®s->sysctl) |
602 SYSCTL_RSTC);
603 while (esdhc_read32(®s->sysctl) & SYSCTL_RSTC)
604 ;
605
606 if (data) {
607 esdhc_write32(®s->sysctl,
608 esdhc_read32(®s->sysctl) |
609 SYSCTL_RSTD);
610 while ((esdhc_read32(®s->sysctl) & SYSCTL_RSTD))
611 ;
612 }
613
614 /* If this was CMD11, then notify that power cycle is needed */
615 if (cmd->cmdidx == SD_CMD_SWITCH_UHS18V)
616 printf("CMD11 to switch to 1.8V mode failed, card requires power cycle.\n");
617 }
618
619 esdhc_write32(®s->irqstat, -1);
620
621 return err;
622 }
623
set_sysctl(struct fsl_esdhc_priv * priv,struct mmc * mmc,uint clock)624 static void set_sysctl(struct fsl_esdhc_priv *priv, struct mmc *mmc, uint clock)
625 {
626 struct fsl_esdhc *regs = priv->esdhc_regs;
627 int div = 1;
628 u32 tmp;
629 int ret;
630 #ifdef ARCH_MXC
631 #ifdef CONFIG_MX53
632 /* For i.MX53 eSDHCv3, SYSCTL.SDCLKFS may not be set to 0. */
633 int pre_div = (regs == (struct fsl_esdhc *)MMC_SDHC3_BASE_ADDR) ? 2 : 1;
634 #else
635 int pre_div = 1;
636 #endif
637 #else
638 int pre_div = 2;
639 #endif
640 int ddr_pre_div = mmc->ddr_mode ? 2 : 1;
641 int sdhc_clk = priv->sdhc_clk;
642 uint clk;
643
644 while (sdhc_clk / (16 * pre_div * ddr_pre_div) > clock && pre_div < 256)
645 pre_div *= 2;
646
647 while (sdhc_clk / (div * pre_div * ddr_pre_div) > clock && div < 16)
648 div++;
649
650 pre_div >>= 1;
651 div -= 1;
652
653 clk = (pre_div << 8) | (div << 4);
654
655 #ifdef CONFIG_FSL_USDHC
656 esdhc_clrbits32(®s->vendorspec, VENDORSPEC_CKEN);
657 #else
658 esdhc_clrbits32(®s->sysctl, SYSCTL_CKEN);
659 #endif
660
661 esdhc_clrsetbits32(®s->sysctl, SYSCTL_CLOCK_MASK, clk);
662
663 ret = readx_poll_timeout(esdhc_read32, ®s->prsstat, tmp, tmp & PRSSTAT_SDSTB, 100);
664 if (ret)
665 pr_warn("fsl_esdhc_imx: Internal clock never stabilised.\n");
666
667 #ifdef CONFIG_FSL_USDHC
668 esdhc_setbits32(®s->vendorspec, VENDORSPEC_PEREN | VENDORSPEC_CKEN);
669 #else
670 esdhc_setbits32(®s->sysctl, SYSCTL_PEREN | SYSCTL_CKEN);
671 #endif
672
673 priv->clock = clock;
674 }
675
676 #ifdef MMC_SUPPORTS_TUNING
esdhc_change_pinstate(struct udevice * dev)677 static int esdhc_change_pinstate(struct udevice *dev)
678 {
679 struct fsl_esdhc_priv *priv = dev_get_priv(dev);
680 int ret;
681
682 switch (priv->mode) {
683 case UHS_SDR50:
684 case UHS_DDR50:
685 ret = pinctrl_select_state(dev, "state_100mhz");
686 break;
687 case UHS_SDR104:
688 case MMC_HS_200:
689 case MMC_HS_400:
690 case MMC_HS_400_ES:
691 ret = pinctrl_select_state(dev, "state_200mhz");
692 break;
693 default:
694 ret = pinctrl_select_state(dev, "default");
695 break;
696 }
697
698 if (ret)
699 printf("%s %d error\n", __func__, priv->mode);
700
701 return ret;
702 }
703
esdhc_reset_tuning(struct mmc * mmc)704 static void esdhc_reset_tuning(struct mmc *mmc)
705 {
706 struct fsl_esdhc_priv *priv = dev_get_priv(mmc->dev);
707 struct fsl_esdhc *regs = priv->esdhc_regs;
708
709 if (priv->flags & ESDHC_FLAG_USDHC) {
710 if (priv->flags & ESDHC_FLAG_STD_TUNING) {
711 esdhc_clrbits32(®s->autoc12err,
712 MIX_CTRL_SMPCLK_SEL |
713 MIX_CTRL_EXE_TUNE);
714 }
715 }
716 }
717
esdhc_set_strobe_dll(struct mmc * mmc)718 static void esdhc_set_strobe_dll(struct mmc *mmc)
719 {
720 struct fsl_esdhc_priv *priv = dev_get_priv(mmc->dev);
721 struct fsl_esdhc *regs = priv->esdhc_regs;
722 u32 val;
723
724 if (priv->clock > ESDHC_STROBE_DLL_CLK_FREQ) {
725 esdhc_write32(®s->strobe_dllctrl, ESDHC_STROBE_DLL_CTRL_RESET);
726
727 /*
728 * enable strobe dll ctrl and adjust the delay target
729 * for the uSDHC loopback read clock
730 */
731 val = ESDHC_STROBE_DLL_CTRL_ENABLE |
732 (priv->strobe_dll_delay_target <<
733 ESDHC_STROBE_DLL_CTRL_SLV_DLY_TARGET_SHIFT);
734 esdhc_write32(®s->strobe_dllctrl, val);
735 /* wait 1us to make sure strobe dll status register stable */
736 mdelay(1);
737 val = esdhc_read32(®s->strobe_dllstat);
738 if (!(val & ESDHC_STROBE_DLL_STS_REF_LOCK))
739 pr_warn("HS400 strobe DLL status REF not lock!\n");
740 if (!(val & ESDHC_STROBE_DLL_STS_SLV_LOCK))
741 pr_warn("HS400 strobe DLL status SLV not lock!\n");
742 }
743 }
744
esdhc_set_timing(struct mmc * mmc)745 static int esdhc_set_timing(struct mmc *mmc)
746 {
747 struct fsl_esdhc_priv *priv = dev_get_priv(mmc->dev);
748 struct fsl_esdhc *regs = priv->esdhc_regs;
749 u32 mixctrl;
750
751 mixctrl = esdhc_read32(®s->mixctrl);
752 mixctrl &= ~(MIX_CTRL_DDREN | MIX_CTRL_HS400_EN);
753
754 switch (mmc->selected_mode) {
755 case MMC_LEGACY:
756 esdhc_reset_tuning(mmc);
757 esdhc_write32(®s->mixctrl, mixctrl);
758 break;
759 case MMC_HS_400:
760 case MMC_HS_400_ES:
761 mixctrl |= MIX_CTRL_DDREN | MIX_CTRL_HS400_EN;
762 esdhc_write32(®s->mixctrl, mixctrl);
763 break;
764 case MMC_HS:
765 case MMC_HS_52:
766 case MMC_HS_200:
767 case SD_HS:
768 case UHS_SDR12:
769 case UHS_SDR25:
770 case UHS_SDR50:
771 case UHS_SDR104:
772 esdhc_write32(®s->mixctrl, mixctrl);
773 break;
774 case UHS_DDR50:
775 case MMC_DDR_52:
776 mixctrl |= MIX_CTRL_DDREN;
777 esdhc_write32(®s->mixctrl, mixctrl);
778 break;
779 default:
780 printf("Not supported %d\n", mmc->selected_mode);
781 return -EINVAL;
782 }
783
784 priv->mode = mmc->selected_mode;
785
786 return esdhc_change_pinstate(mmc->dev);
787 }
788
esdhc_set_voltage(struct mmc * mmc)789 static int esdhc_set_voltage(struct mmc *mmc)
790 {
791 struct fsl_esdhc_priv *priv = dev_get_priv(mmc->dev);
792 struct fsl_esdhc *regs = priv->esdhc_regs;
793 #if CONFIG_IS_ENABLED(DM_REGULATOR)
794 int ret;
795 #endif
796
797 priv->signal_voltage = mmc->signal_voltage;
798 switch (mmc->signal_voltage) {
799 case MMC_SIGNAL_VOLTAGE_330:
800 if (priv->vs18_enable)
801 return -ENOTSUPP;
802 #if CONFIG_IS_ENABLED(DM_REGULATOR)
803 if (!IS_ERR_OR_NULL(priv->vqmmc_dev)) {
804 ret = regulator_set_value(priv->vqmmc_dev, 3300000);
805 if (ret) {
806 printf("Setting to 3.3V error");
807 return -EIO;
808 }
809 /* Wait for 5ms */
810 mdelay(5);
811 }
812 #endif
813
814 esdhc_clrbits32(®s->vendorspec, ESDHC_VENDORSPEC_VSELECT);
815 if (!(esdhc_read32(®s->vendorspec) &
816 ESDHC_VENDORSPEC_VSELECT))
817 return 0;
818
819 return -EAGAIN;
820 case MMC_SIGNAL_VOLTAGE_180:
821 #if CONFIG_IS_ENABLED(DM_REGULATOR)
822 if (!IS_ERR_OR_NULL(priv->vqmmc_dev)) {
823 ret = regulator_set_value(priv->vqmmc_dev, 1800000);
824 if (ret) {
825 printf("Setting to 1.8V error");
826 return -EIO;
827 }
828 }
829 #endif
830 esdhc_setbits32(®s->vendorspec, ESDHC_VENDORSPEC_VSELECT);
831 /*
832 * some board like imx8mm-evk need about 18ms to switch
833 * the IO voltage from 3.3v to 1.8v, common code only
834 * delay 10ms, so need to delay extra time to make sure
835 * the IO voltage change to 1.8v.
836 */
837 if (priv->signal_voltage_switch_extra_delay_ms)
838 mdelay(priv->signal_voltage_switch_extra_delay_ms);
839 if (esdhc_read32(®s->vendorspec) & ESDHC_VENDORSPEC_VSELECT)
840 return 0;
841
842 return -EAGAIN;
843 case MMC_SIGNAL_VOLTAGE_120:
844 return -ENOTSUPP;
845 default:
846 return 0;
847 }
848 }
849
esdhc_stop_tuning(struct mmc * mmc)850 static void esdhc_stop_tuning(struct mmc *mmc)
851 {
852 struct mmc_cmd cmd;
853
854 cmd.cmdidx = MMC_CMD_STOP_TRANSMISSION;
855 cmd.cmdarg = 0;
856 cmd.resp_type = MMC_RSP_R1b;
857
858 mmc_send_cmd(mmc, &cmd, NULL);
859 }
860
fsl_esdhc_execute_tuning(struct udevice * dev,uint32_t opcode)861 static int fsl_esdhc_execute_tuning(struct udevice *dev, uint32_t opcode)
862 {
863 struct fsl_esdhc_plat *plat = dev_get_plat(dev);
864 struct fsl_esdhc_priv *priv = dev_get_priv(dev);
865 struct fsl_esdhc *regs = priv->esdhc_regs;
866 struct mmc *mmc = &plat->mmc;
867 u32 irqstaten = esdhc_read32(®s->irqstaten);
868 u32 irqsigen = esdhc_read32(®s->irqsigen);
869 int i, ret = -ETIMEDOUT;
870 u32 val, mixctrl;
871
872 /* clock tuning is not needed for upto 52MHz */
873 if (mmc->clock <= 52000000)
874 return 0;
875
876 /* This is readw/writew SDHCI_HOST_CONTROL2 when tuning */
877 if (priv->flags & ESDHC_FLAG_STD_TUNING) {
878 val = esdhc_read32(®s->autoc12err);
879 mixctrl = esdhc_read32(®s->mixctrl);
880 val &= ~MIX_CTRL_SMPCLK_SEL;
881 mixctrl &= ~(MIX_CTRL_FBCLK_SEL | MIX_CTRL_AUTO_TUNE_EN);
882
883 val |= MIX_CTRL_EXE_TUNE;
884 mixctrl |= MIX_CTRL_FBCLK_SEL | MIX_CTRL_AUTO_TUNE_EN;
885
886 esdhc_write32(®s->autoc12err, val);
887 esdhc_write32(®s->mixctrl, mixctrl);
888 }
889
890 /* sdhci_writew(host, SDHCI_TRNS_READ, SDHCI_TRANSFER_MODE); */
891 mixctrl = esdhc_read32(®s->mixctrl);
892 mixctrl = MIX_CTRL_DTDSEL_READ | (mixctrl & ~MIX_CTRL_SDHCI_MASK);
893 esdhc_write32(®s->mixctrl, mixctrl);
894
895 esdhc_write32(®s->irqstaten, IRQSTATEN_BRR);
896 esdhc_write32(®s->irqsigen, IRQSTATEN_BRR);
897
898 /*
899 * Issue opcode repeatedly till Execute Tuning is set to 0 or the number
900 * of loops reaches 40 times.
901 */
902 for (i = 0; i < MAX_TUNING_LOOP; i++) {
903 u32 ctrl;
904
905 if (opcode == MMC_CMD_SEND_TUNING_BLOCK_HS200) {
906 if (mmc->bus_width == 8)
907 esdhc_write32(®s->blkattr, 0x7080);
908 else if (mmc->bus_width == 4)
909 esdhc_write32(®s->blkattr, 0x7040);
910 } else {
911 esdhc_write32(®s->blkattr, 0x7040);
912 }
913
914 /* sdhci_writew(host, SDHCI_TRNS_READ, SDHCI_TRANSFER_MODE) */
915 val = esdhc_read32(®s->mixctrl);
916 val = MIX_CTRL_DTDSEL_READ | (val & ~MIX_CTRL_SDHCI_MASK);
917 esdhc_write32(®s->mixctrl, val);
918
919 /* We are using STD tuning, no need to check return value */
920 mmc_send_tuning(mmc, opcode, NULL);
921
922 ctrl = esdhc_read32(®s->autoc12err);
923 if ((!(ctrl & MIX_CTRL_EXE_TUNE)) &&
924 (ctrl & MIX_CTRL_SMPCLK_SEL)) {
925 ret = 0;
926 break;
927 }
928 }
929
930 esdhc_write32(®s->irqstaten, irqstaten);
931 esdhc_write32(®s->irqsigen, irqsigen);
932
933 esdhc_stop_tuning(mmc);
934
935 return ret;
936 }
937 #endif
938
esdhc_set_ios_common(struct fsl_esdhc_priv * priv,struct mmc * mmc)939 static int esdhc_set_ios_common(struct fsl_esdhc_priv *priv, struct mmc *mmc)
940 {
941 struct fsl_esdhc *regs = priv->esdhc_regs;
942 int ret __maybe_unused;
943 u32 clock;
944
945 #ifdef MMC_SUPPORTS_TUNING
946 /*
947 * call esdhc_set_timing() before update the clock rate,
948 * This is because current we support DDR and SDR mode,
949 * Once the DDR_EN bit is set, the card clock will be
950 * divide by 2 automatically. So need to do this before
951 * setting clock rate.
952 */
953 if (priv->mode != mmc->selected_mode) {
954 ret = esdhc_set_timing(mmc);
955 if (ret) {
956 printf("esdhc_set_timing error %d\n", ret);
957 return ret;
958 }
959 }
960 #endif
961
962 /* Set the clock speed */
963 clock = mmc->clock;
964 if (clock < mmc->cfg->f_min)
965 clock = mmc->cfg->f_min;
966
967 if (priv->clock != clock)
968 set_sysctl(priv, mmc, clock);
969
970 #ifdef MMC_SUPPORTS_TUNING
971 if (mmc->clk_disable) {
972 #ifdef CONFIG_FSL_USDHC
973 esdhc_clrbits32(®s->vendorspec, VENDORSPEC_CKEN);
974 #else
975 esdhc_clrbits32(®s->sysctl, SYSCTL_CKEN);
976 #endif
977 } else {
978 #ifdef CONFIG_FSL_USDHC
979 esdhc_setbits32(®s->vendorspec, VENDORSPEC_PEREN |
980 VENDORSPEC_CKEN);
981 #else
982 esdhc_setbits32(®s->sysctl, SYSCTL_PEREN | SYSCTL_CKEN);
983 #endif
984 }
985
986 /*
987 * For HS400/HS400ES mode, make sure set the strobe dll in the
988 * target clock rate. So call esdhc_set_strobe_dll() after the
989 * clock updated.
990 */
991 if (mmc->selected_mode == MMC_HS_400 || mmc->selected_mode == MMC_HS_400_ES)
992 esdhc_set_strobe_dll(mmc);
993
994 if (priv->signal_voltage != mmc->signal_voltage) {
995 ret = esdhc_set_voltage(mmc);
996 if (ret) {
997 if (ret != -ENOTSUPP)
998 printf("esdhc_set_voltage error %d\n", ret);
999 return ret;
1000 }
1001 }
1002 #endif
1003
1004 /* Set the bus width */
1005 esdhc_clrbits32(®s->proctl, PROCTL_DTW_4 | PROCTL_DTW_8);
1006
1007 if (mmc->bus_width == 4)
1008 esdhc_setbits32(®s->proctl, PROCTL_DTW_4);
1009 else if (mmc->bus_width == 8)
1010 esdhc_setbits32(®s->proctl, PROCTL_DTW_8);
1011
1012 return 0;
1013 }
1014
esdhc_init_common(struct fsl_esdhc_priv * priv,struct mmc * mmc)1015 static int esdhc_init_common(struct fsl_esdhc_priv *priv, struct mmc *mmc)
1016 {
1017 struct fsl_esdhc *regs = priv->esdhc_regs;
1018 ulong start;
1019
1020 /* Reset the entire host controller */
1021 esdhc_setbits32(®s->sysctl, SYSCTL_RSTA);
1022
1023 /* Wait until the controller is available */
1024 start = get_timer(0);
1025 while ((esdhc_read32(®s->sysctl) & SYSCTL_RSTA)) {
1026 if (get_timer(start) > 1000)
1027 return -ETIMEDOUT;
1028 }
1029
1030 #if defined(CONFIG_FSL_USDHC)
1031 /* RSTA doesn't reset MMC_BOOT register, so manually reset it */
1032 esdhc_write32(®s->mmcboot, 0x0);
1033 /* Reset MIX_CTRL and CLK_TUNE_CTRL_STATUS regs to 0 */
1034 esdhc_write32(®s->mixctrl, 0x0);
1035 esdhc_write32(®s->clktunectrlstatus, 0x0);
1036
1037 /* Put VEND_SPEC to default value */
1038 if (priv->vs18_enable)
1039 esdhc_write32(®s->vendorspec, (VENDORSPEC_INIT |
1040 ESDHC_VENDORSPEC_VSELECT));
1041 else
1042 esdhc_write32(®s->vendorspec, VENDORSPEC_INIT);
1043
1044 /* Disable DLL_CTRL delay line */
1045 esdhc_write32(®s->dllctrl, 0x0);
1046 #endif
1047
1048 #ifndef ARCH_MXC
1049 /* Enable cache snooping */
1050 esdhc_write32(®s->scr, 0x00000040);
1051 #endif
1052
1053 #ifndef CONFIG_FSL_USDHC
1054 esdhc_setbits32(®s->sysctl, SYSCTL_HCKEN | SYSCTL_IPGEN);
1055 #else
1056 esdhc_setbits32(®s->vendorspec, VENDORSPEC_HCKEN | VENDORSPEC_IPGEN);
1057 #endif
1058
1059 /* Set the initial clock speed */
1060 mmc_set_clock(mmc, 400000, MMC_CLK_ENABLE);
1061
1062 /* Disable the BRR and BWR bits in IRQSTAT */
1063 esdhc_clrbits32(®s->irqstaten, IRQSTATEN_BRR | IRQSTATEN_BWR);
1064
1065 #ifdef CONFIG_MCF5441x
1066 esdhc_write32(®s->proctl, PROCTL_INIT | PROCTL_D3CD);
1067 #else
1068 /* Put the PROCTL reg back to the default */
1069 esdhc_write32(®s->proctl, PROCTL_INIT);
1070 #endif
1071
1072 /* Set timout to the maximum value */
1073 esdhc_clrsetbits32(®s->sysctl, SYSCTL_TIMEOUT_MASK, 14 << 16);
1074
1075 return 0;
1076 }
1077
esdhc_getcd_common(struct fsl_esdhc_priv * priv)1078 static int esdhc_getcd_common(struct fsl_esdhc_priv *priv)
1079 {
1080 struct fsl_esdhc *regs = priv->esdhc_regs;
1081 int timeout = 1000;
1082
1083 #ifdef CONFIG_ESDHC_DETECT_QUIRK
1084 if (CONFIG_ESDHC_DETECT_QUIRK)
1085 return 1;
1086 #endif
1087
1088 #if CONFIG_IS_ENABLED(DM_MMC)
1089 if (priv->non_removable)
1090 return 1;
1091
1092 if (priv->broken_cd)
1093 return 1;
1094 #if CONFIG_IS_ENABLED(DM_GPIO)
1095 if (dm_gpio_is_valid(&priv->cd_gpio))
1096 return dm_gpio_get_value(&priv->cd_gpio);
1097 #endif
1098 #endif
1099
1100 while (!(esdhc_read32(®s->prsstat) & PRSSTAT_CINS) && --timeout)
1101 udelay(1000);
1102
1103 return timeout > 0;
1104 }
1105
esdhc_reset(struct fsl_esdhc * regs)1106 static int esdhc_reset(struct fsl_esdhc *regs)
1107 {
1108 ulong start;
1109
1110 /* reset the controller */
1111 esdhc_setbits32(®s->sysctl, SYSCTL_RSTA);
1112
1113 /* hardware clears the bit when it is done */
1114 start = get_timer(0);
1115 while ((esdhc_read32(®s->sysctl) & SYSCTL_RSTA)) {
1116 if (get_timer(start) > 100) {
1117 printf("MMC/SD: Reset never completed.\n");
1118 return -ETIMEDOUT;
1119 }
1120 }
1121
1122 return 0;
1123 }
1124
1125 #if !CONFIG_IS_ENABLED(DM_MMC)
esdhc_getcd(struct mmc * mmc)1126 static int esdhc_getcd(struct mmc *mmc)
1127 {
1128 struct fsl_esdhc_priv *priv = mmc->priv;
1129
1130 return esdhc_getcd_common(priv);
1131 }
1132
esdhc_init(struct mmc * mmc)1133 static int esdhc_init(struct mmc *mmc)
1134 {
1135 struct fsl_esdhc_priv *priv = mmc->priv;
1136
1137 return esdhc_init_common(priv, mmc);
1138 }
1139
esdhc_send_cmd(struct mmc * mmc,struct mmc_cmd * cmd,struct mmc_data * data)1140 static int esdhc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd,
1141 struct mmc_data *data)
1142 {
1143 struct fsl_esdhc_priv *priv = mmc->priv;
1144
1145 return esdhc_send_cmd_common(priv, mmc, cmd, data);
1146 }
1147
esdhc_set_ios(struct mmc * mmc)1148 static int esdhc_set_ios(struct mmc *mmc)
1149 {
1150 struct fsl_esdhc_priv *priv = mmc->priv;
1151
1152 return esdhc_set_ios_common(priv, mmc);
1153 }
1154
1155 static const struct mmc_ops esdhc_ops = {
1156 .getcd = esdhc_getcd,
1157 .init = esdhc_init,
1158 .send_cmd = esdhc_send_cmd,
1159 .set_ios = esdhc_set_ios,
1160 };
1161 #endif
1162
fsl_esdhc_init(struct fsl_esdhc_priv * priv,struct fsl_esdhc_plat * plat)1163 static int fsl_esdhc_init(struct fsl_esdhc_priv *priv,
1164 struct fsl_esdhc_plat *plat)
1165 {
1166 struct mmc_config *cfg;
1167 struct fsl_esdhc *regs;
1168 u32 caps, voltage_caps;
1169 int ret;
1170
1171 if (!priv)
1172 return -EINVAL;
1173
1174 regs = priv->esdhc_regs;
1175
1176 /* First reset the eSDHC controller */
1177 ret = esdhc_reset(regs);
1178 if (ret)
1179 return ret;
1180
1181 #ifdef CONFIG_MCF5441x
1182 /* ColdFire, using SDHC_DATA[3] for card detection */
1183 esdhc_write32(®s->proctl, PROCTL_INIT | PROCTL_D3CD);
1184 #endif
1185
1186 #ifndef CONFIG_FSL_USDHC
1187 esdhc_setbits32(®s->sysctl, SYSCTL_PEREN | SYSCTL_HCKEN
1188 | SYSCTL_IPGEN | SYSCTL_CKEN);
1189 /* Clearing tuning bits in case ROM has set it already */
1190 esdhc_write32(®s->mixctrl, 0);
1191 esdhc_write32(®s->autoc12err, 0);
1192 esdhc_write32(®s->clktunectrlstatus, 0);
1193 #else
1194 esdhc_setbits32(®s->vendorspec, VENDORSPEC_PEREN |
1195 VENDORSPEC_HCKEN | VENDORSPEC_IPGEN | VENDORSPEC_CKEN);
1196 #endif
1197
1198 if (priv->vs18_enable)
1199 esdhc_setbits32(®s->vendorspec, ESDHC_VENDORSPEC_VSELECT);
1200
1201 esdhc_write32(®s->irqstaten, SDHCI_IRQ_EN_BITS);
1202 cfg = &plat->cfg;
1203 #ifndef CONFIG_DM_MMC
1204 memset(cfg, '\0', sizeof(*cfg));
1205 #endif
1206
1207 voltage_caps = 0;
1208 caps = esdhc_read32(®s->hostcapblt);
1209
1210 #ifdef CONFIG_MCF5441x
1211 /*
1212 * MCF5441x RM declares in more points that sdhc clock speed must
1213 * never exceed 25 Mhz. From this, the HS bit needs to be disabled
1214 * from host capabilities.
1215 */
1216 caps &= ~ESDHC_HOSTCAPBLT_HSS;
1217 #endif
1218
1219 #ifdef CONFIG_SYS_FSL_ERRATUM_ESDHC135
1220 caps = caps & ~(ESDHC_HOSTCAPBLT_SRS |
1221 ESDHC_HOSTCAPBLT_VS18 | ESDHC_HOSTCAPBLT_VS30);
1222 #endif
1223
1224 if (caps & ESDHC_HOSTCAPBLT_VS18)
1225 voltage_caps |= MMC_VDD_165_195;
1226 if (caps & ESDHC_HOSTCAPBLT_VS30)
1227 voltage_caps |= MMC_VDD_29_30 | MMC_VDD_30_31;
1228 if (caps & ESDHC_HOSTCAPBLT_VS33)
1229 voltage_caps |= MMC_VDD_32_33 | MMC_VDD_33_34;
1230
1231 cfg->name = "FSL_SDHC";
1232 #if !CONFIG_IS_ENABLED(DM_MMC)
1233 cfg->ops = &esdhc_ops;
1234 #endif
1235 #ifdef CONFIG_SYS_SD_VOLTAGE
1236 cfg->voltages = CONFIG_SYS_SD_VOLTAGE;
1237 #else
1238 cfg->voltages = MMC_VDD_32_33 | MMC_VDD_33_34;
1239 #endif
1240 if ((cfg->voltages & voltage_caps) == 0) {
1241 printf("voltage not supported by controller\n");
1242 return -1;
1243 }
1244
1245 if (priv->bus_width == 8)
1246 cfg->host_caps = MMC_MODE_4BIT | MMC_MODE_8BIT;
1247 else if (priv->bus_width == 4)
1248 cfg->host_caps = MMC_MODE_4BIT;
1249
1250 cfg->host_caps = MMC_MODE_4BIT | MMC_MODE_8BIT;
1251 #ifdef CONFIG_SYS_FSL_ESDHC_HAS_DDR_MODE
1252 cfg->host_caps |= MMC_MODE_DDR_52MHz;
1253 #endif
1254
1255 if (priv->bus_width > 0) {
1256 if (priv->bus_width < 8)
1257 cfg->host_caps &= ~MMC_MODE_8BIT;
1258 if (priv->bus_width < 4)
1259 cfg->host_caps &= ~MMC_MODE_4BIT;
1260 }
1261
1262 if (caps & ESDHC_HOSTCAPBLT_HSS)
1263 cfg->host_caps |= MMC_MODE_HS_52MHz | MMC_MODE_HS;
1264
1265 #ifdef CONFIG_ESDHC_DETECT_8_BIT_QUIRK
1266 if (CONFIG_ESDHC_DETECT_8_BIT_QUIRK)
1267 cfg->host_caps &= ~MMC_MODE_8BIT;
1268 #endif
1269
1270 cfg->host_caps |= priv->caps;
1271
1272 cfg->f_min = 400000;
1273 cfg->f_max = min(priv->sdhc_clk, (u32)200000000);
1274
1275 cfg->b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT;
1276
1277 esdhc_write32(®s->dllctrl, 0);
1278 if (priv->flags & ESDHC_FLAG_USDHC) {
1279 if (priv->flags & ESDHC_FLAG_STD_TUNING) {
1280 u32 val = esdhc_read32(®s->tuning_ctrl);
1281
1282 val |= ESDHC_STD_TUNING_EN;
1283 val &= ~ESDHC_TUNING_START_TAP_MASK;
1284 val |= priv->tuning_start_tap;
1285 val &= ~ESDHC_TUNING_STEP_MASK;
1286 val |= (priv->tuning_step) << ESDHC_TUNING_STEP_SHIFT;
1287
1288 /* Disable the CMD CRC check for tuning, if not, need to
1289 * add some delay after every tuning command, because
1290 * hardware standard tuning logic will directly go to next
1291 * step once it detect the CMD CRC error, will not wait for
1292 * the card side to finally send out the tuning data, trigger
1293 * the buffer read ready interrupt immediately. If usdhc send
1294 * the next tuning command some eMMC card will stuck, can't
1295 * response, block the tuning procedure or the first command
1296 * after the whole tuning procedure always can't get any response.
1297 */
1298 val |= ESDHC_TUNING_CMD_CRC_CHECK_DISABLE;
1299 esdhc_write32(®s->tuning_ctrl, val);
1300 }
1301 }
1302
1303 return 0;
1304 }
1305
1306 #if !CONFIG_IS_ENABLED(DM_MMC)
fsl_esdhc_cfg_to_priv(struct fsl_esdhc_cfg * cfg,struct fsl_esdhc_priv * priv)1307 static int fsl_esdhc_cfg_to_priv(struct fsl_esdhc_cfg *cfg,
1308 struct fsl_esdhc_priv *priv)
1309 {
1310 if (!cfg || !priv)
1311 return -EINVAL;
1312
1313 priv->esdhc_regs = (struct fsl_esdhc *)(unsigned long)(cfg->esdhc_base);
1314 priv->bus_width = cfg->max_bus_width;
1315 priv->sdhc_clk = cfg->sdhc_clk;
1316 priv->wp_enable = cfg->wp_enable;
1317 priv->vs18_enable = cfg->vs18_enable;
1318
1319 return 0;
1320 };
1321
fsl_esdhc_initialize(struct bd_info * bis,struct fsl_esdhc_cfg * cfg)1322 int fsl_esdhc_initialize(struct bd_info *bis, struct fsl_esdhc_cfg *cfg)
1323 {
1324 struct fsl_esdhc_plat *plat;
1325 struct fsl_esdhc_priv *priv;
1326 struct mmc *mmc;
1327 int ret;
1328
1329 if (!cfg)
1330 return -EINVAL;
1331
1332 priv = calloc(sizeof(struct fsl_esdhc_priv), 1);
1333 if (!priv)
1334 return -ENOMEM;
1335 plat = calloc(sizeof(struct fsl_esdhc_plat), 1);
1336 if (!plat) {
1337 free(priv);
1338 return -ENOMEM;
1339 }
1340
1341 ret = fsl_esdhc_cfg_to_priv(cfg, priv);
1342 if (ret) {
1343 debug("%s xlate failure\n", __func__);
1344 free(plat);
1345 free(priv);
1346 return ret;
1347 }
1348
1349 ret = fsl_esdhc_init(priv, plat);
1350 if (ret) {
1351 debug("%s init failure\n", __func__);
1352 free(plat);
1353 free(priv);
1354 return ret;
1355 }
1356
1357 mmc = mmc_create(&plat->cfg, priv);
1358 if (!mmc)
1359 return -EIO;
1360
1361 priv->mmc = mmc;
1362
1363 return 0;
1364 }
1365
fsl_esdhc_mmc_init(struct bd_info * bis)1366 int fsl_esdhc_mmc_init(struct bd_info *bis)
1367 {
1368 struct fsl_esdhc_cfg *cfg;
1369
1370 cfg = calloc(sizeof(struct fsl_esdhc_cfg), 1);
1371 cfg->esdhc_base = CONFIG_SYS_FSL_ESDHC_ADDR;
1372 cfg->sdhc_clk = gd->arch.sdhc_clk;
1373 return fsl_esdhc_initialize(bis, cfg);
1374 }
1375 #endif
1376
1377 #ifdef CONFIG_OF_LIBFDT
esdhc_status_fixup(void * blob,const char * compat)1378 __weak int esdhc_status_fixup(void *blob, const char *compat)
1379 {
1380 #ifdef CONFIG_FSL_ESDHC_PIN_MUX
1381 if (!hwconfig("esdhc")) {
1382 do_fixup_by_compat(blob, compat, "status", "disabled",
1383 sizeof("disabled"), 1);
1384 return 1;
1385 }
1386 #endif
1387 return 0;
1388 }
1389
fdt_fixup_esdhc(void * blob,struct bd_info * bd)1390 void fdt_fixup_esdhc(void *blob, struct bd_info *bd)
1391 {
1392 const char *compat = "fsl,esdhc";
1393
1394 if (esdhc_status_fixup(blob, compat))
1395 return;
1396
1397 do_fixup_by_compat_u32(blob, compat, "clock-frequency",
1398 gd->arch.sdhc_clk, 1);
1399 }
1400 #endif
1401
1402 #if CONFIG_IS_ENABLED(DM_MMC)
1403 #include <asm/arch/clock.h>
init_clk_usdhc(u32 index)1404 __weak void init_clk_usdhc(u32 index)
1405 {
1406 }
1407
fsl_esdhc_of_to_plat(struct udevice * dev)1408 static int fsl_esdhc_of_to_plat(struct udevice *dev)
1409 {
1410 #if !CONFIG_IS_ENABLED(OF_PLATDATA)
1411 struct fsl_esdhc_priv *priv = dev_get_priv(dev);
1412 #if CONFIG_IS_ENABLED(DM_REGULATOR)
1413 struct udevice *vqmmc_dev;
1414 int ret;
1415 #endif
1416 const void *fdt = gd->fdt_blob;
1417 int node = dev_of_offset(dev);
1418
1419 fdt_addr_t addr;
1420 unsigned int val;
1421
1422 addr = dev_read_addr(dev);
1423 if (addr == FDT_ADDR_T_NONE)
1424 return -EINVAL;
1425 priv->esdhc_regs = (struct fsl_esdhc *)addr;
1426 priv->dev = dev;
1427 priv->mode = -1;
1428
1429 val = dev_read_u32_default(dev, "bus-width", -1);
1430 if (val == 8)
1431 priv->bus_width = 8;
1432 else if (val == 4)
1433 priv->bus_width = 4;
1434 else
1435 priv->bus_width = 1;
1436
1437 val = fdtdec_get_int(fdt, node, "fsl,tuning-step", 1);
1438 priv->tuning_step = val;
1439 val = fdtdec_get_int(fdt, node, "fsl,tuning-start-tap",
1440 ESDHC_TUNING_START_TAP_DEFAULT);
1441 priv->tuning_start_tap = val;
1442 val = fdtdec_get_int(fdt, node, "fsl,strobe-dll-delay-target",
1443 ESDHC_STROBE_DLL_CTRL_SLV_DLY_TARGET_DEFAULT);
1444 priv->strobe_dll_delay_target = val;
1445 val = fdtdec_get_int(fdt, node, "fsl,signal-voltage-switch-extra-delay-ms", 0);
1446 priv->signal_voltage_switch_extra_delay_ms = val;
1447
1448 if (dev_read_bool(dev, "broken-cd"))
1449 priv->broken_cd = 1;
1450
1451 if (dev_read_bool(dev, "non-removable")) {
1452 priv->non_removable = 1;
1453 } else {
1454 priv->non_removable = 0;
1455 #if CONFIG_IS_ENABLED(DM_GPIO)
1456 gpio_request_by_name(dev, "cd-gpios", 0, &priv->cd_gpio,
1457 GPIOD_IS_IN);
1458 #endif
1459 }
1460
1461 if (dev_read_prop(dev, "fsl,wp-controller", NULL)) {
1462 priv->wp_enable = 1;
1463 } else {
1464 priv->wp_enable = 0;
1465 #if CONFIG_IS_ENABLED(DM_GPIO)
1466 gpio_request_by_name(dev, "wp-gpios", 0, &priv->wp_gpio,
1467 GPIOD_IS_IN);
1468 #endif
1469 }
1470
1471 priv->vs18_enable = 0;
1472
1473 #if CONFIG_IS_ENABLED(DM_REGULATOR)
1474 /*
1475 * If emmc I/O has a fixed voltage at 1.8V, this must be provided,
1476 * otherwise, emmc will work abnormally.
1477 */
1478 ret = device_get_supply_regulator(dev, "vqmmc-supply", &vqmmc_dev);
1479 if (ret) {
1480 dev_dbg(dev, "no vqmmc-supply\n");
1481 } else {
1482 priv->vqmmc_dev = vqmmc_dev;
1483 ret = regulator_set_enable(vqmmc_dev, true);
1484 if (ret) {
1485 dev_err(dev, "fail to enable vqmmc-supply\n");
1486 return ret;
1487 }
1488
1489 if (regulator_get_value(vqmmc_dev) == 1800000)
1490 priv->vs18_enable = 1;
1491 }
1492 #endif
1493 #endif
1494 return 0;
1495 }
1496
fsl_esdhc_probe(struct udevice * dev)1497 static int fsl_esdhc_probe(struct udevice *dev)
1498 {
1499 struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
1500 struct fsl_esdhc_plat *plat = dev_get_plat(dev);
1501 struct fsl_esdhc_priv *priv = dev_get_priv(dev);
1502 struct esdhc_soc_data *data =
1503 (struct esdhc_soc_data *)dev_get_driver_data(dev);
1504 struct mmc *mmc;
1505 #if !CONFIG_IS_ENABLED(BLK)
1506 struct blk_desc *bdesc;
1507 #endif
1508 int ret;
1509
1510 #if CONFIG_IS_ENABLED(OF_PLATDATA)
1511 struct dtd_fsl_esdhc *dtplat = &plat->dtplat;
1512 unsigned int val;
1513
1514 priv->esdhc_regs = map_sysmem(dtplat->reg[0], dtplat->reg[1]);
1515 val = plat->dtplat.bus_width;
1516 if (val == 8)
1517 priv->bus_width = 8;
1518 else if (val == 4)
1519 priv->bus_width = 4;
1520 else
1521 priv->bus_width = 1;
1522
1523 if (dtplat->non_removable)
1524 priv->non_removable = 1;
1525 else
1526 priv->non_removable = 0;
1527
1528 if (CONFIG_IS_ENABLED(DM_GPIO) && !priv->non_removable) {
1529 struct udevice *gpiodev;
1530
1531 ret = device_get_by_ofplat_idx(dtplat->cd_gpios->idx, &gpiodev);
1532 if (ret)
1533 return ret;
1534
1535 ret = gpio_dev_request_index(gpiodev, gpiodev->name, "cd-gpios",
1536 dtplat->cd_gpios->arg[0], GPIOD_IS_IN,
1537 dtplat->cd_gpios->arg[1], &priv->cd_gpio);
1538
1539 if (ret)
1540 return ret;
1541 }
1542 #endif
1543
1544 if (data)
1545 priv->flags = data->flags;
1546
1547 /*
1548 * TODO:
1549 * Because lack of clk driver, if SDHC clk is not enabled,
1550 * need to enable it first before this driver is invoked.
1551 *
1552 * we use MXC_ESDHC_CLK to get clk freq.
1553 * If one would like to make this function work,
1554 * the aliases should be provided in dts as this:
1555 *
1556 * aliases {
1557 * mmc0 = &usdhc1;
1558 * mmc1 = &usdhc2;
1559 * mmc2 = &usdhc3;
1560 * mmc3 = &usdhc4;
1561 * };
1562 * Then if your board only supports mmc2 and mmc3, but we can
1563 * correctly get the seq as 2 and 3, then let mxc_get_clock
1564 * work as expected.
1565 */
1566
1567 init_clk_usdhc(dev_seq(dev));
1568
1569 #if CONFIG_IS_ENABLED(CLK)
1570 /* Assigned clock already set clock */
1571 ret = clk_get_by_name(dev, "per", &priv->per_clk);
1572 if (ret) {
1573 printf("Failed to get per_clk\n");
1574 return ret;
1575 }
1576 ret = clk_enable(&priv->per_clk);
1577 if (ret) {
1578 printf("Failed to enable per_clk\n");
1579 return ret;
1580 }
1581
1582 priv->sdhc_clk = clk_get_rate(&priv->per_clk);
1583 #else
1584 priv->sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK + dev_seq(dev));
1585 if (priv->sdhc_clk <= 0) {
1586 dev_err(dev, "Unable to get clk for %s\n", dev->name);
1587 return -EINVAL;
1588 }
1589 #endif
1590
1591 ret = fsl_esdhc_init(priv, plat);
1592 if (ret) {
1593 dev_err(dev, "fsl_esdhc_init failure\n");
1594 return ret;
1595 }
1596
1597 #if !CONFIG_IS_ENABLED(OF_PLATDATA)
1598 ret = mmc_of_parse(dev, &plat->cfg);
1599 if (ret)
1600 return ret;
1601 #endif
1602
1603 mmc = &plat->mmc;
1604 mmc->cfg = &plat->cfg;
1605 mmc->dev = dev;
1606 #if !CONFIG_IS_ENABLED(BLK)
1607 mmc->priv = priv;
1608
1609 /* Setup dsr related values */
1610 mmc->dsr_imp = 0;
1611 mmc->dsr = ESDHC_DRIVER_STAGE_VALUE;
1612 /* Setup the universal parts of the block interface just once */
1613 bdesc = mmc_get_blk_desc(mmc);
1614 bdesc->if_type = IF_TYPE_MMC;
1615 bdesc->removable = 1;
1616 bdesc->devnum = mmc_get_next_devnum();
1617 bdesc->block_read = mmc_bread;
1618 bdesc->block_write = mmc_bwrite;
1619 bdesc->block_erase = mmc_berase;
1620
1621 /* setup initial part type */
1622 bdesc->part_type = mmc->cfg->part_type;
1623 mmc_list_add(mmc);
1624 #endif
1625
1626 upriv->mmc = mmc;
1627
1628 return esdhc_init_common(priv, mmc);
1629 }
1630
1631 #if CONFIG_IS_ENABLED(DM_MMC)
fsl_esdhc_get_cd(struct udevice * dev)1632 static int fsl_esdhc_get_cd(struct udevice *dev)
1633 {
1634 struct fsl_esdhc_priv *priv = dev_get_priv(dev);
1635
1636 return esdhc_getcd_common(priv);
1637 }
1638
fsl_esdhc_send_cmd(struct udevice * dev,struct mmc_cmd * cmd,struct mmc_data * data)1639 static int fsl_esdhc_send_cmd(struct udevice *dev, struct mmc_cmd *cmd,
1640 struct mmc_data *data)
1641 {
1642 struct fsl_esdhc_plat *plat = dev_get_plat(dev);
1643 struct fsl_esdhc_priv *priv = dev_get_priv(dev);
1644
1645 return esdhc_send_cmd_common(priv, &plat->mmc, cmd, data);
1646 }
1647
fsl_esdhc_set_ios(struct udevice * dev)1648 static int fsl_esdhc_set_ios(struct udevice *dev)
1649 {
1650 struct fsl_esdhc_plat *plat = dev_get_plat(dev);
1651 struct fsl_esdhc_priv *priv = dev_get_priv(dev);
1652
1653 return esdhc_set_ios_common(priv, &plat->mmc);
1654 }
1655
1656 #if CONFIG_IS_ENABLED(MMC_HS400_ES_SUPPORT)
fsl_esdhc_set_enhanced_strobe(struct udevice * dev)1657 static int fsl_esdhc_set_enhanced_strobe(struct udevice *dev)
1658 {
1659 struct fsl_esdhc_priv *priv = dev_get_priv(dev);
1660 struct fsl_esdhc *regs = priv->esdhc_regs;
1661 u32 m;
1662
1663 m = esdhc_read32(®s->mixctrl);
1664 m |= MIX_CTRL_HS400_ES;
1665 esdhc_write32(®s->mixctrl, m);
1666
1667 return 0;
1668 }
1669 #endif
1670
fsl_esdhc_wait_dat0(struct udevice * dev,int state,int timeout_us)1671 static int fsl_esdhc_wait_dat0(struct udevice *dev, int state,
1672 int timeout_us)
1673 {
1674 int ret;
1675 u32 tmp;
1676 struct fsl_esdhc_priv *priv = dev_get_priv(dev);
1677 struct fsl_esdhc *regs = priv->esdhc_regs;
1678
1679 ret = readx_poll_timeout(esdhc_read32, ®s->prsstat, tmp,
1680 !!(tmp & PRSSTAT_DAT0) == !!state,
1681 timeout_us);
1682 return ret;
1683 }
1684
1685 static const struct dm_mmc_ops fsl_esdhc_ops = {
1686 .get_cd = fsl_esdhc_get_cd,
1687 .send_cmd = fsl_esdhc_send_cmd,
1688 .set_ios = fsl_esdhc_set_ios,
1689 #ifdef MMC_SUPPORTS_TUNING
1690 .execute_tuning = fsl_esdhc_execute_tuning,
1691 #endif
1692 #if CONFIG_IS_ENABLED(MMC_HS400_ES_SUPPORT)
1693 .set_enhanced_strobe = fsl_esdhc_set_enhanced_strobe,
1694 #endif
1695 .wait_dat0 = fsl_esdhc_wait_dat0,
1696 };
1697 #endif
1698
1699 static struct esdhc_soc_data usdhc_imx7d_data = {
1700 .flags = ESDHC_FLAG_USDHC | ESDHC_FLAG_STD_TUNING
1701 | ESDHC_FLAG_HAVE_CAP1 | ESDHC_FLAG_HS200
1702 | ESDHC_FLAG_HS400,
1703 };
1704
1705 static struct esdhc_soc_data usdhc_imx8qm_data = {
1706 .flags = ESDHC_FLAG_USDHC | ESDHC_FLAG_STD_TUNING |
1707 ESDHC_FLAG_HAVE_CAP1 | ESDHC_FLAG_HS200 |
1708 ESDHC_FLAG_HS400 | ESDHC_FLAG_HS400_ES,
1709 };
1710
1711 static const struct udevice_id fsl_esdhc_ids[] = {
1712 { .compatible = "fsl,imx51-esdhc", },
1713 { .compatible = "fsl,imx53-esdhc", },
1714 { .compatible = "fsl,imx6ul-usdhc", },
1715 { .compatible = "fsl,imx6sx-usdhc", },
1716 { .compatible = "fsl,imx6sl-usdhc", },
1717 { .compatible = "fsl,imx6q-usdhc", },
1718 { .compatible = "fsl,imx7d-usdhc", .data = (ulong)&usdhc_imx7d_data,},
1719 { .compatible = "fsl,imx7ulp-usdhc", },
1720 { .compatible = "fsl,imx8qm-usdhc", .data = (ulong)&usdhc_imx8qm_data,},
1721 { .compatible = "fsl,imx8mm-usdhc", .data = (ulong)&usdhc_imx8qm_data,},
1722 { .compatible = "fsl,imx8mn-usdhc", .data = (ulong)&usdhc_imx8qm_data,},
1723 { .compatible = "fsl,imx8mq-usdhc", .data = (ulong)&usdhc_imx8qm_data,},
1724 { .compatible = "fsl,imxrt-usdhc", },
1725 { .compatible = "fsl,esdhc", },
1726 { /* sentinel */ }
1727 };
1728
1729 #if CONFIG_IS_ENABLED(BLK)
fsl_esdhc_bind(struct udevice * dev)1730 static int fsl_esdhc_bind(struct udevice *dev)
1731 {
1732 struct fsl_esdhc_plat *plat = dev_get_plat(dev);
1733
1734 return mmc_bind(dev, &plat->mmc, &plat->cfg);
1735 }
1736 #endif
1737
1738 U_BOOT_DRIVER(fsl_esdhc) = {
1739 .name = "fsl_esdhc",
1740 .id = UCLASS_MMC,
1741 .of_match = fsl_esdhc_ids,
1742 .of_to_plat = fsl_esdhc_of_to_plat,
1743 .ops = &fsl_esdhc_ops,
1744 #if CONFIG_IS_ENABLED(BLK)
1745 .bind = fsl_esdhc_bind,
1746 #endif
1747 .probe = fsl_esdhc_probe,
1748 .plat_auto = sizeof(struct fsl_esdhc_plat),
1749 .priv_auto = sizeof(struct fsl_esdhc_priv),
1750 };
1751
1752 DM_DRIVER_ALIAS(fsl_esdhc, fsl_imx6q_usdhc)
1753 #endif
1754