1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * R8A77990 processor support - PFC hardware block.
4 *
5 * Copyright (C) 2018-2019 Renesas Electronics Corp.
6 *
7 * This file is based on the drivers/pinctrl/renesas/pfc-r8a7796.c
8 *
9 * R8A7796 processor support - PFC hardware block.
10 *
11 * Copyright (C) 2016-2017 Renesas Electronics Corp.
12 */
13
14 #include <common.h>
15 #include <dm.h>
16 #include <errno.h>
17 #include <dm/pinctrl.h>
18 #include <linux/bitops.h>
19 #include <linux/kernel.h>
20
21 #include "sh_pfc.h"
22
23 #define CFG_FLAGS (SH_PFC_PIN_CFG_PULL_UP_DOWN)
24
25 #define CPU_ALL_GP(fn, sfx) \
26 PORT_GP_CFG_18(0, fn, sfx, CFG_FLAGS), \
27 PORT_GP_CFG_23(1, fn, sfx, CFG_FLAGS), \
28 PORT_GP_CFG_26(2, fn, sfx, CFG_FLAGS), \
29 PORT_GP_CFG_12(3, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE), \
30 PORT_GP_CFG_1(3, 12, fn, sfx, CFG_FLAGS), \
31 PORT_GP_CFG_1(3, 13, fn, sfx, CFG_FLAGS), \
32 PORT_GP_CFG_1(3, 14, fn, sfx, CFG_FLAGS), \
33 PORT_GP_CFG_1(3, 15, fn, sfx, CFG_FLAGS), \
34 PORT_GP_CFG_11(4, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE), \
35 PORT_GP_CFG_20(5, fn, sfx, CFG_FLAGS), \
36 PORT_GP_CFG_9(6, fn, sfx, CFG_FLAGS), \
37 PORT_GP_CFG_1(6, 9, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \
38 PORT_GP_CFG_1(6, 10, fn, sfx, CFG_FLAGS), \
39 PORT_GP_CFG_1(6, 11, fn, sfx, CFG_FLAGS), \
40 PORT_GP_CFG_1(6, 12, fn, sfx, CFG_FLAGS), \
41 PORT_GP_CFG_1(6, 13, fn, sfx, CFG_FLAGS), \
42 PORT_GP_CFG_1(6, 14, fn, sfx, CFG_FLAGS), \
43 PORT_GP_CFG_1(6, 15, fn, sfx, CFG_FLAGS), \
44 PORT_GP_CFG_1(6, 16, fn, sfx, CFG_FLAGS), \
45 PORT_GP_CFG_1(6, 17, fn, sfx, CFG_FLAGS)
46
47 #define CPU_ALL_NOGP(fn) \
48 PIN_NOGP_CFG(ASEBRK, "ASEBRK", fn, CFG_FLAGS), \
49 PIN_NOGP_CFG(AVB_MDC, "AVB_MDC", fn, CFG_FLAGS), \
50 PIN_NOGP_CFG(AVB_MDIO, "AVB_MDIO", fn, CFG_FLAGS), \
51 PIN_NOGP_CFG(AVB_TD0, "AVB_TD0", fn, CFG_FLAGS), \
52 PIN_NOGP_CFG(AVB_TD1, "AVB_TD1", fn, CFG_FLAGS), \
53 PIN_NOGP_CFG(AVB_TD2, "AVB_TD2", fn, CFG_FLAGS), \
54 PIN_NOGP_CFG(AVB_TD3, "AVB_TD3", fn, CFG_FLAGS), \
55 PIN_NOGP_CFG(AVB_TXC, "AVB_TXC", fn, CFG_FLAGS), \
56 PIN_NOGP_CFG(AVB_TX_CTL, "AVB_TX_CTL", fn, CFG_FLAGS), \
57 PIN_NOGP_CFG(FSCLKST_N, "FSCLKST_N", fn, CFG_FLAGS), \
58 PIN_NOGP_CFG(MLB_REF, "MLB_REF", fn, CFG_FLAGS), \
59 PIN_NOGP_CFG(PRESETOUT_N, "PRESETOUT_N", fn, CFG_FLAGS), \
60 PIN_NOGP_CFG(TCK, "TCK", fn, CFG_FLAGS), \
61 PIN_NOGP_CFG(TDI, "TDI", fn, CFG_FLAGS), \
62 PIN_NOGP_CFG(TMS, "TMS", fn, CFG_FLAGS), \
63 PIN_NOGP_CFG(TRST_N, "TRST_N", fn, CFG_FLAGS)
64
65 /*
66 * F_() : just information
67 * FM() : macro for FN_xxx / xxx_MARK
68 */
69
70 /* GPSR0 */
71 #define GPSR0_17 F_(SDA4, IP7_27_24)
72 #define GPSR0_16 F_(SCL4, IP7_23_20)
73 #define GPSR0_15 F_(D15, IP7_19_16)
74 #define GPSR0_14 F_(D14, IP7_15_12)
75 #define GPSR0_13 F_(D13, IP7_11_8)
76 #define GPSR0_12 F_(D12, IP7_7_4)
77 #define GPSR0_11 F_(D11, IP7_3_0)
78 #define GPSR0_10 F_(D10, IP6_31_28)
79 #define GPSR0_9 F_(D9, IP6_27_24)
80 #define GPSR0_8 F_(D8, IP6_23_20)
81 #define GPSR0_7 F_(D7, IP6_19_16)
82 #define GPSR0_6 F_(D6, IP6_15_12)
83 #define GPSR0_5 F_(D5, IP6_11_8)
84 #define GPSR0_4 F_(D4, IP6_7_4)
85 #define GPSR0_3 F_(D3, IP6_3_0)
86 #define GPSR0_2 F_(D2, IP5_31_28)
87 #define GPSR0_1 F_(D1, IP5_27_24)
88 #define GPSR0_0 F_(D0, IP5_23_20)
89
90 /* GPSR1 */
91 #define GPSR1_22 F_(WE0_N, IP5_19_16)
92 #define GPSR1_21 F_(CS0_N, IP5_15_12)
93 #define GPSR1_20 FM(CLKOUT)
94 #define GPSR1_19 F_(A19, IP5_11_8)
95 #define GPSR1_18 F_(A18, IP5_7_4)
96 #define GPSR1_17 F_(A17, IP5_3_0)
97 #define GPSR1_16 F_(A16, IP4_31_28)
98 #define GPSR1_15 F_(A15, IP4_27_24)
99 #define GPSR1_14 F_(A14, IP4_23_20)
100 #define GPSR1_13 F_(A13, IP4_19_16)
101 #define GPSR1_12 F_(A12, IP4_15_12)
102 #define GPSR1_11 F_(A11, IP4_11_8)
103 #define GPSR1_10 F_(A10, IP4_7_4)
104 #define GPSR1_9 F_(A9, IP4_3_0)
105 #define GPSR1_8 F_(A8, IP3_31_28)
106 #define GPSR1_7 F_(A7, IP3_27_24)
107 #define GPSR1_6 F_(A6, IP3_23_20)
108 #define GPSR1_5 F_(A5, IP3_19_16)
109 #define GPSR1_4 F_(A4, IP3_15_12)
110 #define GPSR1_3 F_(A3, IP3_11_8)
111 #define GPSR1_2 F_(A2, IP3_7_4)
112 #define GPSR1_1 F_(A1, IP3_3_0)
113 #define GPSR1_0 F_(A0, IP2_31_28)
114
115 /* GPSR2 */
116 #define GPSR2_25 F_(EX_WAIT0, IP2_27_24)
117 #define GPSR2_24 F_(RD_WR_N, IP2_23_20)
118 #define GPSR2_23 F_(RD_N, IP2_19_16)
119 #define GPSR2_22 F_(BS_N, IP2_15_12)
120 #define GPSR2_21 FM(AVB_PHY_INT)
121 #define GPSR2_20 F_(AVB_TXCREFCLK, IP2_3_0)
122 #define GPSR2_19 FM(AVB_RD3)
123 #define GPSR2_18 F_(AVB_RD2, IP1_31_28)
124 #define GPSR2_17 F_(AVB_RD1, IP1_27_24)
125 #define GPSR2_16 F_(AVB_RD0, IP1_23_20)
126 #define GPSR2_15 FM(AVB_RXC)
127 #define GPSR2_14 FM(AVB_RX_CTL)
128 #define GPSR2_13 F_(RPC_RESET_N, IP1_19_16)
129 #define GPSR2_12 F_(RPC_INT_N, IP1_15_12)
130 #define GPSR2_11 F_(QSPI1_SSL, IP1_11_8)
131 #define GPSR2_10 F_(QSPI1_IO3, IP1_7_4)
132 #define GPSR2_9 F_(QSPI1_IO2, IP1_3_0)
133 #define GPSR2_8 F_(QSPI1_MISO_IO1, IP0_31_28)
134 #define GPSR2_7 F_(QSPI1_MOSI_IO0, IP0_27_24)
135 #define GPSR2_6 F_(QSPI1_SPCLK, IP0_23_20)
136 #define GPSR2_5 FM(QSPI0_SSL)
137 #define GPSR2_4 F_(QSPI0_IO3, IP0_19_16)
138 #define GPSR2_3 F_(QSPI0_IO2, IP0_15_12)
139 #define GPSR2_2 F_(QSPI0_MISO_IO1, IP0_11_8)
140 #define GPSR2_1 F_(QSPI0_MOSI_IO0, IP0_7_4)
141 #define GPSR2_0 F_(QSPI0_SPCLK, IP0_3_0)
142
143 /* GPSR3 */
144 #define GPSR3_15 F_(SD1_WP, IP11_7_4)
145 #define GPSR3_14 F_(SD1_CD, IP11_3_0)
146 #define GPSR3_13 F_(SD0_WP, IP10_31_28)
147 #define GPSR3_12 F_(SD0_CD, IP10_27_24)
148 #define GPSR3_11 F_(SD1_DAT3, IP9_11_8)
149 #define GPSR3_10 F_(SD1_DAT2, IP9_7_4)
150 #define GPSR3_9 F_(SD1_DAT1, IP9_3_0)
151 #define GPSR3_8 F_(SD1_DAT0, IP8_31_28)
152 #define GPSR3_7 F_(SD1_CMD, IP8_27_24)
153 #define GPSR3_6 F_(SD1_CLK, IP8_23_20)
154 #define GPSR3_5 F_(SD0_DAT3, IP8_19_16)
155 #define GPSR3_4 F_(SD0_DAT2, IP8_15_12)
156 #define GPSR3_3 F_(SD0_DAT1, IP8_11_8)
157 #define GPSR3_2 F_(SD0_DAT0, IP8_7_4)
158 #define GPSR3_1 F_(SD0_CMD, IP8_3_0)
159 #define GPSR3_0 F_(SD0_CLK, IP7_31_28)
160
161 /* GPSR4 */
162 #define GPSR4_10 F_(SD3_DS, IP10_23_20)
163 #define GPSR4_9 F_(SD3_DAT7, IP10_19_16)
164 #define GPSR4_8 F_(SD3_DAT6, IP10_15_12)
165 #define GPSR4_7 F_(SD3_DAT5, IP10_11_8)
166 #define GPSR4_6 F_(SD3_DAT4, IP10_7_4)
167 #define GPSR4_5 F_(SD3_DAT3, IP10_3_0)
168 #define GPSR4_4 F_(SD3_DAT2, IP9_31_28)
169 #define GPSR4_3 F_(SD3_DAT1, IP9_27_24)
170 #define GPSR4_2 F_(SD3_DAT0, IP9_23_20)
171 #define GPSR4_1 F_(SD3_CMD, IP9_19_16)
172 #define GPSR4_0 F_(SD3_CLK, IP9_15_12)
173
174 /* GPSR5 */
175 #define GPSR5_19 F_(MLB_DAT, IP13_23_20)
176 #define GPSR5_18 F_(MLB_SIG, IP13_19_16)
177 #define GPSR5_17 F_(MLB_CLK, IP13_15_12)
178 #define GPSR5_16 F_(SSI_SDATA9, IP13_11_8)
179 #define GPSR5_15 F_(MSIOF0_SS2, IP13_7_4)
180 #define GPSR5_14 F_(MSIOF0_SS1, IP13_3_0)
181 #define GPSR5_13 F_(MSIOF0_SYNC, IP12_31_28)
182 #define GPSR5_12 F_(MSIOF0_TXD, IP12_27_24)
183 #define GPSR5_11 F_(MSIOF0_RXD, IP12_23_20)
184 #define GPSR5_10 F_(MSIOF0_SCK, IP12_19_16)
185 #define GPSR5_9 F_(RX2_A, IP12_15_12)
186 #define GPSR5_8 F_(TX2_A, IP12_11_8)
187 #define GPSR5_7 F_(SCK2_A, IP12_7_4)
188 #define GPSR5_6 F_(TX1, IP12_3_0)
189 #define GPSR5_5 F_(RX1, IP11_31_28)
190 #define GPSR5_4 F_(RTS0_N_A, IP11_23_20)
191 #define GPSR5_3 F_(CTS0_N_A, IP11_19_16)
192 #define GPSR5_2 F_(TX0_A, IP11_15_12)
193 #define GPSR5_1 F_(RX0_A, IP11_11_8)
194 #define GPSR5_0 F_(SCK0_A, IP11_27_24)
195
196 /* GPSR6 */
197 #define GPSR6_17 F_(USB30_PWEN, IP15_27_24)
198 #define GPSR6_16 F_(SSI_SDATA6, IP15_19_16)
199 #define GPSR6_15 F_(SSI_WS6, IP15_15_12)
200 #define GPSR6_14 F_(SSI_SCK6, IP15_11_8)
201 #define GPSR6_13 F_(SSI_SDATA5, IP15_7_4)
202 #define GPSR6_12 F_(SSI_WS5, IP15_3_0)
203 #define GPSR6_11 F_(SSI_SCK5, IP14_31_28)
204 #define GPSR6_10 F_(SSI_SDATA4, IP14_27_24)
205 #define GPSR6_9 F_(USB30_OVC, IP15_31_28)
206 #define GPSR6_8 F_(AUDIO_CLKA, IP15_23_20)
207 #define GPSR6_7 F_(SSI_SDATA3, IP14_23_20)
208 #define GPSR6_6 F_(SSI_WS349, IP14_19_16)
209 #define GPSR6_5 F_(SSI_SCK349, IP14_15_12)
210 #define GPSR6_4 F_(SSI_SDATA2, IP14_11_8)
211 #define GPSR6_3 F_(SSI_SDATA1, IP14_7_4)
212 #define GPSR6_2 F_(SSI_SDATA0, IP14_3_0)
213 #define GPSR6_1 F_(SSI_WS01239, IP13_31_28)
214 #define GPSR6_0 F_(SSI_SCK01239, IP13_27_24)
215
216 /* IPSRx */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */ /* 8 */ /* 9 - F */
217 #define IP0_3_0 FM(QSPI0_SPCLK) FM(HSCK4_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
218 #define IP0_7_4 FM(QSPI0_MOSI_IO0) FM(HCTS4_N_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
219 #define IP0_11_8 FM(QSPI0_MISO_IO1) FM(HRTS4_N_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
220 #define IP0_15_12 FM(QSPI0_IO2) FM(HTX4_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
221 #define IP0_19_16 FM(QSPI0_IO3) FM(HRX4_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
222 #define IP0_23_20 FM(QSPI1_SPCLK) FM(RIF2_CLK_A) FM(HSCK4_B) FM(VI4_DATA0_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
223 #define IP0_27_24 FM(QSPI1_MOSI_IO0) FM(RIF2_SYNC_A) FM(HTX4_B) FM(VI4_DATA1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
224 #define IP0_31_28 FM(QSPI1_MISO_IO1) FM(RIF2_D0_A) FM(HRX4_B) FM(VI4_DATA2_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
225 #define IP1_3_0 FM(QSPI1_IO2) FM(RIF2_D1_A) FM(HTX3_C) FM(VI4_DATA3_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
226 #define IP1_7_4 FM(QSPI1_IO3) FM(RIF3_CLK_A) FM(HRX3_C) FM(VI4_DATA4_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
227 #define IP1_11_8 FM(QSPI1_SSL) FM(RIF3_SYNC_A) FM(HSCK3_C) FM(VI4_DATA5_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
228 #define IP1_15_12 FM(RPC_INT_N) FM(RIF3_D0_A) FM(HCTS3_N_C) FM(VI4_DATA6_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
229 #define IP1_19_16 FM(RPC_RESET_N) FM(RIF3_D1_A) FM(HRTS3_N_C) FM(VI4_DATA7_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
230 #define IP1_23_20 FM(AVB_RD0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
231 #define IP1_27_24 FM(AVB_RD1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
232 #define IP1_31_28 FM(AVB_RD2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
233 #define IP2_3_0 FM(AVB_TXCREFCLK) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
234 #define IP2_7_4 FM(AVB_MDIO) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
235 #define IP2_11_8 FM(AVB_MDC) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
236 #define IP2_15_12 FM(BS_N) FM(PWM0_A) FM(AVB_MAGIC) FM(VI4_CLK) F_(0, 0) FM(TX3_C) F_(0, 0) FM(VI5_CLK_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
237 #define IP2_19_16 FM(RD_N) FM(PWM1_A) FM(AVB_LINK) FM(VI4_FIELD) F_(0, 0) FM(RX3_C) FM(FSCLKST2_N_A) FM(VI5_DATA0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
238 #define IP2_23_20 FM(RD_WR_N) FM(SCL7_A) FM(AVB_AVTP_MATCH) FM(VI4_VSYNC_N) FM(TX5_B) FM(SCK3_C) FM(PWM5_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
239 #define IP2_27_24 FM(EX_WAIT0) FM(SDA7_A) FM(AVB_AVTP_CAPTURE) FM(VI4_HSYNC_N) FM(RX5_B) FM(PWM6_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
240 #define IP2_31_28 FM(A0) FM(IRQ0) FM(PWM2_A) FM(MSIOF3_SS1_B) FM(VI5_CLK_A) FM(DU_CDE) FM(HRX3_D) FM(IERX) FM(QSTB_QHE) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
241 #define IP3_3_0 FM(A1) FM(IRQ1) FM(PWM3_A) FM(DU_DOTCLKIN1) FM(VI5_DATA0_A) FM(DU_DISP_CDE) FM(SDA6_B) FM(IETX) FM(QCPV_QDE) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
242 #define IP3_7_4 FM(A2) FM(IRQ2) FM(AVB_AVTP_PPS) FM(VI4_CLKENB) FM(VI5_DATA1_A) FM(DU_DISP) FM(SCL6_B) F_(0, 0) FM(QSTVB_QVE) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
243 #define IP3_11_8 FM(A3) FM(CTS4_N_A) FM(PWM4_A) FM(VI4_DATA12) F_(0, 0) FM(DU_DOTCLKOUT0) FM(HTX3_D) FM(IECLK) FM(LCDOUT12) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
244 #define IP3_15_12 FM(A4) FM(RTS4_N_A) FM(MSIOF3_SYNC_B) FM(VI4_DATA8) FM(PWM2_B) FM(DU_DG4) FM(RIF2_CLK_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
245 #define IP3_19_16 FM(A5) FM(SCK4_A) FM(MSIOF3_SCK_B) FM(VI4_DATA9) FM(PWM3_B) F_(0, 0) FM(RIF2_SYNC_B) F_(0, 0) FM(QPOLA) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
246 #define IP3_23_20 FM(A6) FM(RX4_A) FM(MSIOF3_RXD_B) FM(VI4_DATA10) F_(0, 0) F_(0, 0) FM(RIF2_D0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
247 #define IP3_27_24 FM(A7) FM(TX4_A) FM(MSIOF3_TXD_B) FM(VI4_DATA11) F_(0, 0) F_(0, 0) FM(RIF2_D1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
248 #define IP3_31_28 FM(A8) FM(SDA6_A) FM(RX3_B) FM(HRX4_C) FM(VI5_HSYNC_N_A) FM(DU_HSYNC) FM(VI4_DATA0_B) F_(0, 0) FM(QSTH_QHS) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
249
250 /* IPSRx */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */ /* 8 */ /* 9 - F */
251 #define IP4_3_0 FM(A9) FM(TX5_A) FM(IRQ3) FM(VI4_DATA16) FM(VI5_VSYNC_N_A) FM(DU_DG7) F_(0, 0) F_(0, 0) FM(LCDOUT15) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
252 #define IP4_7_4 FM(A10) FM(IRQ4) FM(MSIOF2_SYNC_B) FM(VI4_DATA13) FM(VI5_FIELD_A) FM(DU_DG5) FM(FSCLKST2_N_B) F_(0, 0) FM(LCDOUT13) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
253 #define IP4_11_8 FM(A11) FM(SCL6_A) FM(TX3_B) FM(HTX4_C) F_(0, 0) FM(DU_VSYNC) FM(VI4_DATA1_B) F_(0, 0) FM(QSTVA_QVS) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
254 #define IP4_15_12 FM(A12) FM(RX5_A) FM(MSIOF2_SS2_B) FM(VI4_DATA17) FM(VI5_DATA3_A) FM(DU_DG6) F_(0, 0) F_(0, 0) FM(LCDOUT14) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
255 #define IP4_19_16 FM(A13) FM(SCK5_A) FM(MSIOF2_SCK_B) FM(VI4_DATA14) FM(HRX4_D) FM(DU_DB2) F_(0, 0) F_(0, 0) FM(LCDOUT2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
256 #define IP4_23_20 FM(A14) FM(MSIOF1_SS1) FM(MSIOF2_RXD_B) FM(VI4_DATA15) FM(HTX4_D) FM(DU_DB3) F_(0, 0) F_(0, 0) FM(LCDOUT3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
257 #define IP4_27_24 FM(A15) FM(MSIOF1_SS2) FM(MSIOF2_TXD_B) FM(VI4_DATA18) FM(VI5_DATA4_A) FM(DU_DB4) F_(0, 0) F_(0, 0) FM(LCDOUT4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
258 #define IP4_31_28 FM(A16) FM(MSIOF1_SYNC) FM(MSIOF2_SS1_B) FM(VI4_DATA19) FM(VI5_DATA5_A) FM(DU_DB5) F_(0, 0) F_(0, 0) FM(LCDOUT5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
259 #define IP5_3_0 FM(A17) FM(MSIOF1_RXD) F_(0, 0) FM(VI4_DATA20) FM(VI5_DATA6_A) FM(DU_DB6) F_(0, 0) F_(0, 0) FM(LCDOUT6) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
260 #define IP5_7_4 FM(A18) FM(MSIOF1_TXD) F_(0, 0) FM(VI4_DATA21) FM(VI5_DATA7_A) FM(DU_DB0) F_(0, 0) FM(HRX4_E) FM(LCDOUT0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
261 #define IP5_11_8 FM(A19) FM(MSIOF1_SCK) F_(0, 0) FM(VI4_DATA22) FM(VI5_DATA2_A) FM(DU_DB1) F_(0, 0) FM(HTX4_E) FM(LCDOUT1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
262 #define IP5_15_12 FM(CS0_N) FM(SCL5) F_(0, 0) F_(0, 0) F_(0, 0) FM(DU_DR0) FM(VI4_DATA2_B) F_(0, 0) FM(LCDOUT16) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
263 #define IP5_19_16 FM(WE0_N) FM(SDA5) F_(0, 0) F_(0, 0) F_(0, 0) FM(DU_DR1) FM(VI4_DATA3_B) F_(0, 0) FM(LCDOUT17) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
264 #define IP5_23_20 FM(D0) FM(MSIOF3_SCK_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(DU_DR2) FM(CTS4_N_C) F_(0, 0) FM(LCDOUT18) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
265 #define IP5_27_24 FM(D1) FM(MSIOF3_SYNC_A) FM(SCK3_A) FM(VI4_DATA23) FM(VI5_CLKENB_A) FM(DU_DB7) FM(RTS4_N_C) F_(0, 0) FM(LCDOUT7) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
266 #define IP5_31_28 FM(D2) FM(MSIOF3_RXD_A) FM(RX5_C) F_(0, 0) FM(VI5_DATA14_A) FM(DU_DR3) FM(RX4_C) F_(0, 0) FM(LCDOUT19) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
267 #define IP6_3_0 FM(D3) FM(MSIOF3_TXD_A) FM(TX5_C) F_(0, 0) FM(VI5_DATA15_A) FM(DU_DR4) FM(TX4_C) F_(0, 0) FM(LCDOUT20) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
268 #define IP6_7_4 FM(D4) FM(CANFD1_TX) FM(HSCK3_B) FM(CAN1_TX) FM(RTS3_N_A) FM(MSIOF3_SS2_A) F_(0, 0) FM(VI5_DATA1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
269 #define IP6_11_8 FM(D5) FM(RX3_A) FM(HRX3_B) F_(0, 0) F_(0, 0) FM(DU_DR5) FM(VI4_DATA4_B) F_(0, 0) FM(LCDOUT21) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
270 #define IP6_15_12 FM(D6) FM(TX3_A) FM(HTX3_B) F_(0, 0) F_(0, 0) FM(DU_DR6) FM(VI4_DATA5_B) F_(0, 0) FM(LCDOUT22) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
271 #define IP6_19_16 FM(D7) FM(CANFD1_RX) FM(IRQ5) FM(CAN1_RX) FM(CTS3_N_A) F_(0, 0) F_(0, 0) FM(VI5_DATA2_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
272 #define IP6_23_20 FM(D8) FM(MSIOF2_SCK_A) FM(SCK4_B) F_(0, 0) FM(VI5_DATA12_A) FM(DU_DR7) FM(RIF3_CLK_B) FM(HCTS3_N_E) FM(LCDOUT23) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
273 #define IP6_27_24 FM(D9) FM(MSIOF2_SYNC_A) F_(0, 0) F_(0, 0) FM(VI5_DATA10_A) FM(DU_DG0) FM(RIF3_SYNC_B) FM(HRX3_E) FM(LCDOUT8) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
274 #define IP6_31_28 FM(D10) FM(MSIOF2_RXD_A) F_(0, 0) F_(0, 0) FM(VI5_DATA13_A) FM(DU_DG1) FM(RIF3_D0_B) FM(HTX3_E) FM(LCDOUT9) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
275 #define IP7_3_0 FM(D11) FM(MSIOF2_TXD_A) F_(0, 0) F_(0, 0) FM(VI5_DATA11_A) FM(DU_DG2) FM(RIF3_D1_B) FM(HRTS3_N_E) FM(LCDOUT10) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
276 #define IP7_7_4 FM(D12) FM(CANFD0_TX) FM(TX4_B) FM(CAN0_TX) FM(VI5_DATA8_A) F_(0, 0) F_(0, 0) FM(VI5_DATA3_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
277 #define IP7_11_8 FM(D13) FM(CANFD0_RX) FM(RX4_B) FM(CAN0_RX) FM(VI5_DATA9_A) FM(SCL7_B) F_(0, 0) FM(VI5_DATA4_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
278 #define IP7_15_12 FM(D14) FM(CAN_CLK) FM(HRX3_A) FM(MSIOF2_SS2_A) F_(0, 0) FM(SDA7_B) F_(0, 0) FM(VI5_DATA5_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
279 #define IP7_19_16 FM(D15) FM(MSIOF2_SS1_A) FM(HTX3_A) FM(MSIOF3_SS1_A) F_(0, 0) FM(DU_DG3) F_(0, 0) F_(0, 0) FM(LCDOUT11) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
280 #define IP7_23_20 FM(SCL4) FM(CS1_N_A26) F_(0, 0) F_(0, 0) F_(0, 0) FM(DU_DOTCLKIN0) FM(VI4_DATA6_B) FM(VI5_DATA6_B) FM(QCLK) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
281 #define IP7_27_24 FM(SDA4) FM(WE1_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(VI4_DATA7_B) FM(VI5_DATA7_B) FM(QPOLB) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
282 #define IP7_31_28 FM(SD0_CLK) FM(NFDATA8) FM(SCL1_C) FM(HSCK1_B) FM(SDA2_E) FM(FMCLK_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
283
284 /* IPSRx */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */ /* 8 */ /* 9 - F */
285 #define IP8_3_0 FM(SD0_CMD) FM(NFDATA9) F_(0, 0) FM(HRX1_B) F_(0, 0) FM(SPEEDIN_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
286 #define IP8_7_4 FM(SD0_DAT0) FM(NFDATA10) F_(0, 0) FM(HTX1_B) F_(0, 0) FM(REMOCON_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
287 #define IP8_11_8 FM(SD0_DAT1) FM(NFDATA11) FM(SDA2_C) FM(HCTS1_N_B) F_(0, 0) FM(FMIN_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
288 #define IP8_15_12 FM(SD0_DAT2) FM(NFDATA12) FM(SCL2_C) FM(HRTS1_N_B) F_(0, 0) FM(BPFCLK_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
289 #define IP8_19_16 FM(SD0_DAT3) FM(NFDATA13) FM(SDA1_C) FM(SCL2_E) FM(SPEEDIN_C) FM(REMOCON_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
290 #define IP8_23_20 FM(SD1_CLK) FM(NFDATA14_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
291 #define IP8_27_24 FM(SD1_CMD) FM(NFDATA15_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
292 #define IP8_31_28 FM(SD1_DAT0) FM(NFWP_N_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
293 #define IP9_3_0 FM(SD1_DAT1) FM(NFCE_N_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
294 #define IP9_7_4 FM(SD1_DAT2) FM(NFALE_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
295 #define IP9_11_8 FM(SD1_DAT3) FM(NFRB_N_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
296 #define IP9_15_12 FM(SD3_CLK) FM(NFWE_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
297 #define IP9_19_16 FM(SD3_CMD) FM(NFRE_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
298 #define IP9_23_20 FM(SD3_DAT0) FM(NFDATA0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
299 #define IP9_27_24 FM(SD3_DAT1) FM(NFDATA1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
300 #define IP9_31_28 FM(SD3_DAT2) FM(NFDATA2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
301 #define IP10_3_0 FM(SD3_DAT3) FM(NFDATA3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
302 #define IP10_7_4 FM(SD3_DAT4) FM(NFDATA4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
303 #define IP10_11_8 FM(SD3_DAT5) FM(NFDATA5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
304 #define IP10_15_12 FM(SD3_DAT6) FM(NFDATA6) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
305 #define IP10_19_16 FM(SD3_DAT7) FM(NFDATA7) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
306 #define IP10_23_20 FM(SD3_DS) FM(NFCLE) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
307 #define IP10_27_24 FM(SD0_CD) FM(NFALE_A) FM(SD3_CD) FM(RIF0_CLK_B) FM(SCL2_B) FM(TCLK1_A) FM(SSI_SCK2_B) FM(TS_SCK0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
308 #define IP10_31_28 FM(SD0_WP) FM(NFRB_N_A) FM(SD3_WP) FM(RIF0_D0_B) FM(SDA2_B) FM(TCLK2_A) FM(SSI_WS2_B) FM(TS_SDAT0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
309 #define IP11_3_0 FM(SD1_CD) FM(NFCE_N_A) FM(SSI_SCK1) FM(RIF0_D1_B) F_(0, 0) F_(0, 0) F_(0, 0) FM(TS_SDEN0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
310 #define IP11_7_4 FM(SD1_WP) FM(NFWP_N_A) FM(SSI_WS1) FM(RIF0_SYNC_B) F_(0, 0) F_(0, 0) F_(0, 0) FM(TS_SPSYNC0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
311 #define IP11_11_8 FM(RX0_A) FM(HRX1_A) FM(SSI_SCK2_A) FM(RIF1_SYNC) F_(0, 0) F_(0, 0) F_(0, 0) FM(TS_SCK1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
312 #define IP11_15_12 FM(TX0_A) FM(HTX1_A) FM(SSI_WS2_A) FM(RIF1_D0) F_(0, 0) F_(0, 0) F_(0, 0) FM(TS_SDAT1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
313 #define IP11_19_16 FM(CTS0_N_A) FM(NFDATA14_A) FM(AUDIO_CLKOUT_A) FM(RIF1_D1) FM(SCIF_CLK_A) FM(FMCLK_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
314 #define IP11_23_20 FM(RTS0_N_A) FM(NFDATA15_A) FM(AUDIO_CLKOUT1_A) FM(RIF1_CLK) FM(SCL2_A) FM(FMIN_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
315 #define IP11_27_24 FM(SCK0_A) FM(HSCK1_A) FM(USB3HS0_ID) FM(RTS1_N) FM(SDA2_A) FM(FMCLK_C) F_(0, 0) F_(0, 0) FM(USB0_ID) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
316 #define IP11_31_28 FM(RX1) FM(HRX2_B) FM(SSI_SCK9_B) FM(AUDIO_CLKOUT1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
317
318 /* IPSRx */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */ /* 8 */ /* 9 - F */
319 #define IP12_3_0 FM(TX1) FM(HTX2_B) FM(SSI_WS9_B) FM(AUDIO_CLKOUT3_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
320 #define IP12_7_4 FM(SCK2_A) FM(HSCK0_A) FM(AUDIO_CLKB_A) FM(CTS1_N) FM(RIF0_CLK_A) FM(REMOCON_A) FM(SCIF_CLK_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
321 #define IP12_11_8 FM(TX2_A) FM(HRX0_A) FM(AUDIO_CLKOUT2_A) F_(0, 0) FM(SCL1_A) F_(0, 0) FM(FSO_CFE_0_N_A) FM(TS_SDEN1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
322 #define IP12_15_12 FM(RX2_A) FM(HTX0_A) FM(AUDIO_CLKOUT3_A) F_(0, 0) FM(SDA1_A) F_(0, 0) FM(FSO_CFE_1_N_A) FM(TS_SPSYNC1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
323 #define IP12_19_16 FM(MSIOF0_SCK) F_(0, 0) FM(SSI_SCK78) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
324 #define IP12_23_20 FM(MSIOF0_RXD) F_(0, 0) FM(SSI_WS78) F_(0, 0) F_(0, 0) FM(TX2_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
325 #define IP12_27_24 FM(MSIOF0_TXD) F_(0, 0) FM(SSI_SDATA7) F_(0, 0) F_(0, 0) FM(RX2_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
326 #define IP12_31_28 FM(MSIOF0_SYNC) FM(AUDIO_CLKOUT_B) FM(SSI_SDATA8) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
327 #define IP13_3_0 FM(MSIOF0_SS1) FM(HRX2_A) FM(SSI_SCK4) FM(HCTS0_N_A) FM(BPFCLK_C) FM(SPEEDIN_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
328 #define IP13_7_4 FM(MSIOF0_SS2) FM(HTX2_A) FM(SSI_WS4) FM(HRTS0_N_A) FM(FMIN_C) FM(BPFCLK_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
329 #define IP13_11_8 FM(SSI_SDATA9) F_(0, 0) FM(AUDIO_CLKC_A) FM(SCK1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
330 #define IP13_15_12 FM(MLB_CLK) FM(RX0_B) F_(0, 0) FM(RIF0_D0_A) FM(SCL1_B) FM(TCLK1_B) F_(0, 0) F_(0, 0) FM(SIM0_RST_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
331 #define IP13_19_16 FM(MLB_SIG) FM(SCK0_B) F_(0, 0) FM(RIF0_D1_A) FM(SDA1_B) FM(TCLK2_B) F_(0, 0) F_(0, 0) FM(SIM0_D_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
332 #define IP13_23_20 FM(MLB_DAT) FM(TX0_B) F_(0, 0) FM(RIF0_SYNC_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(SIM0_CLK_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
333 #define IP13_27_24 FM(SSI_SCK01239) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
334 #define IP13_31_28 FM(SSI_WS01239) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
335 #define IP14_3_0 FM(SSI_SDATA0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
336 #define IP14_7_4 FM(SSI_SDATA1) FM(AUDIO_CLKC_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(PWM0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
337 #define IP14_11_8 FM(SSI_SDATA2) FM(AUDIO_CLKOUT2_B) FM(SSI_SCK9_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(PWM1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
338 #define IP14_15_12 FM(SSI_SCK349) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(PWM2_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
339 #define IP14_19_16 FM(SSI_WS349) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(PWM3_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
340 #define IP14_23_20 FM(SSI_SDATA3) FM(AUDIO_CLKOUT1_C) FM(AUDIO_CLKB_B) F_(0, 0) F_(0, 0) F_(0, 0) FM(PWM4_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
341 #define IP14_27_24 FM(SSI_SDATA4) F_(0, 0) FM(SSI_WS9_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(PWM5_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
342 #define IP14_31_28 FM(SSI_SCK5) FM(HRX0_B) F_(0, 0) FM(USB0_PWEN_B) FM(SCL2_D) F_(0, 0) FM(PWM6_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
343 #define IP15_3_0 FM(SSI_WS5) FM(HTX0_B) F_(0, 0) FM(USB0_OVC_B) FM(SDA2_D) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
344 #define IP15_7_4 FM(SSI_SDATA5) FM(HSCK0_B) FM(AUDIO_CLKB_C) FM(TPU0TO0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
345 #define IP15_11_8 FM(SSI_SCK6) FM(HSCK2_A) FM(AUDIO_CLKC_C) FM(TPU0TO1) F_(0, 0) F_(0, 0) FM(FSO_CFE_0_N_B) F_(0, 0) FM(SIM0_RST_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
346 #define IP15_15_12 FM(SSI_WS6) FM(HCTS2_N_A) FM(AUDIO_CLKOUT2_C) FM(TPU0TO2) FM(SDA1_D) F_(0, 0) FM(FSO_CFE_1_N_B) F_(0, 0) FM(SIM0_D_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
347 #define IP15_19_16 FM(SSI_SDATA6) FM(HRTS2_N_A) FM(AUDIO_CLKOUT3_C) FM(TPU0TO3) FM(SCL1_D) F_(0, 0) FM(FSO_TOE_N_B) F_(0, 0) FM(SIM0_CLK_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
348 #define IP15_23_20 FM(AUDIO_CLKA) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
349 #define IP15_27_24 FM(USB30_PWEN) FM(USB0_PWEN_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
350 #define IP15_31_28 FM(USB30_OVC) FM(USB0_OVC_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(FSO_TOE_N_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
351
352 #define PINMUX_GPSR \
353 \
354 \
355 \
356 \
357 \
358 \
359 \
360 GPSR2_25 \
361 GPSR2_24 \
362 GPSR2_23 \
363 GPSR1_22 GPSR2_22 \
364 GPSR1_21 GPSR2_21 \
365 GPSR1_20 GPSR2_20 \
366 GPSR1_19 GPSR2_19 GPSR5_19 \
367 GPSR1_18 GPSR2_18 GPSR5_18 \
368 GPSR0_17 GPSR1_17 GPSR2_17 GPSR5_17 GPSR6_17 \
369 GPSR0_16 GPSR1_16 GPSR2_16 GPSR5_16 GPSR6_16 \
370 GPSR0_15 GPSR1_15 GPSR2_15 GPSR3_15 GPSR5_15 GPSR6_15 \
371 GPSR0_14 GPSR1_14 GPSR2_14 GPSR3_14 GPSR5_14 GPSR6_14 \
372 GPSR0_13 GPSR1_13 GPSR2_13 GPSR3_13 GPSR5_13 GPSR6_13 \
373 GPSR0_12 GPSR1_12 GPSR2_12 GPSR3_12 GPSR5_12 GPSR6_12 \
374 GPSR0_11 GPSR1_11 GPSR2_11 GPSR3_11 GPSR5_11 GPSR6_11 \
375 GPSR0_10 GPSR1_10 GPSR2_10 GPSR3_10 GPSR4_10 GPSR5_10 GPSR6_10 \
376 GPSR0_9 GPSR1_9 GPSR2_9 GPSR3_9 GPSR4_9 GPSR5_9 GPSR6_9 \
377 GPSR0_8 GPSR1_8 GPSR2_8 GPSR3_8 GPSR4_8 GPSR5_8 GPSR6_8 \
378 GPSR0_7 GPSR1_7 GPSR2_7 GPSR3_7 GPSR4_7 GPSR5_7 GPSR6_7 \
379 GPSR0_6 GPSR1_6 GPSR2_6 GPSR3_6 GPSR4_6 GPSR5_6 GPSR6_6 \
380 GPSR0_5 GPSR1_5 GPSR2_5 GPSR3_5 GPSR4_5 GPSR5_5 GPSR6_5 \
381 GPSR0_4 GPSR1_4 GPSR2_4 GPSR3_4 GPSR4_4 GPSR5_4 GPSR6_4 \
382 GPSR0_3 GPSR1_3 GPSR2_3 GPSR3_3 GPSR4_3 GPSR5_3 GPSR6_3 \
383 GPSR0_2 GPSR1_2 GPSR2_2 GPSR3_2 GPSR4_2 GPSR5_2 GPSR6_2 \
384 GPSR0_1 GPSR1_1 GPSR2_1 GPSR3_1 GPSR4_1 GPSR5_1 GPSR6_1 \
385 GPSR0_0 GPSR1_0 GPSR2_0 GPSR3_0 GPSR4_0 GPSR5_0 GPSR6_0
386
387 #define PINMUX_IPSR \
388 \
389 FM(IP0_3_0) IP0_3_0 FM(IP1_3_0) IP1_3_0 FM(IP2_3_0) IP2_3_0 FM(IP3_3_0) IP3_3_0 \
390 FM(IP0_7_4) IP0_7_4 FM(IP1_7_4) IP1_7_4 FM(IP2_7_4) IP2_7_4 FM(IP3_7_4) IP3_7_4 \
391 FM(IP0_11_8) IP0_11_8 FM(IP1_11_8) IP1_11_8 FM(IP2_11_8) IP2_11_8 FM(IP3_11_8) IP3_11_8 \
392 FM(IP0_15_12) IP0_15_12 FM(IP1_15_12) IP1_15_12 FM(IP2_15_12) IP2_15_12 FM(IP3_15_12) IP3_15_12 \
393 FM(IP0_19_16) IP0_19_16 FM(IP1_19_16) IP1_19_16 FM(IP2_19_16) IP2_19_16 FM(IP3_19_16) IP3_19_16 \
394 FM(IP0_23_20) IP0_23_20 FM(IP1_23_20) IP1_23_20 FM(IP2_23_20) IP2_23_20 FM(IP3_23_20) IP3_23_20 \
395 FM(IP0_27_24) IP0_27_24 FM(IP1_27_24) IP1_27_24 FM(IP2_27_24) IP2_27_24 FM(IP3_27_24) IP3_27_24 \
396 FM(IP0_31_28) IP0_31_28 FM(IP1_31_28) IP1_31_28 FM(IP2_31_28) IP2_31_28 FM(IP3_31_28) IP3_31_28 \
397 \
398 FM(IP4_3_0) IP4_3_0 FM(IP5_3_0) IP5_3_0 FM(IP6_3_0) IP6_3_0 FM(IP7_3_0) IP7_3_0 \
399 FM(IP4_7_4) IP4_7_4 FM(IP5_7_4) IP5_7_4 FM(IP6_7_4) IP6_7_4 FM(IP7_7_4) IP7_7_4 \
400 FM(IP4_11_8) IP4_11_8 FM(IP5_11_8) IP5_11_8 FM(IP6_11_8) IP6_11_8 FM(IP7_11_8) IP7_11_8 \
401 FM(IP4_15_12) IP4_15_12 FM(IP5_15_12) IP5_15_12 FM(IP6_15_12) IP6_15_12 FM(IP7_15_12) IP7_15_12 \
402 FM(IP4_19_16) IP4_19_16 FM(IP5_19_16) IP5_19_16 FM(IP6_19_16) IP6_19_16 FM(IP7_19_16) IP7_19_16 \
403 FM(IP4_23_20) IP4_23_20 FM(IP5_23_20) IP5_23_20 FM(IP6_23_20) IP6_23_20 FM(IP7_23_20) IP7_23_20 \
404 FM(IP4_27_24) IP4_27_24 FM(IP5_27_24) IP5_27_24 FM(IP6_27_24) IP6_27_24 FM(IP7_27_24) IP7_27_24 \
405 FM(IP4_31_28) IP4_31_28 FM(IP5_31_28) IP5_31_28 FM(IP6_31_28) IP6_31_28 FM(IP7_31_28) IP7_31_28 \
406 \
407 FM(IP8_3_0) IP8_3_0 FM(IP9_3_0) IP9_3_0 FM(IP10_3_0) IP10_3_0 FM(IP11_3_0) IP11_3_0 \
408 FM(IP8_7_4) IP8_7_4 FM(IP9_7_4) IP9_7_4 FM(IP10_7_4) IP10_7_4 FM(IP11_7_4) IP11_7_4 \
409 FM(IP8_11_8) IP8_11_8 FM(IP9_11_8) IP9_11_8 FM(IP10_11_8) IP10_11_8 FM(IP11_11_8) IP11_11_8 \
410 FM(IP8_15_12) IP8_15_12 FM(IP9_15_12) IP9_15_12 FM(IP10_15_12) IP10_15_12 FM(IP11_15_12) IP11_15_12 \
411 FM(IP8_19_16) IP8_19_16 FM(IP9_19_16) IP9_19_16 FM(IP10_19_16) IP10_19_16 FM(IP11_19_16) IP11_19_16 \
412 FM(IP8_23_20) IP8_23_20 FM(IP9_23_20) IP9_23_20 FM(IP10_23_20) IP10_23_20 FM(IP11_23_20) IP11_23_20 \
413 FM(IP8_27_24) IP8_27_24 FM(IP9_27_24) IP9_27_24 FM(IP10_27_24) IP10_27_24 FM(IP11_27_24) IP11_27_24 \
414 FM(IP8_31_28) IP8_31_28 FM(IP9_31_28) IP9_31_28 FM(IP10_31_28) IP10_31_28 FM(IP11_31_28) IP11_31_28 \
415 \
416 FM(IP12_3_0) IP12_3_0 FM(IP13_3_0) IP13_3_0 FM(IP14_3_0) IP14_3_0 FM(IP15_3_0) IP15_3_0 \
417 FM(IP12_7_4) IP12_7_4 FM(IP13_7_4) IP13_7_4 FM(IP14_7_4) IP14_7_4 FM(IP15_7_4) IP15_7_4 \
418 FM(IP12_11_8) IP12_11_8 FM(IP13_11_8) IP13_11_8 FM(IP14_11_8) IP14_11_8 FM(IP15_11_8) IP15_11_8 \
419 FM(IP12_15_12) IP12_15_12 FM(IP13_15_12) IP13_15_12 FM(IP14_15_12) IP14_15_12 FM(IP15_15_12) IP15_15_12 \
420 FM(IP12_19_16) IP12_19_16 FM(IP13_19_16) IP13_19_16 FM(IP14_19_16) IP14_19_16 FM(IP15_19_16) IP15_19_16 \
421 FM(IP12_23_20) IP12_23_20 FM(IP13_23_20) IP13_23_20 FM(IP14_23_20) IP14_23_20 FM(IP15_23_20) IP15_23_20 \
422 FM(IP12_27_24) IP12_27_24 FM(IP13_27_24) IP13_27_24 FM(IP14_27_24) IP14_27_24 FM(IP15_27_24) IP15_27_24 \
423 FM(IP12_31_28) IP12_31_28 FM(IP13_31_28) IP13_31_28 FM(IP14_31_28) IP14_31_28 FM(IP15_31_28) IP15_31_28
424
425 /* The bit numbering in MOD_SEL fields is reversed */
426 #define REV4(f0, f1, f2, f3) f0 f2 f1 f3
427 #define REV8(f0, f1, f2, f3, f4, f5, f6, f7) f0 f4 f2 f6 f1 f5 f3 f7
428
429 /* MOD_SEL0 */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */
430 #define MOD_SEL0_30_29 REV4(FM(SEL_ADGB_0), FM(SEL_ADGB_1), FM(SEL_ADGB_2), F_(0, 0))
431 #define MOD_SEL0_28 FM(SEL_DRIF0_0) FM(SEL_DRIF0_1)
432 #define MOD_SEL0_27_26 REV4(FM(SEL_FM_0), FM(SEL_FM_1), FM(SEL_FM_2), F_(0, 0))
433 #define MOD_SEL0_25 FM(SEL_FSO_0) FM(SEL_FSO_1)
434 #define MOD_SEL0_24 FM(SEL_HSCIF0_0) FM(SEL_HSCIF0_1)
435 #define MOD_SEL0_23 FM(SEL_HSCIF1_0) FM(SEL_HSCIF1_1)
436 #define MOD_SEL0_22 FM(SEL_HSCIF2_0) FM(SEL_HSCIF2_1)
437 #define MOD_SEL0_21_20 REV4(FM(SEL_I2C1_0), FM(SEL_I2C1_1), FM(SEL_I2C1_2), FM(SEL_I2C1_3))
438 #define MOD_SEL0_19_18_17 REV8(FM(SEL_I2C2_0), FM(SEL_I2C2_1), FM(SEL_I2C2_2), FM(SEL_I2C2_3), FM(SEL_I2C2_4), F_(0, 0), F_(0, 0), F_(0, 0))
439 #define MOD_SEL0_16 FM(SEL_NDF_0) FM(SEL_NDF_1)
440 #define MOD_SEL0_15 FM(SEL_PWM0_0) FM(SEL_PWM0_1)
441 #define MOD_SEL0_14 FM(SEL_PWM1_0) FM(SEL_PWM1_1)
442 #define MOD_SEL0_13_12 REV4(FM(SEL_PWM2_0), FM(SEL_PWM2_1), FM(SEL_PWM2_2), F_(0, 0))
443 #define MOD_SEL0_11_10 REV4(FM(SEL_PWM3_0), FM(SEL_PWM3_1), FM(SEL_PWM3_2), F_(0, 0))
444 #define MOD_SEL0_9 FM(SEL_PWM4_0) FM(SEL_PWM4_1)
445 #define MOD_SEL0_8 FM(SEL_PWM5_0) FM(SEL_PWM5_1)
446 #define MOD_SEL0_7 FM(SEL_PWM6_0) FM(SEL_PWM6_1)
447 #define MOD_SEL0_6_5 REV4(FM(SEL_REMOCON_0), FM(SEL_REMOCON_1), FM(SEL_REMOCON_2), F_(0, 0))
448 #define MOD_SEL0_4 FM(SEL_SCIF_0) FM(SEL_SCIF_1)
449 #define MOD_SEL0_3 FM(SEL_SCIF0_0) FM(SEL_SCIF0_1)
450 #define MOD_SEL0_2 FM(SEL_SCIF2_0) FM(SEL_SCIF2_1)
451 #define MOD_SEL0_1_0 REV4(FM(SEL_SPEED_PULSE_IF_0), FM(SEL_SPEED_PULSE_IF_1), FM(SEL_SPEED_PULSE_IF_2), F_(0, 0))
452
453 /* MOD_SEL1 */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */
454 #define MOD_SEL1_31 FM(SEL_SIMCARD_0) FM(SEL_SIMCARD_1)
455 #define MOD_SEL1_30 FM(SEL_SSI2_0) FM(SEL_SSI2_1)
456 #define MOD_SEL1_29 FM(SEL_TIMER_TMU_0) FM(SEL_TIMER_TMU_1)
457 #define MOD_SEL1_28 FM(SEL_USB_20_CH0_0) FM(SEL_USB_20_CH0_1)
458 #define MOD_SEL1_26 FM(SEL_DRIF2_0) FM(SEL_DRIF2_1)
459 #define MOD_SEL1_25 FM(SEL_DRIF3_0) FM(SEL_DRIF3_1)
460 #define MOD_SEL1_24_23_22 REV8(FM(SEL_HSCIF3_0), FM(SEL_HSCIF3_1), FM(SEL_HSCIF3_2), FM(SEL_HSCIF3_3), FM(SEL_HSCIF3_4), F_(0, 0), F_(0, 0), F_(0, 0))
461 #define MOD_SEL1_21_20_19 REV8(FM(SEL_HSCIF4_0), FM(SEL_HSCIF4_1), FM(SEL_HSCIF4_2), FM(SEL_HSCIF4_3), FM(SEL_HSCIF4_4), F_(0, 0), F_(0, 0), F_(0, 0))
462 #define MOD_SEL1_18 FM(SEL_I2C6_0) FM(SEL_I2C6_1)
463 #define MOD_SEL1_17 FM(SEL_I2C7_0) FM(SEL_I2C7_1)
464 #define MOD_SEL1_16 FM(SEL_MSIOF2_0) FM(SEL_MSIOF2_1)
465 #define MOD_SEL1_15 FM(SEL_MSIOF3_0) FM(SEL_MSIOF3_1)
466 #define MOD_SEL1_14_13 REV4(FM(SEL_SCIF3_0), FM(SEL_SCIF3_1), FM(SEL_SCIF3_2), F_(0, 0))
467 #define MOD_SEL1_12_11 REV4(FM(SEL_SCIF4_0), FM(SEL_SCIF4_1), FM(SEL_SCIF4_2), F_(0, 0))
468 #define MOD_SEL1_10_9 REV4(FM(SEL_SCIF5_0), FM(SEL_SCIF5_1), FM(SEL_SCIF5_2), F_(0, 0))
469 #define MOD_SEL1_8 FM(SEL_VIN4_0) FM(SEL_VIN4_1)
470 #define MOD_SEL1_7 FM(SEL_VIN5_0) FM(SEL_VIN5_1)
471 #define MOD_SEL1_6_5 REV4(FM(SEL_ADGC_0), FM(SEL_ADGC_1), FM(SEL_ADGC_2), F_(0, 0))
472 #define MOD_SEL1_4 FM(SEL_SSI9_0) FM(SEL_SSI9_1)
473
474 #define PINMUX_MOD_SELS \
475 \
476 MOD_SEL1_31 \
477 MOD_SEL0_30_29 MOD_SEL1_30 \
478 MOD_SEL1_29 \
479 MOD_SEL0_28 MOD_SEL1_28 \
480 MOD_SEL0_27_26 \
481 MOD_SEL1_26 \
482 MOD_SEL0_25 MOD_SEL1_25 \
483 MOD_SEL0_24 MOD_SEL1_24_23_22 \
484 MOD_SEL0_23 \
485 MOD_SEL0_22 \
486 MOD_SEL0_21_20 MOD_SEL1_21_20_19 \
487 MOD_SEL0_19_18_17 MOD_SEL1_18 \
488 MOD_SEL1_17 \
489 MOD_SEL0_16 MOD_SEL1_16 \
490 MOD_SEL0_15 MOD_SEL1_15 \
491 MOD_SEL0_14 MOD_SEL1_14_13 \
492 MOD_SEL0_13_12 \
493 MOD_SEL1_12_11 \
494 MOD_SEL0_11_10 \
495 MOD_SEL1_10_9 \
496 MOD_SEL0_9 \
497 MOD_SEL0_8 MOD_SEL1_8 \
498 MOD_SEL0_7 MOD_SEL1_7 \
499 MOD_SEL0_6_5 MOD_SEL1_6_5 \
500 MOD_SEL0_4 MOD_SEL1_4 \
501 MOD_SEL0_3 \
502 MOD_SEL0_2 \
503 MOD_SEL0_1_0
504
505 /*
506 * These pins are not able to be muxed but have other properties
507 * that can be set, such as pull-up/pull-down enable.
508 */
509 #define PINMUX_STATIC \
510 FM(AVB_TX_CTL) FM(AVB_TXC) FM(AVB_TD0) FM(AVB_TD1) FM(AVB_TD2) \
511 FM(AVB_TD3) \
512 FM(PRESETOUT_N) FM(FSCLKST_N) FM(TRST_N) FM(TCK) FM(TMS) FM(TDI) \
513 FM(ASEBRK) \
514 FM(MLB_REF)
515
516 enum {
517 PINMUX_RESERVED = 0,
518
519 PINMUX_DATA_BEGIN,
520 GP_ALL(DATA),
521 PINMUX_DATA_END,
522
523 #define F_(x, y)
524 #define FM(x) FN_##x,
525 PINMUX_FUNCTION_BEGIN,
526 GP_ALL(FN),
527 PINMUX_GPSR
528 PINMUX_IPSR
529 PINMUX_MOD_SELS
530 PINMUX_FUNCTION_END,
531 #undef F_
532 #undef FM
533
534 #define F_(x, y)
535 #define FM(x) x##_MARK,
536 PINMUX_MARK_BEGIN,
537 PINMUX_GPSR
538 PINMUX_IPSR
539 PINMUX_MOD_SELS
540 PINMUX_STATIC
541 PINMUX_MARK_END,
542 #undef F_
543 #undef FM
544 };
545
546 static const u16 pinmux_data[] = {
547 PINMUX_DATA_GP_ALL(),
548
549 PINMUX_SINGLE(CLKOUT),
550 PINMUX_SINGLE(AVB_PHY_INT),
551 PINMUX_SINGLE(AVB_RD3),
552 PINMUX_SINGLE(AVB_RXC),
553 PINMUX_SINGLE(AVB_RX_CTL),
554 PINMUX_SINGLE(QSPI0_SSL),
555
556 /* IPSR0 */
557 PINMUX_IPSR_GPSR(IP0_3_0, QSPI0_SPCLK),
558 PINMUX_IPSR_MSEL(IP0_3_0, HSCK4_A, SEL_HSCIF4_0),
559
560 PINMUX_IPSR_GPSR(IP0_7_4, QSPI0_MOSI_IO0),
561 PINMUX_IPSR_MSEL(IP0_7_4, HCTS4_N_A, SEL_HSCIF4_0),
562
563 PINMUX_IPSR_GPSR(IP0_11_8, QSPI0_MISO_IO1),
564 PINMUX_IPSR_MSEL(IP0_11_8, HRTS4_N_A, SEL_HSCIF4_0),
565
566 PINMUX_IPSR_GPSR(IP0_15_12, QSPI0_IO2),
567 PINMUX_IPSR_GPSR(IP0_15_12, HTX4_A),
568
569 PINMUX_IPSR_GPSR(IP0_19_16, QSPI0_IO3),
570 PINMUX_IPSR_MSEL(IP0_19_16, HRX4_A, SEL_HSCIF4_0),
571
572 PINMUX_IPSR_GPSR(IP0_23_20, QSPI1_SPCLK),
573 PINMUX_IPSR_MSEL(IP0_23_20, RIF2_CLK_A, SEL_DRIF2_0),
574 PINMUX_IPSR_MSEL(IP0_23_20, HSCK4_B, SEL_HSCIF4_1),
575 PINMUX_IPSR_MSEL(IP0_23_20, VI4_DATA0_A, SEL_VIN4_0),
576
577 PINMUX_IPSR_GPSR(IP0_27_24, QSPI1_MOSI_IO0),
578 PINMUX_IPSR_MSEL(IP0_27_24, RIF2_SYNC_A, SEL_DRIF2_0),
579 PINMUX_IPSR_GPSR(IP0_27_24, HTX4_B),
580 PINMUX_IPSR_MSEL(IP0_27_24, VI4_DATA1_A, SEL_VIN4_0),
581
582 PINMUX_IPSR_GPSR(IP0_31_28, QSPI1_MISO_IO1),
583 PINMUX_IPSR_MSEL(IP0_31_28, RIF2_D0_A, SEL_DRIF2_0),
584 PINMUX_IPSR_MSEL(IP0_31_28, HRX4_B, SEL_HSCIF4_1),
585 PINMUX_IPSR_MSEL(IP0_31_28, VI4_DATA2_A, SEL_VIN4_0),
586
587 /* IPSR1 */
588 PINMUX_IPSR_GPSR(IP1_3_0, QSPI1_IO2),
589 PINMUX_IPSR_MSEL(IP1_3_0, RIF2_D1_A, SEL_DRIF2_0),
590 PINMUX_IPSR_GPSR(IP1_3_0, HTX3_C),
591 PINMUX_IPSR_MSEL(IP1_3_0, VI4_DATA3_A, SEL_VIN4_0),
592
593 PINMUX_IPSR_GPSR(IP1_7_4, QSPI1_IO3),
594 PINMUX_IPSR_MSEL(IP1_7_4, RIF3_CLK_A, SEL_DRIF3_0),
595 PINMUX_IPSR_MSEL(IP1_7_4, HRX3_C, SEL_HSCIF3_2),
596 PINMUX_IPSR_MSEL(IP1_7_4, VI4_DATA4_A, SEL_VIN4_0),
597
598 PINMUX_IPSR_GPSR(IP1_11_8, QSPI1_SSL),
599 PINMUX_IPSR_MSEL(IP1_11_8, RIF3_SYNC_A, SEL_DRIF3_0),
600 PINMUX_IPSR_MSEL(IP1_11_8, HSCK3_C, SEL_HSCIF3_2),
601 PINMUX_IPSR_MSEL(IP1_11_8, VI4_DATA5_A, SEL_VIN4_0),
602
603 PINMUX_IPSR_GPSR(IP1_15_12, RPC_INT_N),
604 PINMUX_IPSR_MSEL(IP1_15_12, RIF3_D0_A, SEL_DRIF3_0),
605 PINMUX_IPSR_MSEL(IP1_15_12, HCTS3_N_C, SEL_HSCIF3_2),
606 PINMUX_IPSR_MSEL(IP1_15_12, VI4_DATA6_A, SEL_VIN4_0),
607
608 PINMUX_IPSR_GPSR(IP1_19_16, RPC_RESET_N),
609 PINMUX_IPSR_MSEL(IP1_19_16, RIF3_D1_A, SEL_DRIF3_0),
610 PINMUX_IPSR_MSEL(IP1_19_16, HRTS3_N_C, SEL_HSCIF3_2),
611 PINMUX_IPSR_MSEL(IP1_19_16, VI4_DATA7_A, SEL_VIN4_0),
612
613 PINMUX_IPSR_GPSR(IP1_23_20, AVB_RD0),
614
615 PINMUX_IPSR_GPSR(IP1_27_24, AVB_RD1),
616
617 PINMUX_IPSR_GPSR(IP1_31_28, AVB_RD2),
618
619 /* IPSR2 */
620 PINMUX_IPSR_GPSR(IP2_3_0, AVB_TXCREFCLK),
621
622 PINMUX_IPSR_GPSR(IP2_7_4, AVB_MDIO),
623
624 PINMUX_IPSR_GPSR(IP2_11_8, AVB_MDC),
625
626 PINMUX_IPSR_GPSR(IP2_15_12, BS_N),
627 PINMUX_IPSR_MSEL(IP2_15_12, PWM0_A, SEL_PWM0_0),
628 PINMUX_IPSR_GPSR(IP2_15_12, AVB_MAGIC),
629 PINMUX_IPSR_GPSR(IP2_15_12, VI4_CLK),
630 PINMUX_IPSR_GPSR(IP2_15_12, TX3_C),
631 PINMUX_IPSR_MSEL(IP2_15_12, VI5_CLK_B, SEL_VIN5_1),
632
633 PINMUX_IPSR_GPSR(IP2_19_16, RD_N),
634 PINMUX_IPSR_MSEL(IP2_19_16, PWM1_A, SEL_PWM1_0),
635 PINMUX_IPSR_GPSR(IP2_19_16, AVB_LINK),
636 PINMUX_IPSR_GPSR(IP2_19_16, VI4_FIELD),
637 PINMUX_IPSR_MSEL(IP2_19_16, RX3_C, SEL_SCIF3_2),
638 PINMUX_IPSR_GPSR(IP2_19_16, FSCLKST2_N_A),
639 PINMUX_IPSR_MSEL(IP2_19_16, VI5_DATA0_B, SEL_VIN5_1),
640
641 PINMUX_IPSR_GPSR(IP2_23_20, RD_WR_N),
642 PINMUX_IPSR_MSEL(IP2_23_20, SCL7_A, SEL_I2C7_0),
643 PINMUX_IPSR_GPSR(IP2_23_20, AVB_AVTP_MATCH),
644 PINMUX_IPSR_GPSR(IP2_23_20, VI4_VSYNC_N),
645 PINMUX_IPSR_GPSR(IP2_23_20, TX5_B),
646 PINMUX_IPSR_MSEL(IP2_23_20, SCK3_C, SEL_SCIF3_2),
647 PINMUX_IPSR_MSEL(IP2_23_20, PWM5_A, SEL_PWM5_0),
648
649 PINMUX_IPSR_GPSR(IP2_27_24, EX_WAIT0),
650 PINMUX_IPSR_MSEL(IP2_27_24, SDA7_A, SEL_I2C7_0),
651 PINMUX_IPSR_GPSR(IP2_27_24, AVB_AVTP_CAPTURE),
652 PINMUX_IPSR_GPSR(IP2_27_24, VI4_HSYNC_N),
653 PINMUX_IPSR_MSEL(IP2_27_24, RX5_B, SEL_SCIF5_1),
654 PINMUX_IPSR_MSEL(IP2_27_24, PWM6_A, SEL_PWM6_0),
655
656 PINMUX_IPSR_GPSR(IP2_31_28, A0),
657 PINMUX_IPSR_GPSR(IP2_31_28, IRQ0),
658 PINMUX_IPSR_MSEL(IP2_31_28, PWM2_A, SEL_PWM2_0),
659 PINMUX_IPSR_MSEL(IP2_31_28, MSIOF3_SS1_B, SEL_MSIOF3_1),
660 PINMUX_IPSR_MSEL(IP2_31_28, VI5_CLK_A, SEL_VIN5_0),
661 PINMUX_IPSR_GPSR(IP2_31_28, DU_CDE),
662 PINMUX_IPSR_MSEL(IP2_31_28, HRX3_D, SEL_HSCIF3_3),
663 PINMUX_IPSR_GPSR(IP2_31_28, IERX),
664 PINMUX_IPSR_GPSR(IP2_31_28, QSTB_QHE),
665
666 /* IPSR3 */
667 PINMUX_IPSR_GPSR(IP3_3_0, A1),
668 PINMUX_IPSR_GPSR(IP3_3_0, IRQ1),
669 PINMUX_IPSR_MSEL(IP3_3_0, PWM3_A, SEL_PWM3_0),
670 PINMUX_IPSR_GPSR(IP3_3_0, DU_DOTCLKIN1),
671 PINMUX_IPSR_MSEL(IP3_3_0, VI5_DATA0_A, SEL_VIN5_0),
672 PINMUX_IPSR_GPSR(IP3_3_0, DU_DISP_CDE),
673 PINMUX_IPSR_MSEL(IP3_3_0, SDA6_B, SEL_I2C6_1),
674 PINMUX_IPSR_GPSR(IP3_3_0, IETX),
675 PINMUX_IPSR_GPSR(IP3_3_0, QCPV_QDE),
676
677 PINMUX_IPSR_GPSR(IP3_7_4, A2),
678 PINMUX_IPSR_GPSR(IP3_7_4, IRQ2),
679 PINMUX_IPSR_GPSR(IP3_7_4, AVB_AVTP_PPS),
680 PINMUX_IPSR_GPSR(IP3_7_4, VI4_CLKENB),
681 PINMUX_IPSR_MSEL(IP3_7_4, VI5_DATA1_A, SEL_VIN5_0),
682 PINMUX_IPSR_GPSR(IP3_7_4, DU_DISP),
683 PINMUX_IPSR_MSEL(IP3_7_4, SCL6_B, SEL_I2C6_1),
684 PINMUX_IPSR_GPSR(IP3_7_4, QSTVB_QVE),
685
686 PINMUX_IPSR_GPSR(IP3_11_8, A3),
687 PINMUX_IPSR_MSEL(IP3_11_8, CTS4_N_A, SEL_SCIF4_0),
688 PINMUX_IPSR_MSEL(IP3_11_8, PWM4_A, SEL_PWM4_0),
689 PINMUX_IPSR_GPSR(IP3_11_8, VI4_DATA12),
690 PINMUX_IPSR_GPSR(IP3_11_8, DU_DOTCLKOUT0),
691 PINMUX_IPSR_GPSR(IP3_11_8, HTX3_D),
692 PINMUX_IPSR_GPSR(IP3_11_8, IECLK),
693 PINMUX_IPSR_GPSR(IP3_11_8, LCDOUT12),
694
695 PINMUX_IPSR_GPSR(IP3_15_12, A4),
696 PINMUX_IPSR_MSEL(IP3_15_12, RTS4_N_A, SEL_SCIF4_0),
697 PINMUX_IPSR_MSEL(IP3_15_12, MSIOF3_SYNC_B, SEL_MSIOF3_1),
698 PINMUX_IPSR_GPSR(IP3_15_12, VI4_DATA8),
699 PINMUX_IPSR_MSEL(IP3_15_12, PWM2_B, SEL_PWM2_1),
700 PINMUX_IPSR_GPSR(IP3_15_12, DU_DG4),
701 PINMUX_IPSR_MSEL(IP3_15_12, RIF2_CLK_B, SEL_DRIF2_1),
702
703 PINMUX_IPSR_GPSR(IP3_19_16, A5),
704 PINMUX_IPSR_MSEL(IP3_19_16, SCK4_A, SEL_SCIF4_0),
705 PINMUX_IPSR_MSEL(IP3_19_16, MSIOF3_SCK_B, SEL_MSIOF3_1),
706 PINMUX_IPSR_GPSR(IP3_19_16, VI4_DATA9),
707 PINMUX_IPSR_MSEL(IP3_19_16, PWM3_B, SEL_PWM3_1),
708 PINMUX_IPSR_MSEL(IP3_19_16, RIF2_SYNC_B, SEL_DRIF2_1),
709 PINMUX_IPSR_GPSR(IP3_19_16, QPOLA),
710
711 PINMUX_IPSR_GPSR(IP3_23_20, A6),
712 PINMUX_IPSR_MSEL(IP3_23_20, RX4_A, SEL_SCIF4_0),
713 PINMUX_IPSR_MSEL(IP3_23_20, MSIOF3_RXD_B, SEL_MSIOF3_1),
714 PINMUX_IPSR_GPSR(IP3_23_20, VI4_DATA10),
715 PINMUX_IPSR_MSEL(IP3_23_20, RIF2_D0_B, SEL_DRIF2_1),
716
717 PINMUX_IPSR_GPSR(IP3_27_24, A7),
718 PINMUX_IPSR_GPSR(IP3_27_24, TX4_A),
719 PINMUX_IPSR_GPSR(IP3_27_24, MSIOF3_TXD_B),
720 PINMUX_IPSR_GPSR(IP3_27_24, VI4_DATA11),
721 PINMUX_IPSR_MSEL(IP3_27_24, RIF2_D1_B, SEL_DRIF2_1),
722
723 PINMUX_IPSR_GPSR(IP3_31_28, A8),
724 PINMUX_IPSR_MSEL(IP3_31_28, SDA6_A, SEL_I2C6_0),
725 PINMUX_IPSR_MSEL(IP3_31_28, RX3_B, SEL_SCIF3_1),
726 PINMUX_IPSR_MSEL(IP3_31_28, HRX4_C, SEL_HSCIF4_2),
727 PINMUX_IPSR_MSEL(IP3_31_28, VI5_HSYNC_N_A, SEL_VIN5_0),
728 PINMUX_IPSR_GPSR(IP3_31_28, DU_HSYNC),
729 PINMUX_IPSR_MSEL(IP3_31_28, VI4_DATA0_B, SEL_VIN4_1),
730 PINMUX_IPSR_GPSR(IP3_31_28, QSTH_QHS),
731
732 /* IPSR4 */
733 PINMUX_IPSR_GPSR(IP4_3_0, A9),
734 PINMUX_IPSR_GPSR(IP4_3_0, TX5_A),
735 PINMUX_IPSR_GPSR(IP4_3_0, IRQ3),
736 PINMUX_IPSR_GPSR(IP4_3_0, VI4_DATA16),
737 PINMUX_IPSR_MSEL(IP4_3_0, VI5_VSYNC_N_A, SEL_VIN5_0),
738 PINMUX_IPSR_GPSR(IP4_3_0, DU_DG7),
739 PINMUX_IPSR_GPSR(IP4_3_0, LCDOUT15),
740
741 PINMUX_IPSR_GPSR(IP4_7_4, A10),
742 PINMUX_IPSR_GPSR(IP4_7_4, IRQ4),
743 PINMUX_IPSR_MSEL(IP4_7_4, MSIOF2_SYNC_B, SEL_MSIOF2_1),
744 PINMUX_IPSR_GPSR(IP4_7_4, VI4_DATA13),
745 PINMUX_IPSR_MSEL(IP4_7_4, VI5_FIELD_A, SEL_VIN5_0),
746 PINMUX_IPSR_GPSR(IP4_7_4, DU_DG5),
747 PINMUX_IPSR_GPSR(IP4_7_4, FSCLKST2_N_B),
748 PINMUX_IPSR_GPSR(IP4_7_4, LCDOUT13),
749
750 PINMUX_IPSR_GPSR(IP4_11_8, A11),
751 PINMUX_IPSR_MSEL(IP4_11_8, SCL6_A, SEL_I2C6_0),
752 PINMUX_IPSR_GPSR(IP4_11_8, TX3_B),
753 PINMUX_IPSR_GPSR(IP4_11_8, HTX4_C),
754 PINMUX_IPSR_GPSR(IP4_11_8, DU_VSYNC),
755 PINMUX_IPSR_MSEL(IP4_11_8, VI4_DATA1_B, SEL_VIN4_1),
756 PINMUX_IPSR_GPSR(IP4_11_8, QSTVA_QVS),
757
758 PINMUX_IPSR_GPSR(IP4_15_12, A12),
759 PINMUX_IPSR_MSEL(IP4_15_12, RX5_A, SEL_SCIF5_0),
760 PINMUX_IPSR_GPSR(IP4_15_12, MSIOF2_SS2_B),
761 PINMUX_IPSR_GPSR(IP4_15_12, VI4_DATA17),
762 PINMUX_IPSR_MSEL(IP4_15_12, VI5_DATA3_A, SEL_VIN5_0),
763 PINMUX_IPSR_GPSR(IP4_15_12, DU_DG6),
764 PINMUX_IPSR_GPSR(IP4_15_12, LCDOUT14),
765
766 PINMUX_IPSR_GPSR(IP4_19_16, A13),
767 PINMUX_IPSR_MSEL(IP4_19_16, SCK5_A, SEL_SCIF5_0),
768 PINMUX_IPSR_MSEL(IP4_19_16, MSIOF2_SCK_B, SEL_MSIOF2_1),
769 PINMUX_IPSR_GPSR(IP4_19_16, VI4_DATA14),
770 PINMUX_IPSR_MSEL(IP4_19_16, HRX4_D, SEL_HSCIF4_3),
771 PINMUX_IPSR_GPSR(IP4_19_16, DU_DB2),
772 PINMUX_IPSR_GPSR(IP4_19_16, LCDOUT2),
773
774 PINMUX_IPSR_GPSR(IP4_23_20, A14),
775 PINMUX_IPSR_GPSR(IP4_23_20, MSIOF1_SS1),
776 PINMUX_IPSR_MSEL(IP4_23_20, MSIOF2_RXD_B, SEL_MSIOF2_1),
777 PINMUX_IPSR_GPSR(IP4_23_20, VI4_DATA15),
778 PINMUX_IPSR_GPSR(IP4_23_20, HTX4_D),
779 PINMUX_IPSR_GPSR(IP4_23_20, DU_DB3),
780 PINMUX_IPSR_GPSR(IP4_23_20, LCDOUT3),
781
782 PINMUX_IPSR_GPSR(IP4_27_24, A15),
783 PINMUX_IPSR_GPSR(IP4_27_24, MSIOF1_SS2),
784 PINMUX_IPSR_GPSR(IP4_27_24, MSIOF2_TXD_B),
785 PINMUX_IPSR_GPSR(IP4_27_24, VI4_DATA18),
786 PINMUX_IPSR_MSEL(IP4_27_24, VI5_DATA4_A, SEL_VIN5_0),
787 PINMUX_IPSR_GPSR(IP4_27_24, DU_DB4),
788 PINMUX_IPSR_GPSR(IP4_27_24, LCDOUT4),
789
790 PINMUX_IPSR_GPSR(IP4_31_28, A16),
791 PINMUX_IPSR_GPSR(IP4_31_28, MSIOF1_SYNC),
792 PINMUX_IPSR_GPSR(IP4_31_28, MSIOF2_SS1_B),
793 PINMUX_IPSR_GPSR(IP4_31_28, VI4_DATA19),
794 PINMUX_IPSR_MSEL(IP4_31_28, VI5_DATA5_A, SEL_VIN5_0),
795 PINMUX_IPSR_GPSR(IP4_31_28, DU_DB5),
796 PINMUX_IPSR_GPSR(IP4_31_28, LCDOUT5),
797
798 /* IPSR5 */
799 PINMUX_IPSR_GPSR(IP5_3_0, A17),
800 PINMUX_IPSR_GPSR(IP5_3_0, MSIOF1_RXD),
801 PINMUX_IPSR_GPSR(IP5_3_0, VI4_DATA20),
802 PINMUX_IPSR_MSEL(IP5_3_0, VI5_DATA6_A, SEL_VIN5_0),
803 PINMUX_IPSR_GPSR(IP5_3_0, DU_DB6),
804 PINMUX_IPSR_GPSR(IP5_3_0, LCDOUT6),
805
806 PINMUX_IPSR_GPSR(IP5_7_4, A18),
807 PINMUX_IPSR_GPSR(IP5_7_4, MSIOF1_TXD),
808 PINMUX_IPSR_GPSR(IP5_7_4, VI4_DATA21),
809 PINMUX_IPSR_MSEL(IP5_7_4, VI5_DATA7_A, SEL_VIN5_0),
810 PINMUX_IPSR_GPSR(IP5_7_4, DU_DB0),
811 PINMUX_IPSR_MSEL(IP5_7_4, HRX4_E, SEL_HSCIF4_4),
812 PINMUX_IPSR_GPSR(IP5_7_4, LCDOUT0),
813
814 PINMUX_IPSR_GPSR(IP5_11_8, A19),
815 PINMUX_IPSR_GPSR(IP5_11_8, MSIOF1_SCK),
816 PINMUX_IPSR_GPSR(IP5_11_8, VI4_DATA22),
817 PINMUX_IPSR_MSEL(IP5_11_8, VI5_DATA2_A, SEL_VIN5_0),
818 PINMUX_IPSR_GPSR(IP5_11_8, DU_DB1),
819 PINMUX_IPSR_GPSR(IP5_11_8, HTX4_E),
820 PINMUX_IPSR_GPSR(IP5_11_8, LCDOUT1),
821
822 PINMUX_IPSR_GPSR(IP5_15_12, CS0_N),
823 PINMUX_IPSR_GPSR(IP5_15_12, SCL5),
824 PINMUX_IPSR_GPSR(IP5_15_12, DU_DR0),
825 PINMUX_IPSR_MSEL(IP5_15_12, VI4_DATA2_B, SEL_VIN4_1),
826 PINMUX_IPSR_GPSR(IP5_15_12, LCDOUT16),
827
828 PINMUX_IPSR_GPSR(IP5_19_16, WE0_N),
829 PINMUX_IPSR_GPSR(IP5_19_16, SDA5),
830 PINMUX_IPSR_GPSR(IP5_19_16, DU_DR1),
831 PINMUX_IPSR_MSEL(IP5_19_16, VI4_DATA3_B, SEL_VIN4_1),
832 PINMUX_IPSR_GPSR(IP5_19_16, LCDOUT17),
833
834 PINMUX_IPSR_GPSR(IP5_23_20, D0),
835 PINMUX_IPSR_MSEL(IP5_23_20, MSIOF3_SCK_A, SEL_MSIOF3_0),
836 PINMUX_IPSR_GPSR(IP5_23_20, DU_DR2),
837 PINMUX_IPSR_MSEL(IP5_23_20, CTS4_N_C, SEL_SCIF4_2),
838 PINMUX_IPSR_GPSR(IP5_23_20, LCDOUT18),
839
840 PINMUX_IPSR_GPSR(IP5_27_24, D1),
841 PINMUX_IPSR_MSEL(IP5_27_24, MSIOF3_SYNC_A, SEL_MSIOF3_0),
842 PINMUX_IPSR_MSEL(IP5_27_24, SCK3_A, SEL_SCIF3_0),
843 PINMUX_IPSR_GPSR(IP5_27_24, VI4_DATA23),
844 PINMUX_IPSR_MSEL(IP5_27_24, VI5_CLKENB_A, SEL_VIN5_0),
845 PINMUX_IPSR_GPSR(IP5_27_24, DU_DB7),
846 PINMUX_IPSR_MSEL(IP5_27_24, RTS4_N_C, SEL_SCIF4_2),
847 PINMUX_IPSR_GPSR(IP5_27_24, LCDOUT7),
848
849 PINMUX_IPSR_GPSR(IP5_31_28, D2),
850 PINMUX_IPSR_MSEL(IP5_31_28, MSIOF3_RXD_A, SEL_MSIOF3_0),
851 PINMUX_IPSR_MSEL(IP5_31_28, RX5_C, SEL_SCIF5_2),
852 PINMUX_IPSR_MSEL(IP5_31_28, VI5_DATA14_A, SEL_VIN5_0),
853 PINMUX_IPSR_GPSR(IP5_31_28, DU_DR3),
854 PINMUX_IPSR_MSEL(IP5_31_28, RX4_C, SEL_SCIF4_2),
855 PINMUX_IPSR_GPSR(IP5_31_28, LCDOUT19),
856
857 /* IPSR6 */
858 PINMUX_IPSR_GPSR(IP6_3_0, D3),
859 PINMUX_IPSR_GPSR(IP6_3_0, MSIOF3_TXD_A),
860 PINMUX_IPSR_GPSR(IP6_3_0, TX5_C),
861 PINMUX_IPSR_MSEL(IP6_3_0, VI5_DATA15_A, SEL_VIN5_0),
862 PINMUX_IPSR_GPSR(IP6_3_0, DU_DR4),
863 PINMUX_IPSR_GPSR(IP6_3_0, TX4_C),
864 PINMUX_IPSR_GPSR(IP6_3_0, LCDOUT20),
865
866 PINMUX_IPSR_GPSR(IP6_7_4, D4),
867 PINMUX_IPSR_GPSR(IP6_7_4, CANFD1_TX),
868 PINMUX_IPSR_MSEL(IP6_7_4, HSCK3_B, SEL_HSCIF3_1),
869 PINMUX_IPSR_GPSR(IP6_7_4, CAN1_TX),
870 PINMUX_IPSR_MSEL(IP6_7_4, RTS3_N_A, SEL_SCIF3_0),
871 PINMUX_IPSR_GPSR(IP6_7_4, MSIOF3_SS2_A),
872 PINMUX_IPSR_MSEL(IP6_7_4, VI5_DATA1_B, SEL_VIN5_1),
873
874 PINMUX_IPSR_GPSR(IP6_11_8, D5),
875 PINMUX_IPSR_MSEL(IP6_11_8, RX3_A, SEL_SCIF3_0),
876 PINMUX_IPSR_MSEL(IP6_11_8, HRX3_B, SEL_HSCIF3_1),
877 PINMUX_IPSR_GPSR(IP6_11_8, DU_DR5),
878 PINMUX_IPSR_MSEL(IP6_11_8, VI4_DATA4_B, SEL_VIN4_1),
879 PINMUX_IPSR_GPSR(IP6_11_8, LCDOUT21),
880
881 PINMUX_IPSR_GPSR(IP6_15_12, D6),
882 PINMUX_IPSR_GPSR(IP6_15_12, TX3_A),
883 PINMUX_IPSR_GPSR(IP6_15_12, HTX3_B),
884 PINMUX_IPSR_GPSR(IP6_15_12, DU_DR6),
885 PINMUX_IPSR_MSEL(IP6_15_12, VI4_DATA5_B, SEL_VIN4_1),
886 PINMUX_IPSR_GPSR(IP6_15_12, LCDOUT22),
887
888 PINMUX_IPSR_GPSR(IP6_19_16, D7),
889 PINMUX_IPSR_GPSR(IP6_19_16, CANFD1_RX),
890 PINMUX_IPSR_GPSR(IP6_19_16, IRQ5),
891 PINMUX_IPSR_GPSR(IP6_19_16, CAN1_RX),
892 PINMUX_IPSR_MSEL(IP6_19_16, CTS3_N_A, SEL_SCIF3_0),
893 PINMUX_IPSR_MSEL(IP6_19_16, VI5_DATA2_B, SEL_VIN5_1),
894
895 PINMUX_IPSR_GPSR(IP6_23_20, D8),
896 PINMUX_IPSR_MSEL(IP6_23_20, MSIOF2_SCK_A, SEL_MSIOF2_0),
897 PINMUX_IPSR_MSEL(IP6_23_20, SCK4_B, SEL_SCIF4_1),
898 PINMUX_IPSR_MSEL(IP6_23_20, VI5_DATA12_A, SEL_VIN5_0),
899 PINMUX_IPSR_GPSR(IP6_23_20, DU_DR7),
900 PINMUX_IPSR_MSEL(IP6_23_20, RIF3_CLK_B, SEL_DRIF3_1),
901 PINMUX_IPSR_MSEL(IP6_23_20, HCTS3_N_E, SEL_HSCIF3_4),
902 PINMUX_IPSR_GPSR(IP6_23_20, LCDOUT23),
903
904 PINMUX_IPSR_GPSR(IP6_27_24, D9),
905 PINMUX_IPSR_MSEL(IP6_27_24, MSIOF2_SYNC_A, SEL_MSIOF2_0),
906 PINMUX_IPSR_MSEL(IP6_27_24, VI5_DATA10_A, SEL_VIN5_0),
907 PINMUX_IPSR_GPSR(IP6_27_24, DU_DG0),
908 PINMUX_IPSR_MSEL(IP6_27_24, RIF3_SYNC_B, SEL_DRIF3_1),
909 PINMUX_IPSR_MSEL(IP6_27_24, HRX3_E, SEL_HSCIF3_4),
910 PINMUX_IPSR_GPSR(IP6_27_24, LCDOUT8),
911
912 PINMUX_IPSR_GPSR(IP6_31_28, D10),
913 PINMUX_IPSR_MSEL(IP6_31_28, MSIOF2_RXD_A, SEL_MSIOF2_0),
914 PINMUX_IPSR_MSEL(IP6_31_28, VI5_DATA13_A, SEL_VIN5_0),
915 PINMUX_IPSR_GPSR(IP6_31_28, DU_DG1),
916 PINMUX_IPSR_MSEL(IP6_31_28, RIF3_D0_B, SEL_DRIF3_1),
917 PINMUX_IPSR_GPSR(IP6_31_28, HTX3_E),
918 PINMUX_IPSR_GPSR(IP6_31_28, LCDOUT9),
919
920 /* IPSR7 */
921 PINMUX_IPSR_GPSR(IP7_3_0, D11),
922 PINMUX_IPSR_GPSR(IP7_3_0, MSIOF2_TXD_A),
923 PINMUX_IPSR_MSEL(IP7_3_0, VI5_DATA11_A, SEL_VIN5_0),
924 PINMUX_IPSR_GPSR(IP7_3_0, DU_DG2),
925 PINMUX_IPSR_MSEL(IP7_3_0, RIF3_D1_B, SEL_DRIF3_1),
926 PINMUX_IPSR_MSEL(IP7_3_0, HRTS3_N_E, SEL_HSCIF3_4),
927 PINMUX_IPSR_GPSR(IP7_3_0, LCDOUT10),
928
929 PINMUX_IPSR_GPSR(IP7_7_4, D12),
930 PINMUX_IPSR_GPSR(IP7_7_4, CANFD0_TX),
931 PINMUX_IPSR_GPSR(IP7_7_4, TX4_B),
932 PINMUX_IPSR_GPSR(IP7_7_4, CAN0_TX),
933 PINMUX_IPSR_MSEL(IP7_7_4, VI5_DATA8_A, SEL_VIN5_0),
934 PINMUX_IPSR_MSEL(IP7_7_4, VI5_DATA3_B, SEL_VIN5_1),
935
936 PINMUX_IPSR_GPSR(IP7_11_8, D13),
937 PINMUX_IPSR_GPSR(IP7_11_8, CANFD0_RX),
938 PINMUX_IPSR_MSEL(IP7_11_8, RX4_B, SEL_SCIF4_1),
939 PINMUX_IPSR_GPSR(IP7_11_8, CAN0_RX),
940 PINMUX_IPSR_MSEL(IP7_11_8, VI5_DATA9_A, SEL_VIN5_0),
941 PINMUX_IPSR_MSEL(IP7_11_8, SCL7_B, SEL_I2C7_1),
942 PINMUX_IPSR_MSEL(IP7_11_8, VI5_DATA4_B, SEL_VIN5_1),
943
944 PINMUX_IPSR_GPSR(IP7_15_12, D14),
945 PINMUX_IPSR_GPSR(IP7_15_12, CAN_CLK),
946 PINMUX_IPSR_MSEL(IP7_15_12, HRX3_A, SEL_HSCIF3_0),
947 PINMUX_IPSR_GPSR(IP7_15_12, MSIOF2_SS2_A),
948 PINMUX_IPSR_MSEL(IP7_15_12, SDA7_B, SEL_I2C7_1),
949 PINMUX_IPSR_MSEL(IP7_15_12, VI5_DATA5_B, SEL_VIN5_1),
950
951 PINMUX_IPSR_GPSR(IP7_19_16, D15),
952 PINMUX_IPSR_GPSR(IP7_19_16, MSIOF2_SS1_A),
953 PINMUX_IPSR_GPSR(IP7_19_16, HTX3_A),
954 PINMUX_IPSR_GPSR(IP7_19_16, MSIOF3_SS1_A),
955 PINMUX_IPSR_GPSR(IP7_19_16, DU_DG3),
956 PINMUX_IPSR_GPSR(IP7_19_16, LCDOUT11),
957
958 PINMUX_IPSR_GPSR(IP7_23_20, SCL4),
959 PINMUX_IPSR_GPSR(IP7_23_20, CS1_N_A26),
960 PINMUX_IPSR_GPSR(IP7_23_20, DU_DOTCLKIN0),
961 PINMUX_IPSR_MSEL(IP7_23_20, VI4_DATA6_B, SEL_VIN4_1),
962 PINMUX_IPSR_MSEL(IP7_23_20, VI5_DATA6_B, SEL_VIN5_1),
963 PINMUX_IPSR_GPSR(IP7_23_20, QCLK),
964
965 PINMUX_IPSR_GPSR(IP7_27_24, SDA4),
966 PINMUX_IPSR_GPSR(IP7_27_24, WE1_N),
967 PINMUX_IPSR_MSEL(IP7_27_24, VI4_DATA7_B, SEL_VIN4_1),
968 PINMUX_IPSR_MSEL(IP7_27_24, VI5_DATA7_B, SEL_VIN5_1),
969 PINMUX_IPSR_GPSR(IP7_27_24, QPOLB),
970
971 PINMUX_IPSR_GPSR(IP7_31_28, SD0_CLK),
972 PINMUX_IPSR_GPSR(IP7_31_28, NFDATA8),
973 PINMUX_IPSR_MSEL(IP7_31_28, SCL1_C, SEL_I2C1_2),
974 PINMUX_IPSR_MSEL(IP7_31_28, HSCK1_B, SEL_HSCIF1_1),
975 PINMUX_IPSR_MSEL(IP7_31_28, SDA2_E, SEL_I2C2_4),
976 PINMUX_IPSR_MSEL(IP7_31_28, FMCLK_B, SEL_FM_1),
977
978 /* IPSR8 */
979 PINMUX_IPSR_GPSR(IP8_3_0, SD0_CMD),
980 PINMUX_IPSR_GPSR(IP8_3_0, NFDATA9),
981 PINMUX_IPSR_MSEL(IP8_3_0, HRX1_B, SEL_HSCIF1_1),
982 PINMUX_IPSR_MSEL(IP8_3_0, SPEEDIN_B, SEL_SPEED_PULSE_IF_1),
983
984 PINMUX_IPSR_GPSR(IP8_7_4, SD0_DAT0),
985 PINMUX_IPSR_GPSR(IP8_7_4, NFDATA10),
986 PINMUX_IPSR_GPSR(IP8_7_4, HTX1_B),
987 PINMUX_IPSR_MSEL(IP8_7_4, REMOCON_B, SEL_REMOCON_1),
988
989 PINMUX_IPSR_GPSR(IP8_11_8, SD0_DAT1),
990 PINMUX_IPSR_GPSR(IP8_11_8, NFDATA11),
991 PINMUX_IPSR_MSEL(IP8_11_8, SDA2_C, SEL_I2C2_2),
992 PINMUX_IPSR_MSEL(IP8_11_8, HCTS1_N_B, SEL_HSCIF1_1),
993 PINMUX_IPSR_MSEL(IP8_11_8, FMIN_B, SEL_FM_1),
994
995 PINMUX_IPSR_GPSR(IP8_15_12, SD0_DAT2),
996 PINMUX_IPSR_GPSR(IP8_15_12, NFDATA12),
997 PINMUX_IPSR_MSEL(IP8_15_12, SCL2_C, SEL_I2C2_2),
998 PINMUX_IPSR_MSEL(IP8_15_12, HRTS1_N_B, SEL_HSCIF1_1),
999 PINMUX_IPSR_GPSR(IP8_15_12, BPFCLK_B),
1000
1001 PINMUX_IPSR_GPSR(IP8_19_16, SD0_DAT3),
1002 PINMUX_IPSR_GPSR(IP8_19_16, NFDATA13),
1003 PINMUX_IPSR_MSEL(IP8_19_16, SDA1_C, SEL_I2C1_2),
1004 PINMUX_IPSR_MSEL(IP8_19_16, SCL2_E, SEL_I2C2_4),
1005 PINMUX_IPSR_MSEL(IP8_19_16, SPEEDIN_C, SEL_SPEED_PULSE_IF_2),
1006 PINMUX_IPSR_MSEL(IP8_19_16, REMOCON_C, SEL_REMOCON_2),
1007
1008 PINMUX_IPSR_GPSR(IP8_23_20, SD1_CLK),
1009 PINMUX_IPSR_MSEL(IP8_23_20, NFDATA14_B, SEL_NDF_1),
1010
1011 PINMUX_IPSR_GPSR(IP8_27_24, SD1_CMD),
1012 PINMUX_IPSR_MSEL(IP8_27_24, NFDATA15_B, SEL_NDF_1),
1013
1014 PINMUX_IPSR_GPSR(IP8_31_28, SD1_DAT0),
1015 PINMUX_IPSR_MSEL(IP8_31_28, NFWP_N_B, SEL_NDF_1),
1016
1017 /* IPSR9 */
1018 PINMUX_IPSR_GPSR(IP9_3_0, SD1_DAT1),
1019 PINMUX_IPSR_MSEL(IP9_3_0, NFCE_N_B, SEL_NDF_1),
1020
1021 PINMUX_IPSR_GPSR(IP9_7_4, SD1_DAT2),
1022 PINMUX_IPSR_MSEL(IP9_7_4, NFALE_B, SEL_NDF_1),
1023
1024 PINMUX_IPSR_GPSR(IP9_11_8, SD1_DAT3),
1025 PINMUX_IPSR_MSEL(IP9_11_8, NFRB_N_B, SEL_NDF_1),
1026
1027 PINMUX_IPSR_GPSR(IP9_15_12, SD3_CLK),
1028 PINMUX_IPSR_GPSR(IP9_15_12, NFWE_N),
1029
1030 PINMUX_IPSR_GPSR(IP9_19_16, SD3_CMD),
1031 PINMUX_IPSR_GPSR(IP9_19_16, NFRE_N),
1032
1033 PINMUX_IPSR_GPSR(IP9_23_20, SD3_DAT0),
1034 PINMUX_IPSR_GPSR(IP9_23_20, NFDATA0),
1035
1036 PINMUX_IPSR_GPSR(IP9_27_24, SD3_DAT1),
1037 PINMUX_IPSR_GPSR(IP9_27_24, NFDATA1),
1038
1039 PINMUX_IPSR_GPSR(IP9_31_28, SD3_DAT2),
1040 PINMUX_IPSR_GPSR(IP9_31_28, NFDATA2),
1041
1042 /* IPSR10 */
1043 PINMUX_IPSR_GPSR(IP10_3_0, SD3_DAT3),
1044 PINMUX_IPSR_GPSR(IP10_3_0, NFDATA3),
1045
1046 PINMUX_IPSR_GPSR(IP10_7_4, SD3_DAT4),
1047 PINMUX_IPSR_GPSR(IP10_7_4, NFDATA4),
1048
1049 PINMUX_IPSR_GPSR(IP10_11_8, SD3_DAT5),
1050 PINMUX_IPSR_GPSR(IP10_11_8, NFDATA5),
1051
1052 PINMUX_IPSR_GPSR(IP10_15_12, SD3_DAT6),
1053 PINMUX_IPSR_GPSR(IP10_15_12, NFDATA6),
1054
1055 PINMUX_IPSR_GPSR(IP10_19_16, SD3_DAT7),
1056 PINMUX_IPSR_GPSR(IP10_19_16, NFDATA7),
1057
1058 PINMUX_IPSR_GPSR(IP10_23_20, SD3_DS),
1059 PINMUX_IPSR_GPSR(IP10_23_20, NFCLE),
1060
1061 PINMUX_IPSR_GPSR(IP10_27_24, SD0_CD),
1062 PINMUX_IPSR_MSEL(IP10_27_24, NFALE_A, SEL_NDF_0),
1063 PINMUX_IPSR_GPSR(IP10_27_24, SD3_CD),
1064 PINMUX_IPSR_MSEL(IP10_27_24, RIF0_CLK_B, SEL_DRIF0_1),
1065 PINMUX_IPSR_MSEL(IP10_27_24, SCL2_B, SEL_I2C2_1),
1066 PINMUX_IPSR_MSEL(IP10_27_24, TCLK1_A, SEL_TIMER_TMU_0),
1067 PINMUX_IPSR_MSEL(IP10_27_24, SSI_SCK2_B, SEL_SSI2_1),
1068 PINMUX_IPSR_GPSR(IP10_27_24, TS_SCK0),
1069
1070 PINMUX_IPSR_GPSR(IP10_31_28, SD0_WP),
1071 PINMUX_IPSR_MSEL(IP10_31_28, NFRB_N_A, SEL_NDF_0),
1072 PINMUX_IPSR_GPSR(IP10_31_28, SD3_WP),
1073 PINMUX_IPSR_MSEL(IP10_31_28, RIF0_D0_B, SEL_DRIF0_1),
1074 PINMUX_IPSR_MSEL(IP10_31_28, SDA2_B, SEL_I2C2_1),
1075 PINMUX_IPSR_MSEL(IP10_31_28, TCLK2_A, SEL_TIMER_TMU_0),
1076 PINMUX_IPSR_MSEL(IP10_31_28, SSI_WS2_B, SEL_SSI2_1),
1077 PINMUX_IPSR_GPSR(IP10_31_28, TS_SDAT0),
1078
1079 /* IPSR11 */
1080 PINMUX_IPSR_GPSR(IP11_3_0, SD1_CD),
1081 PINMUX_IPSR_MSEL(IP11_3_0, NFCE_N_A, SEL_NDF_0),
1082 PINMUX_IPSR_GPSR(IP11_3_0, SSI_SCK1),
1083 PINMUX_IPSR_MSEL(IP11_3_0, RIF0_D1_B, SEL_DRIF0_1),
1084 PINMUX_IPSR_GPSR(IP11_3_0, TS_SDEN0),
1085
1086 PINMUX_IPSR_GPSR(IP11_7_4, SD1_WP),
1087 PINMUX_IPSR_MSEL(IP11_7_4, NFWP_N_A, SEL_NDF_0),
1088 PINMUX_IPSR_GPSR(IP11_7_4, SSI_WS1),
1089 PINMUX_IPSR_MSEL(IP11_7_4, RIF0_SYNC_B, SEL_DRIF0_1),
1090 PINMUX_IPSR_GPSR(IP11_7_4, TS_SPSYNC0),
1091
1092 PINMUX_IPSR_MSEL(IP11_11_8, RX0_A, SEL_SCIF0_0),
1093 PINMUX_IPSR_MSEL(IP11_11_8, HRX1_A, SEL_HSCIF1_0),
1094 PINMUX_IPSR_MSEL(IP11_11_8, SSI_SCK2_A, SEL_SSI2_0),
1095 PINMUX_IPSR_GPSR(IP11_11_8, RIF1_SYNC),
1096 PINMUX_IPSR_GPSR(IP11_11_8, TS_SCK1),
1097
1098 PINMUX_IPSR_MSEL(IP11_15_12, TX0_A, SEL_SCIF0_0),
1099 PINMUX_IPSR_GPSR(IP11_15_12, HTX1_A),
1100 PINMUX_IPSR_MSEL(IP11_15_12, SSI_WS2_A, SEL_SSI2_0),
1101 PINMUX_IPSR_GPSR(IP11_15_12, RIF1_D0),
1102 PINMUX_IPSR_GPSR(IP11_15_12, TS_SDAT1),
1103
1104 PINMUX_IPSR_MSEL(IP11_19_16, CTS0_N_A, SEL_SCIF0_0),
1105 PINMUX_IPSR_MSEL(IP11_19_16, NFDATA14_A, SEL_NDF_0),
1106 PINMUX_IPSR_GPSR(IP11_19_16, AUDIO_CLKOUT_A),
1107 PINMUX_IPSR_GPSR(IP11_19_16, RIF1_D1),
1108 PINMUX_IPSR_MSEL(IP11_19_16, SCIF_CLK_A, SEL_SCIF_0),
1109 PINMUX_IPSR_MSEL(IP11_19_16, FMCLK_A, SEL_FM_0),
1110
1111 PINMUX_IPSR_MSEL(IP11_23_20, RTS0_N_A, SEL_SCIF0_0),
1112 PINMUX_IPSR_MSEL(IP11_23_20, NFDATA15_A, SEL_NDF_0),
1113 PINMUX_IPSR_GPSR(IP11_23_20, AUDIO_CLKOUT1_A),
1114 PINMUX_IPSR_GPSR(IP11_23_20, RIF1_CLK),
1115 PINMUX_IPSR_MSEL(IP11_23_20, SCL2_A, SEL_I2C2_0),
1116 PINMUX_IPSR_MSEL(IP11_23_20, FMIN_A, SEL_FM_0),
1117
1118 PINMUX_IPSR_MSEL(IP11_27_24, SCK0_A, SEL_SCIF0_0),
1119 PINMUX_IPSR_MSEL(IP11_27_24, HSCK1_A, SEL_HSCIF1_0),
1120 PINMUX_IPSR_GPSR(IP11_27_24, USB3HS0_ID),
1121 PINMUX_IPSR_GPSR(IP11_27_24, RTS1_N),
1122 PINMUX_IPSR_MSEL(IP11_27_24, SDA2_A, SEL_I2C2_0),
1123 PINMUX_IPSR_MSEL(IP11_27_24, FMCLK_C, SEL_FM_2),
1124 PINMUX_IPSR_GPSR(IP11_27_24, USB0_ID),
1125
1126 PINMUX_IPSR_GPSR(IP11_31_28, RX1),
1127 PINMUX_IPSR_MSEL(IP11_31_28, HRX2_B, SEL_HSCIF2_1),
1128 PINMUX_IPSR_MSEL(IP11_31_28, SSI_SCK9_B, SEL_SSI9_1),
1129 PINMUX_IPSR_GPSR(IP11_31_28, AUDIO_CLKOUT1_B),
1130
1131 /* IPSR12 */
1132 PINMUX_IPSR_GPSR(IP12_3_0, TX1),
1133 PINMUX_IPSR_GPSR(IP12_3_0, HTX2_B),
1134 PINMUX_IPSR_MSEL(IP12_3_0, SSI_WS9_B, SEL_SSI9_1),
1135 PINMUX_IPSR_GPSR(IP12_3_0, AUDIO_CLKOUT3_B),
1136
1137 PINMUX_IPSR_MSEL(IP12_7_4, SCK2_A, SEL_SCIF2_0),
1138 PINMUX_IPSR_MSEL(IP12_7_4, HSCK0_A, SEL_HSCIF0_0),
1139 PINMUX_IPSR_MSEL(IP12_7_4, AUDIO_CLKB_A, SEL_ADGB_0),
1140 PINMUX_IPSR_GPSR(IP12_7_4, CTS1_N),
1141 PINMUX_IPSR_MSEL(IP12_7_4, RIF0_CLK_A, SEL_DRIF0_0),
1142 PINMUX_IPSR_MSEL(IP12_7_4, REMOCON_A, SEL_REMOCON_0),
1143 PINMUX_IPSR_MSEL(IP12_7_4, SCIF_CLK_B, SEL_SCIF_1),
1144
1145 PINMUX_IPSR_MSEL(IP12_11_8, TX2_A, SEL_SCIF2_0),
1146 PINMUX_IPSR_MSEL(IP12_11_8, HRX0_A, SEL_HSCIF0_0),
1147 PINMUX_IPSR_GPSR(IP12_11_8, AUDIO_CLKOUT2_A),
1148 PINMUX_IPSR_MSEL(IP12_11_8, SCL1_A, SEL_I2C1_0),
1149 PINMUX_IPSR_MSEL(IP12_11_8, FSO_CFE_0_N_A, SEL_FSO_0),
1150 PINMUX_IPSR_GPSR(IP12_11_8, TS_SDEN1),
1151
1152 PINMUX_IPSR_MSEL(IP12_15_12, RX2_A, SEL_SCIF2_0),
1153 PINMUX_IPSR_GPSR(IP12_15_12, HTX0_A),
1154 PINMUX_IPSR_GPSR(IP12_15_12, AUDIO_CLKOUT3_A),
1155 PINMUX_IPSR_MSEL(IP12_15_12, SDA1_A, SEL_I2C1_0),
1156 PINMUX_IPSR_MSEL(IP12_15_12, FSO_CFE_1_N_A, SEL_FSO_0),
1157 PINMUX_IPSR_GPSR(IP12_15_12, TS_SPSYNC1),
1158
1159 PINMUX_IPSR_GPSR(IP12_19_16, MSIOF0_SCK),
1160 PINMUX_IPSR_GPSR(IP12_19_16, SSI_SCK78),
1161
1162 PINMUX_IPSR_GPSR(IP12_23_20, MSIOF0_RXD),
1163 PINMUX_IPSR_GPSR(IP12_23_20, SSI_WS78),
1164 PINMUX_IPSR_MSEL(IP12_23_20, TX2_B, SEL_SCIF2_1),
1165
1166 PINMUX_IPSR_GPSR(IP12_27_24, MSIOF0_TXD),
1167 PINMUX_IPSR_GPSR(IP12_27_24, SSI_SDATA7),
1168 PINMUX_IPSR_MSEL(IP12_27_24, RX2_B, SEL_SCIF2_1),
1169
1170 PINMUX_IPSR_GPSR(IP12_31_28, MSIOF0_SYNC),
1171 PINMUX_IPSR_GPSR(IP12_31_28, AUDIO_CLKOUT_B),
1172 PINMUX_IPSR_GPSR(IP12_31_28, SSI_SDATA8),
1173
1174 /* IPSR13 */
1175 PINMUX_IPSR_GPSR(IP13_3_0, MSIOF0_SS1),
1176 PINMUX_IPSR_MSEL(IP13_3_0, HRX2_A, SEL_HSCIF2_0),
1177 PINMUX_IPSR_GPSR(IP13_3_0, SSI_SCK4),
1178 PINMUX_IPSR_MSEL(IP13_3_0, HCTS0_N_A, SEL_HSCIF0_0),
1179 PINMUX_IPSR_GPSR(IP13_3_0, BPFCLK_C),
1180 PINMUX_IPSR_MSEL(IP13_3_0, SPEEDIN_A, SEL_SPEED_PULSE_IF_0),
1181
1182 PINMUX_IPSR_GPSR(IP13_7_4, MSIOF0_SS2),
1183 PINMUX_IPSR_GPSR(IP13_7_4, HTX2_A),
1184 PINMUX_IPSR_GPSR(IP13_7_4, SSI_WS4),
1185 PINMUX_IPSR_MSEL(IP13_7_4, HRTS0_N_A, SEL_HSCIF0_0),
1186 PINMUX_IPSR_MSEL(IP13_7_4, FMIN_C, SEL_FM_2),
1187 PINMUX_IPSR_GPSR(IP13_7_4, BPFCLK_A),
1188
1189 PINMUX_IPSR_GPSR(IP13_11_8, SSI_SDATA9),
1190 PINMUX_IPSR_MSEL(IP13_11_8, AUDIO_CLKC_A, SEL_ADGC_0),
1191 PINMUX_IPSR_GPSR(IP13_11_8, SCK1),
1192
1193 PINMUX_IPSR_GPSR(IP13_15_12, MLB_CLK),
1194 PINMUX_IPSR_MSEL(IP13_15_12, RX0_B, SEL_SCIF0_1),
1195 PINMUX_IPSR_MSEL(IP13_15_12, RIF0_D0_A, SEL_DRIF0_0),
1196 PINMUX_IPSR_MSEL(IP13_15_12, SCL1_B, SEL_I2C1_1),
1197 PINMUX_IPSR_MSEL(IP13_15_12, TCLK1_B, SEL_TIMER_TMU_1),
1198 PINMUX_IPSR_GPSR(IP13_15_12, SIM0_RST_A),
1199
1200 PINMUX_IPSR_GPSR(IP13_19_16, MLB_SIG),
1201 PINMUX_IPSR_MSEL(IP13_19_16, SCK0_B, SEL_SCIF0_1),
1202 PINMUX_IPSR_MSEL(IP13_19_16, RIF0_D1_A, SEL_DRIF0_0),
1203 PINMUX_IPSR_MSEL(IP13_19_16, SDA1_B, SEL_I2C1_1),
1204 PINMUX_IPSR_MSEL(IP13_19_16, TCLK2_B, SEL_TIMER_TMU_1),
1205 PINMUX_IPSR_MSEL(IP13_19_16, SIM0_D_A, SEL_SIMCARD_0),
1206
1207 PINMUX_IPSR_GPSR(IP13_23_20, MLB_DAT),
1208 PINMUX_IPSR_MSEL(IP13_23_20, TX0_B, SEL_SCIF0_1),
1209 PINMUX_IPSR_MSEL(IP13_23_20, RIF0_SYNC_A, SEL_DRIF0_0),
1210 PINMUX_IPSR_GPSR(IP13_23_20, SIM0_CLK_A),
1211
1212 PINMUX_IPSR_GPSR(IP13_27_24, SSI_SCK01239),
1213
1214 PINMUX_IPSR_GPSR(IP13_31_28, SSI_WS01239),
1215
1216 /* IPSR14 */
1217 PINMUX_IPSR_GPSR(IP14_3_0, SSI_SDATA0),
1218
1219 PINMUX_IPSR_GPSR(IP14_7_4, SSI_SDATA1),
1220 PINMUX_IPSR_MSEL(IP14_7_4, AUDIO_CLKC_B, SEL_ADGC_1),
1221 PINMUX_IPSR_MSEL(IP14_7_4, PWM0_B, SEL_PWM0_1),
1222
1223 PINMUX_IPSR_GPSR(IP14_11_8, SSI_SDATA2),
1224 PINMUX_IPSR_GPSR(IP14_11_8, AUDIO_CLKOUT2_B),
1225 PINMUX_IPSR_MSEL(IP14_11_8, SSI_SCK9_A, SEL_SSI9_0),
1226 PINMUX_IPSR_MSEL(IP14_11_8, PWM1_B, SEL_PWM1_1),
1227
1228 PINMUX_IPSR_GPSR(IP14_15_12, SSI_SCK349),
1229 PINMUX_IPSR_MSEL(IP14_15_12, PWM2_C, SEL_PWM2_2),
1230
1231 PINMUX_IPSR_GPSR(IP14_19_16, SSI_WS349),
1232 PINMUX_IPSR_MSEL(IP14_19_16, PWM3_C, SEL_PWM3_2),
1233
1234 PINMUX_IPSR_GPSR(IP14_23_20, SSI_SDATA3),
1235 PINMUX_IPSR_GPSR(IP14_23_20, AUDIO_CLKOUT1_C),
1236 PINMUX_IPSR_MSEL(IP14_23_20, AUDIO_CLKB_B, SEL_ADGB_1),
1237 PINMUX_IPSR_MSEL(IP14_23_20, PWM4_B, SEL_PWM4_1),
1238
1239 PINMUX_IPSR_GPSR(IP14_27_24, SSI_SDATA4),
1240 PINMUX_IPSR_MSEL(IP14_27_24, SSI_WS9_A, SEL_SSI9_0),
1241 PINMUX_IPSR_MSEL(IP14_27_24, PWM5_B, SEL_PWM5_1),
1242
1243 PINMUX_IPSR_GPSR(IP14_31_28, SSI_SCK5),
1244 PINMUX_IPSR_MSEL(IP14_31_28, HRX0_B, SEL_HSCIF0_1),
1245 PINMUX_IPSR_GPSR(IP14_31_28, USB0_PWEN_B),
1246 PINMUX_IPSR_MSEL(IP14_31_28, SCL2_D, SEL_I2C2_3),
1247 PINMUX_IPSR_MSEL(IP14_31_28, PWM6_B, SEL_PWM6_1),
1248
1249 /* IPSR15 */
1250 PINMUX_IPSR_GPSR(IP15_3_0, SSI_WS5),
1251 PINMUX_IPSR_GPSR(IP15_3_0, HTX0_B),
1252 PINMUX_IPSR_MSEL(IP15_3_0, USB0_OVC_B, SEL_USB_20_CH0_1),
1253 PINMUX_IPSR_MSEL(IP15_3_0, SDA2_D, SEL_I2C2_3),
1254
1255 PINMUX_IPSR_GPSR(IP15_7_4, SSI_SDATA5),
1256 PINMUX_IPSR_MSEL(IP15_7_4, HSCK0_B, SEL_HSCIF0_1),
1257 PINMUX_IPSR_MSEL(IP15_7_4, AUDIO_CLKB_C, SEL_ADGB_2),
1258 PINMUX_IPSR_GPSR(IP15_7_4, TPU0TO0),
1259
1260 PINMUX_IPSR_GPSR(IP15_11_8, SSI_SCK6),
1261 PINMUX_IPSR_MSEL(IP15_11_8, HSCK2_A, SEL_HSCIF2_0),
1262 PINMUX_IPSR_MSEL(IP15_11_8, AUDIO_CLKC_C, SEL_ADGC_2),
1263 PINMUX_IPSR_GPSR(IP15_11_8, TPU0TO1),
1264 PINMUX_IPSR_MSEL(IP15_11_8, FSO_CFE_0_N_B, SEL_FSO_1),
1265 PINMUX_IPSR_GPSR(IP15_11_8, SIM0_RST_B),
1266
1267 PINMUX_IPSR_GPSR(IP15_15_12, SSI_WS6),
1268 PINMUX_IPSR_MSEL(IP15_15_12, HCTS2_N_A, SEL_HSCIF2_0),
1269 PINMUX_IPSR_GPSR(IP15_15_12, AUDIO_CLKOUT2_C),
1270 PINMUX_IPSR_GPSR(IP15_15_12, TPU0TO2),
1271 PINMUX_IPSR_MSEL(IP15_15_12, SDA1_D, SEL_I2C1_3),
1272 PINMUX_IPSR_MSEL(IP15_15_12, FSO_CFE_1_N_B, SEL_FSO_1),
1273 PINMUX_IPSR_MSEL(IP15_15_12, SIM0_D_B, SEL_SIMCARD_1),
1274
1275 PINMUX_IPSR_GPSR(IP15_19_16, SSI_SDATA6),
1276 PINMUX_IPSR_MSEL(IP15_19_16, HRTS2_N_A, SEL_HSCIF2_0),
1277 PINMUX_IPSR_GPSR(IP15_19_16, AUDIO_CLKOUT3_C),
1278 PINMUX_IPSR_GPSR(IP15_19_16, TPU0TO3),
1279 PINMUX_IPSR_MSEL(IP15_19_16, SCL1_D, SEL_I2C1_3),
1280 PINMUX_IPSR_MSEL(IP15_19_16, FSO_TOE_N_B, SEL_FSO_1),
1281 PINMUX_IPSR_GPSR(IP15_19_16, SIM0_CLK_B),
1282
1283 PINMUX_IPSR_GPSR(IP15_23_20, AUDIO_CLKA),
1284
1285 PINMUX_IPSR_GPSR(IP15_27_24, USB30_PWEN),
1286 PINMUX_IPSR_GPSR(IP15_27_24, USB0_PWEN_A),
1287
1288 PINMUX_IPSR_GPSR(IP15_31_28, USB30_OVC),
1289 PINMUX_IPSR_MSEL(IP15_31_28, USB0_OVC_A, SEL_USB_20_CH0_0),
1290
1291 /*
1292 * Static pins can not be muxed between different functions but
1293 * still need mark entries in the pinmux list. Add each static
1294 * pin to the list without an associated function. The sh-pfc
1295 * core will do the right thing and skip trying to mux the pin
1296 * while still applying configuration to it.
1297 */
1298 #define FM(x) PINMUX_DATA(x##_MARK, 0),
1299 PINMUX_STATIC
1300 #undef FM
1301 };
1302
1303 /*
1304 * Pins not associated with a GPIO port.
1305 */
1306 enum {
1307 GP_ASSIGN_LAST(),
1308 NOGP_ALL(),
1309 };
1310
1311 static const struct sh_pfc_pin pinmux_pins[] = {
1312 PINMUX_GPIO_GP_ALL(),
1313 PINMUX_NOGP_ALL(),
1314 };
1315
1316 /* - AUDIO CLOCK ------------------------------------------------------------ */
1317 static const unsigned int audio_clk_a_pins[] = {
1318 /* CLK A */
1319 RCAR_GP_PIN(6, 8),
1320 };
1321
1322 static const unsigned int audio_clk_a_mux[] = {
1323 AUDIO_CLKA_MARK,
1324 };
1325
1326 static const unsigned int audio_clk_b_a_pins[] = {
1327 /* CLK B_A */
1328 RCAR_GP_PIN(5, 7),
1329 };
1330
1331 static const unsigned int audio_clk_b_a_mux[] = {
1332 AUDIO_CLKB_A_MARK,
1333 };
1334
1335 static const unsigned int audio_clk_b_b_pins[] = {
1336 /* CLK B_B */
1337 RCAR_GP_PIN(6, 7),
1338 };
1339
1340 static const unsigned int audio_clk_b_b_mux[] = {
1341 AUDIO_CLKB_B_MARK,
1342 };
1343
1344 static const unsigned int audio_clk_b_c_pins[] = {
1345 /* CLK B_C */
1346 RCAR_GP_PIN(6, 13),
1347 };
1348
1349 static const unsigned int audio_clk_b_c_mux[] = {
1350 AUDIO_CLKB_C_MARK,
1351 };
1352
1353 static const unsigned int audio_clk_c_a_pins[] = {
1354 /* CLK C_A */
1355 RCAR_GP_PIN(5, 16),
1356 };
1357
1358 static const unsigned int audio_clk_c_a_mux[] = {
1359 AUDIO_CLKC_A_MARK,
1360 };
1361
1362 static const unsigned int audio_clk_c_b_pins[] = {
1363 /* CLK C_B */
1364 RCAR_GP_PIN(6, 3),
1365 };
1366
1367 static const unsigned int audio_clk_c_b_mux[] = {
1368 AUDIO_CLKC_B_MARK,
1369 };
1370
1371 static const unsigned int audio_clk_c_c_pins[] = {
1372 /* CLK C_C */
1373 RCAR_GP_PIN(6, 14),
1374 };
1375
1376 static const unsigned int audio_clk_c_c_mux[] = {
1377 AUDIO_CLKC_C_MARK,
1378 };
1379
1380 static const unsigned int audio_clkout_a_pins[] = {
1381 /* CLKOUT_A */
1382 RCAR_GP_PIN(5, 3),
1383 };
1384
1385 static const unsigned int audio_clkout_a_mux[] = {
1386 AUDIO_CLKOUT_A_MARK,
1387 };
1388
1389 static const unsigned int audio_clkout_b_pins[] = {
1390 /* CLKOUT_B */
1391 RCAR_GP_PIN(5, 13),
1392 };
1393
1394 static const unsigned int audio_clkout_b_mux[] = {
1395 AUDIO_CLKOUT_B_MARK,
1396 };
1397
1398 static const unsigned int audio_clkout1_a_pins[] = {
1399 /* CLKOUT1_A */
1400 RCAR_GP_PIN(5, 4),
1401 };
1402
1403 static const unsigned int audio_clkout1_a_mux[] = {
1404 AUDIO_CLKOUT1_A_MARK,
1405 };
1406
1407 static const unsigned int audio_clkout1_b_pins[] = {
1408 /* CLKOUT1_B */
1409 RCAR_GP_PIN(5, 5),
1410 };
1411
1412 static const unsigned int audio_clkout1_b_mux[] = {
1413 AUDIO_CLKOUT1_B_MARK,
1414 };
1415
1416 static const unsigned int audio_clkout1_c_pins[] = {
1417 /* CLKOUT1_C */
1418 RCAR_GP_PIN(6, 7),
1419 };
1420
1421 static const unsigned int audio_clkout1_c_mux[] = {
1422 AUDIO_CLKOUT1_C_MARK,
1423 };
1424
1425 static const unsigned int audio_clkout2_a_pins[] = {
1426 /* CLKOUT2_A */
1427 RCAR_GP_PIN(5, 8),
1428 };
1429
1430 static const unsigned int audio_clkout2_a_mux[] = {
1431 AUDIO_CLKOUT2_A_MARK,
1432 };
1433
1434 static const unsigned int audio_clkout2_b_pins[] = {
1435 /* CLKOUT2_B */
1436 RCAR_GP_PIN(6, 4),
1437 };
1438
1439 static const unsigned int audio_clkout2_b_mux[] = {
1440 AUDIO_CLKOUT2_B_MARK,
1441 };
1442
1443 static const unsigned int audio_clkout2_c_pins[] = {
1444 /* CLKOUT2_C */
1445 RCAR_GP_PIN(6, 15),
1446 };
1447
1448 static const unsigned int audio_clkout2_c_mux[] = {
1449 AUDIO_CLKOUT2_C_MARK,
1450 };
1451
1452 static const unsigned int audio_clkout3_a_pins[] = {
1453 /* CLKOUT3_A */
1454 RCAR_GP_PIN(5, 9),
1455 };
1456
1457 static const unsigned int audio_clkout3_a_mux[] = {
1458 AUDIO_CLKOUT3_A_MARK,
1459 };
1460
1461 static const unsigned int audio_clkout3_b_pins[] = {
1462 /* CLKOUT3_B */
1463 RCAR_GP_PIN(5, 6),
1464 };
1465
1466 static const unsigned int audio_clkout3_b_mux[] = {
1467 AUDIO_CLKOUT3_B_MARK,
1468 };
1469
1470 static const unsigned int audio_clkout3_c_pins[] = {
1471 /* CLKOUT3_C */
1472 RCAR_GP_PIN(6, 16),
1473 };
1474
1475 static const unsigned int audio_clkout3_c_mux[] = {
1476 AUDIO_CLKOUT3_C_MARK,
1477 };
1478
1479 /* - EtherAVB --------------------------------------------------------------- */
1480 static const unsigned int avb_link_pins[] = {
1481 /* AVB_LINK */
1482 RCAR_GP_PIN(2, 23),
1483 };
1484
1485 static const unsigned int avb_link_mux[] = {
1486 AVB_LINK_MARK,
1487 };
1488
1489 static const unsigned int avb_magic_pins[] = {
1490 /* AVB_MAGIC */
1491 RCAR_GP_PIN(2, 22),
1492 };
1493
1494 static const unsigned int avb_magic_mux[] = {
1495 AVB_MAGIC_MARK,
1496 };
1497
1498 static const unsigned int avb_phy_int_pins[] = {
1499 /* AVB_PHY_INT */
1500 RCAR_GP_PIN(2, 21),
1501 };
1502
1503 static const unsigned int avb_phy_int_mux[] = {
1504 AVB_PHY_INT_MARK,
1505 };
1506
1507 static const unsigned int avb_mii_pins[] = {
1508 /*
1509 * AVB_RX_CTL, AVB_RXC, AVB_RD0,
1510 * AVB_RD1, AVB_RD2, AVB_RD3,
1511 * AVB_TXCREFCLK
1512 */
1513 RCAR_GP_PIN(2, 14), RCAR_GP_PIN(2, 15), RCAR_GP_PIN(2, 16),
1514 RCAR_GP_PIN(2, 17), RCAR_GP_PIN(2, 18), RCAR_GP_PIN(2, 19),
1515 RCAR_GP_PIN(2, 20),
1516 };
1517
1518 static const unsigned int avb_mii_mux[] = {
1519 AVB_RX_CTL_MARK, AVB_RXC_MARK, AVB_RD0_MARK,
1520 AVB_RD1_MARK, AVB_RD2_MARK, AVB_RD3_MARK,
1521 AVB_TXCREFCLK_MARK,
1522 };
1523
1524 static const unsigned int avb_avtp_pps_pins[] = {
1525 /* AVB_AVTP_PPS */
1526 RCAR_GP_PIN(1, 2),
1527 };
1528
1529 static const unsigned int avb_avtp_pps_mux[] = {
1530 AVB_AVTP_PPS_MARK,
1531 };
1532
1533 static const unsigned int avb_avtp_match_pins[] = {
1534 /* AVB_AVTP_MATCH */
1535 RCAR_GP_PIN(2, 24),
1536 };
1537
1538 static const unsigned int avb_avtp_match_mux[] = {
1539 AVB_AVTP_MATCH_MARK,
1540 };
1541
1542 static const unsigned int avb_avtp_capture_pins[] = {
1543 /* AVB_AVTP_CAPTURE */
1544 RCAR_GP_PIN(2, 25),
1545 };
1546
1547 static const unsigned int avb_avtp_capture_mux[] = {
1548 AVB_AVTP_CAPTURE_MARK,
1549 };
1550
1551 /* - CAN ------------------------------------------------------------------ */
1552 static const unsigned int can0_data_pins[] = {
1553 /* TX, RX */
1554 RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 13),
1555 };
1556
1557 static const unsigned int can0_data_mux[] = {
1558 CAN0_TX_MARK, CAN0_RX_MARK,
1559 };
1560
1561 static const unsigned int can1_data_pins[] = {
1562 /* TX, RX */
1563 RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 7),
1564 };
1565
1566 static const unsigned int can1_data_mux[] = {
1567 CAN1_TX_MARK, CAN1_RX_MARK,
1568 };
1569
1570 /* - CAN Clock -------------------------------------------------------------- */
1571 static const unsigned int can_clk_pins[] = {
1572 /* CLK */
1573 RCAR_GP_PIN(0, 14),
1574 };
1575
1576 static const unsigned int can_clk_mux[] = {
1577 CAN_CLK_MARK,
1578 };
1579
1580 /* - CAN FD --------------------------------------------------------------- */
1581 static const unsigned int canfd0_data_pins[] = {
1582 /* TX, RX */
1583 RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 13),
1584 };
1585
1586 static const unsigned int canfd0_data_mux[] = {
1587 CANFD0_TX_MARK, CANFD0_RX_MARK,
1588 };
1589
1590 static const unsigned int canfd1_data_pins[] = {
1591 /* TX, RX */
1592 RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 7),
1593 };
1594
1595 static const unsigned int canfd1_data_mux[] = {
1596 CANFD1_TX_MARK, CANFD1_RX_MARK,
1597 };
1598
1599 #ifdef CONFIG_PINCTRL_PFC_R8A77990
1600 /* - DRIF0 --------------------------------------------------------------- */
1601 static const unsigned int drif0_ctrl_a_pins[] = {
1602 /* CLK, SYNC */
1603 RCAR_GP_PIN(5, 7), RCAR_GP_PIN(5, 19),
1604 };
1605
1606 static const unsigned int drif0_ctrl_a_mux[] = {
1607 RIF0_CLK_A_MARK, RIF0_SYNC_A_MARK,
1608 };
1609
1610 static const unsigned int drif0_data0_a_pins[] = {
1611 /* D0 */
1612 RCAR_GP_PIN(5, 17),
1613 };
1614
1615 static const unsigned int drif0_data0_a_mux[] = {
1616 RIF0_D0_A_MARK,
1617 };
1618
1619 static const unsigned int drif0_data1_a_pins[] = {
1620 /* D1 */
1621 RCAR_GP_PIN(5, 18),
1622 };
1623
1624 static const unsigned int drif0_data1_a_mux[] = {
1625 RIF0_D1_A_MARK,
1626 };
1627
1628 static const unsigned int drif0_ctrl_b_pins[] = {
1629 /* CLK, SYNC */
1630 RCAR_GP_PIN(3, 12), RCAR_GP_PIN(3, 15),
1631 };
1632
1633 static const unsigned int drif0_ctrl_b_mux[] = {
1634 RIF0_CLK_B_MARK, RIF0_SYNC_B_MARK,
1635 };
1636
1637 static const unsigned int drif0_data0_b_pins[] = {
1638 /* D0 */
1639 RCAR_GP_PIN(3, 13),
1640 };
1641
1642 static const unsigned int drif0_data0_b_mux[] = {
1643 RIF0_D0_B_MARK,
1644 };
1645
1646 static const unsigned int drif0_data1_b_pins[] = {
1647 /* D1 */
1648 RCAR_GP_PIN(3, 14),
1649 };
1650
1651 static const unsigned int drif0_data1_b_mux[] = {
1652 RIF0_D1_B_MARK,
1653 };
1654
1655 /* - DRIF1 --------------------------------------------------------------- */
1656 static const unsigned int drif1_ctrl_pins[] = {
1657 /* CLK, SYNC */
1658 RCAR_GP_PIN(5, 4), RCAR_GP_PIN(5, 1),
1659 };
1660
1661 static const unsigned int drif1_ctrl_mux[] = {
1662 RIF1_CLK_MARK, RIF1_SYNC_MARK,
1663 };
1664
1665 static const unsigned int drif1_data0_pins[] = {
1666 /* D0 */
1667 RCAR_GP_PIN(5, 2),
1668 };
1669
1670 static const unsigned int drif1_data0_mux[] = {
1671 RIF1_D0_MARK,
1672 };
1673
1674 static const unsigned int drif1_data1_pins[] = {
1675 /* D1 */
1676 RCAR_GP_PIN(5, 3),
1677 };
1678
1679 static const unsigned int drif1_data1_mux[] = {
1680 RIF1_D1_MARK,
1681 };
1682
1683 /* - DRIF2 --------------------------------------------------------------- */
1684 static const unsigned int drif2_ctrl_a_pins[] = {
1685 /* CLK, SYNC */
1686 RCAR_GP_PIN(2, 6), RCAR_GP_PIN(2, 7),
1687 };
1688
1689 static const unsigned int drif2_ctrl_a_mux[] = {
1690 RIF2_CLK_A_MARK, RIF2_SYNC_A_MARK,
1691 };
1692
1693 static const unsigned int drif2_data0_a_pins[] = {
1694 /* D0 */
1695 RCAR_GP_PIN(2, 8),
1696 };
1697
1698 static const unsigned int drif2_data0_a_mux[] = {
1699 RIF2_D0_A_MARK,
1700 };
1701
1702 static const unsigned int drif2_data1_a_pins[] = {
1703 /* D1 */
1704 RCAR_GP_PIN(2, 9),
1705 };
1706
1707 static const unsigned int drif2_data1_a_mux[] = {
1708 RIF2_D1_A_MARK,
1709 };
1710
1711 static const unsigned int drif2_ctrl_b_pins[] = {
1712 /* CLK, SYNC */
1713 RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5),
1714 };
1715
1716 static const unsigned int drif2_ctrl_b_mux[] = {
1717 RIF2_CLK_B_MARK, RIF2_SYNC_B_MARK,
1718 };
1719
1720 static const unsigned int drif2_data0_b_pins[] = {
1721 /* D0 */
1722 RCAR_GP_PIN(1, 6),
1723 };
1724
1725 static const unsigned int drif2_data0_b_mux[] = {
1726 RIF2_D0_B_MARK,
1727 };
1728
1729 static const unsigned int drif2_data1_b_pins[] = {
1730 /* D1 */
1731 RCAR_GP_PIN(1, 7),
1732 };
1733
1734 static const unsigned int drif2_data1_b_mux[] = {
1735 RIF2_D1_B_MARK,
1736 };
1737
1738 /* - DRIF3 --------------------------------------------------------------- */
1739 static const unsigned int drif3_ctrl_a_pins[] = {
1740 /* CLK, SYNC */
1741 RCAR_GP_PIN(2, 10), RCAR_GP_PIN(2, 11),
1742 };
1743
1744 static const unsigned int drif3_ctrl_a_mux[] = {
1745 RIF3_CLK_A_MARK, RIF3_SYNC_A_MARK,
1746 };
1747
1748 static const unsigned int drif3_data0_a_pins[] = {
1749 /* D0 */
1750 RCAR_GP_PIN(2, 12),
1751 };
1752
1753 static const unsigned int drif3_data0_a_mux[] = {
1754 RIF3_D0_A_MARK,
1755 };
1756
1757 static const unsigned int drif3_data1_a_pins[] = {
1758 /* D1 */
1759 RCAR_GP_PIN(2, 13),
1760 };
1761
1762 static const unsigned int drif3_data1_a_mux[] = {
1763 RIF3_D1_A_MARK,
1764 };
1765
1766 static const unsigned int drif3_ctrl_b_pins[] = {
1767 /* CLK, SYNC */
1768 RCAR_GP_PIN(0, 8), RCAR_GP_PIN(0, 9),
1769 };
1770
1771 static const unsigned int drif3_ctrl_b_mux[] = {
1772 RIF3_CLK_B_MARK, RIF3_SYNC_B_MARK,
1773 };
1774
1775 static const unsigned int drif3_data0_b_pins[] = {
1776 /* D0 */
1777 RCAR_GP_PIN(0, 10),
1778 };
1779
1780 static const unsigned int drif3_data0_b_mux[] = {
1781 RIF3_D0_B_MARK,
1782 };
1783
1784 static const unsigned int drif3_data1_b_pins[] = {
1785 /* D1 */
1786 RCAR_GP_PIN(0, 11),
1787 };
1788
1789 static const unsigned int drif3_data1_b_mux[] = {
1790 RIF3_D1_B_MARK,
1791 };
1792 #endif /* CONFIG_PINCTRL_PFC_R8A77990 */
1793
1794 /* - DU --------------------------------------------------------------------- */
1795 static const unsigned int du_rgb666_pins[] = {
1796 /* R[7:2], G[7:2], B[7:2] */
1797 RCAR_GP_PIN(0, 8), RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 5),
1798 RCAR_GP_PIN(0, 3), RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 0),
1799 RCAR_GP_PIN(1, 9), RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 10),
1800 RCAR_GP_PIN(1, 4), RCAR_GP_PIN(0, 15), RCAR_GP_PIN(0, 11),
1801 RCAR_GP_PIN(0, 1), RCAR_GP_PIN(1, 17), RCAR_GP_PIN(1, 16),
1802 RCAR_GP_PIN(1, 15), RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 13),
1803 };
1804 static const unsigned int du_rgb666_mux[] = {
1805 DU_DR7_MARK, DU_DR6_MARK, DU_DR5_MARK, DU_DR4_MARK,
1806 DU_DR3_MARK, DU_DR2_MARK,
1807 DU_DG7_MARK, DU_DG6_MARK, DU_DG5_MARK, DU_DG4_MARK,
1808 DU_DG3_MARK, DU_DG2_MARK,
1809 DU_DB7_MARK, DU_DB6_MARK, DU_DB5_MARK, DU_DB4_MARK,
1810 DU_DB3_MARK, DU_DB2_MARK,
1811 };
1812 static const unsigned int du_rgb888_pins[] = {
1813 /* R[7:0], G[7:0], B[7:0] */
1814 RCAR_GP_PIN(0, 8), RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 5),
1815 RCAR_GP_PIN(0, 3), RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 0),
1816 RCAR_GP_PIN(1, 22), RCAR_GP_PIN(1, 21),
1817 RCAR_GP_PIN(1, 9), RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 10),
1818 RCAR_GP_PIN(1, 4), RCAR_GP_PIN(0, 15), RCAR_GP_PIN(0, 11),
1819 RCAR_GP_PIN(0, 10), RCAR_GP_PIN(0, 9),
1820 RCAR_GP_PIN(0, 1), RCAR_GP_PIN(1, 17), RCAR_GP_PIN(1, 16),
1821 RCAR_GP_PIN(1, 15), RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 13),
1822 RCAR_GP_PIN(1, 19), RCAR_GP_PIN(1, 18),
1823 };
1824 static const unsigned int du_rgb888_mux[] = {
1825 DU_DR7_MARK, DU_DR6_MARK, DU_DR5_MARK, DU_DR4_MARK,
1826 DU_DR3_MARK, DU_DR2_MARK, DU_DR1_MARK, DU_DR0_MARK,
1827 DU_DG7_MARK, DU_DG6_MARK, DU_DG5_MARK, DU_DG4_MARK,
1828 DU_DG3_MARK, DU_DG2_MARK, DU_DG1_MARK, DU_DG0_MARK,
1829 DU_DB7_MARK, DU_DB6_MARK, DU_DB5_MARK, DU_DB4_MARK,
1830 DU_DB3_MARK, DU_DB2_MARK, DU_DB1_MARK, DU_DB0_MARK,
1831 };
1832 static const unsigned int du_clk_in_0_pins[] = {
1833 /* CLKIN0 */
1834 RCAR_GP_PIN(0, 16),
1835 };
1836 static const unsigned int du_clk_in_0_mux[] = {
1837 DU_DOTCLKIN0_MARK
1838 };
1839 static const unsigned int du_clk_in_1_pins[] = {
1840 /* CLKIN1 */
1841 RCAR_GP_PIN(1, 1),
1842 };
1843 static const unsigned int du_clk_in_1_mux[] = {
1844 DU_DOTCLKIN1_MARK
1845 };
1846 static const unsigned int du_clk_out_0_pins[] = {
1847 /* CLKOUT */
1848 RCAR_GP_PIN(1, 3),
1849 };
1850 static const unsigned int du_clk_out_0_mux[] = {
1851 DU_DOTCLKOUT0_MARK
1852 };
1853 static const unsigned int du_sync_pins[] = {
1854 /* VSYNC, HSYNC */
1855 RCAR_GP_PIN(1, 11), RCAR_GP_PIN(1, 8),
1856 };
1857 static const unsigned int du_sync_mux[] = {
1858 DU_VSYNC_MARK, DU_HSYNC_MARK
1859 };
1860 static const unsigned int du_disp_cde_pins[] = {
1861 /* DISP_CDE */
1862 RCAR_GP_PIN(1, 1),
1863 };
1864 static const unsigned int du_disp_cde_mux[] = {
1865 DU_DISP_CDE_MARK,
1866 };
1867 static const unsigned int du_cde_pins[] = {
1868 /* CDE */
1869 RCAR_GP_PIN(1, 0),
1870 };
1871 static const unsigned int du_cde_mux[] = {
1872 DU_CDE_MARK,
1873 };
1874 static const unsigned int du_disp_pins[] = {
1875 /* DISP */
1876 RCAR_GP_PIN(1, 2),
1877 };
1878 static const unsigned int du_disp_mux[] = {
1879 DU_DISP_MARK,
1880 };
1881
1882 /* - HSCIF0 --------------------------------------------------*/
1883 static const unsigned int hscif0_data_a_pins[] = {
1884 /* RX, TX */
1885 RCAR_GP_PIN(5, 8), RCAR_GP_PIN(5, 9),
1886 };
1887
1888 static const unsigned int hscif0_data_a_mux[] = {
1889 HRX0_A_MARK, HTX0_A_MARK,
1890 };
1891
1892 static const unsigned int hscif0_clk_a_pins[] = {
1893 /* SCK */
1894 RCAR_GP_PIN(5, 7),
1895 };
1896
1897 static const unsigned int hscif0_clk_a_mux[] = {
1898 HSCK0_A_MARK,
1899 };
1900
1901 static const unsigned int hscif0_ctrl_a_pins[] = {
1902 /* RTS, CTS */
1903 RCAR_GP_PIN(5, 15), RCAR_GP_PIN(5, 14),
1904 };
1905
1906 static const unsigned int hscif0_ctrl_a_mux[] = {
1907 HRTS0_N_A_MARK, HCTS0_N_A_MARK,
1908 };
1909
1910 static const unsigned int hscif0_data_b_pins[] = {
1911 /* RX, TX */
1912 RCAR_GP_PIN(6, 11), RCAR_GP_PIN(6, 12),
1913 };
1914
1915 static const unsigned int hscif0_data_b_mux[] = {
1916 HRX0_B_MARK, HTX0_B_MARK,
1917 };
1918
1919 static const unsigned int hscif0_clk_b_pins[] = {
1920 /* SCK */
1921 RCAR_GP_PIN(6, 13),
1922 };
1923
1924 static const unsigned int hscif0_clk_b_mux[] = {
1925 HSCK0_B_MARK,
1926 };
1927
1928 /* - HSCIF1 ------------------------------------------------- */
1929 static const unsigned int hscif1_data_a_pins[] = {
1930 /* RX, TX */
1931 RCAR_GP_PIN(5, 1), RCAR_GP_PIN(5, 2),
1932 };
1933
1934 static const unsigned int hscif1_data_a_mux[] = {
1935 HRX1_A_MARK, HTX1_A_MARK,
1936 };
1937
1938 static const unsigned int hscif1_clk_a_pins[] = {
1939 /* SCK */
1940 RCAR_GP_PIN(5, 0),
1941 };
1942
1943 static const unsigned int hscif1_clk_a_mux[] = {
1944 HSCK1_A_MARK,
1945 };
1946
1947 static const unsigned int hscif1_data_b_pins[] = {
1948 /* RX, TX */
1949 RCAR_GP_PIN(3, 1), RCAR_GP_PIN(3, 2),
1950 };
1951
1952 static const unsigned int hscif1_data_b_mux[] = {
1953 HRX1_B_MARK, HTX1_B_MARK,
1954 };
1955
1956 static const unsigned int hscif1_clk_b_pins[] = {
1957 /* SCK */
1958 RCAR_GP_PIN(3, 0),
1959 };
1960
1961 static const unsigned int hscif1_clk_b_mux[] = {
1962 HSCK1_B_MARK,
1963 };
1964
1965 static const unsigned int hscif1_ctrl_b_pins[] = {
1966 /* RTS, CTS */
1967 RCAR_GP_PIN(3, 4), RCAR_GP_PIN(3, 3),
1968 };
1969
1970 static const unsigned int hscif1_ctrl_b_mux[] = {
1971 HRTS1_N_B_MARK, HCTS1_N_B_MARK,
1972 };
1973
1974 /* - HSCIF2 ------------------------------------------------- */
1975 static const unsigned int hscif2_data_a_pins[] = {
1976 /* RX, TX */
1977 RCAR_GP_PIN(5, 14), RCAR_GP_PIN(5, 15),
1978 };
1979
1980 static const unsigned int hscif2_data_a_mux[] = {
1981 HRX2_A_MARK, HTX2_A_MARK,
1982 };
1983
1984 static const unsigned int hscif2_clk_a_pins[] = {
1985 /* SCK */
1986 RCAR_GP_PIN(6, 14),
1987 };
1988
1989 static const unsigned int hscif2_clk_a_mux[] = {
1990 HSCK2_A_MARK,
1991 };
1992
1993 static const unsigned int hscif2_ctrl_a_pins[] = {
1994 /* RTS, CTS */
1995 RCAR_GP_PIN(6, 16), RCAR_GP_PIN(6, 15),
1996 };
1997
1998 static const unsigned int hscif2_ctrl_a_mux[] = {
1999 HRTS2_N_A_MARK, HCTS2_N_A_MARK,
2000 };
2001
2002 static const unsigned int hscif2_data_b_pins[] = {
2003 /* RX, TX */
2004 RCAR_GP_PIN(5, 5), RCAR_GP_PIN(5, 6),
2005 };
2006
2007 static const unsigned int hscif2_data_b_mux[] = {
2008 HRX2_B_MARK, HTX2_B_MARK,
2009 };
2010
2011 /* - HSCIF3 ------------------------------------------------*/
2012 static const unsigned int hscif3_data_a_pins[] = {
2013 /* RX, TX */
2014 RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 15),
2015 };
2016
2017 static const unsigned int hscif3_data_a_mux[] = {
2018 HRX3_A_MARK, HTX3_A_MARK,
2019 };
2020
2021 static const unsigned int hscif3_data_b_pins[] = {
2022 /* RX, TX */
2023 RCAR_GP_PIN(0, 5), RCAR_GP_PIN(0, 6),
2024 };
2025
2026 static const unsigned int hscif3_data_b_mux[] = {
2027 HRX3_B_MARK, HTX3_B_MARK,
2028 };
2029
2030 static const unsigned int hscif3_clk_b_pins[] = {
2031 /* SCK */
2032 RCAR_GP_PIN(0, 4),
2033 };
2034
2035 static const unsigned int hscif3_clk_b_mux[] = {
2036 HSCK3_B_MARK,
2037 };
2038
2039 static const unsigned int hscif3_data_c_pins[] = {
2040 /* RX, TX */
2041 RCAR_GP_PIN(2, 10), RCAR_GP_PIN(2, 9),
2042 };
2043
2044 static const unsigned int hscif3_data_c_mux[] = {
2045 HRX3_C_MARK, HTX3_C_MARK,
2046 };
2047
2048 static const unsigned int hscif3_clk_c_pins[] = {
2049 /* SCK */
2050 RCAR_GP_PIN(2, 11),
2051 };
2052
2053 static const unsigned int hscif3_clk_c_mux[] = {
2054 HSCK3_C_MARK,
2055 };
2056
2057 static const unsigned int hscif3_ctrl_c_pins[] = {
2058 /* RTS, CTS */
2059 RCAR_GP_PIN(2, 13), RCAR_GP_PIN(2, 12),
2060 };
2061
2062 static const unsigned int hscif3_ctrl_c_mux[] = {
2063 HRTS3_N_C_MARK, HCTS3_N_C_MARK,
2064 };
2065
2066 static const unsigned int hscif3_data_d_pins[] = {
2067 /* RX, TX */
2068 RCAR_GP_PIN(1, 0), RCAR_GP_PIN(1, 3),
2069 };
2070
2071 static const unsigned int hscif3_data_d_mux[] = {
2072 HRX3_D_MARK, HTX3_D_MARK,
2073 };
2074
2075 static const unsigned int hscif3_data_e_pins[] = {
2076 /* RX, TX */
2077 RCAR_GP_PIN(0, 9), RCAR_GP_PIN(0, 10),
2078 };
2079
2080 static const unsigned int hscif3_data_e_mux[] = {
2081 HRX3_E_MARK, HTX3_E_MARK,
2082 };
2083
2084 static const unsigned int hscif3_ctrl_e_pins[] = {
2085 /* RTS, CTS */
2086 RCAR_GP_PIN(0, 11), RCAR_GP_PIN(0, 8),
2087 };
2088
2089 static const unsigned int hscif3_ctrl_e_mux[] = {
2090 HRTS3_N_E_MARK, HCTS3_N_E_MARK,
2091 };
2092
2093 /* - HSCIF4 -------------------------------------------------- */
2094 static const unsigned int hscif4_data_a_pins[] = {
2095 /* RX, TX */
2096 RCAR_GP_PIN(2, 4), RCAR_GP_PIN(2, 3),
2097 };
2098
2099 static const unsigned int hscif4_data_a_mux[] = {
2100 HRX4_A_MARK, HTX4_A_MARK,
2101 };
2102
2103 static const unsigned int hscif4_clk_a_pins[] = {
2104 /* SCK */
2105 RCAR_GP_PIN(2, 0),
2106 };
2107
2108 static const unsigned int hscif4_clk_a_mux[] = {
2109 HSCK4_A_MARK,
2110 };
2111
2112 static const unsigned int hscif4_ctrl_a_pins[] = {
2113 /* RTS, CTS */
2114 RCAR_GP_PIN(2, 2), RCAR_GP_PIN(2, 1),
2115 };
2116
2117 static const unsigned int hscif4_ctrl_a_mux[] = {
2118 HRTS4_N_A_MARK, HCTS4_N_A_MARK,
2119 };
2120
2121 static const unsigned int hscif4_data_b_pins[] = {
2122 /* RX, TX */
2123 RCAR_GP_PIN(2, 8), RCAR_GP_PIN(2, 7),
2124 };
2125
2126 static const unsigned int hscif4_data_b_mux[] = {
2127 HRX4_B_MARK, HTX4_B_MARK,
2128 };
2129
2130 static const unsigned int hscif4_clk_b_pins[] = {
2131 /* SCK */
2132 RCAR_GP_PIN(2, 6),
2133 };
2134
2135 static const unsigned int hscif4_clk_b_mux[] = {
2136 HSCK4_B_MARK,
2137 };
2138
2139 static const unsigned int hscif4_data_c_pins[] = {
2140 /* RX, TX */
2141 RCAR_GP_PIN(1, 8), RCAR_GP_PIN(1, 11),
2142 };
2143
2144 static const unsigned int hscif4_data_c_mux[] = {
2145 HRX4_C_MARK, HTX4_C_MARK,
2146 };
2147
2148 static const unsigned int hscif4_data_d_pins[] = {
2149 /* RX, TX */
2150 RCAR_GP_PIN(1, 13), RCAR_GP_PIN(1, 14),
2151 };
2152
2153 static const unsigned int hscif4_data_d_mux[] = {
2154 HRX4_D_MARK, HTX4_D_MARK,
2155 };
2156
2157 static const unsigned int hscif4_data_e_pins[] = {
2158 /* RX, TX */
2159 RCAR_GP_PIN(1, 18), RCAR_GP_PIN(1, 19),
2160 };
2161
2162 static const unsigned int hscif4_data_e_mux[] = {
2163 HRX4_E_MARK, HTX4_E_MARK,
2164 };
2165
2166 /* - I2C -------------------------------------------------------------------- */
2167 static const unsigned int i2c1_a_pins[] = {
2168 /* SCL, SDA */
2169 RCAR_GP_PIN(5, 8), RCAR_GP_PIN(5, 9),
2170 };
2171
2172 static const unsigned int i2c1_a_mux[] = {
2173 SCL1_A_MARK, SDA1_A_MARK,
2174 };
2175
2176 static const unsigned int i2c1_b_pins[] = {
2177 /* SCL, SDA */
2178 RCAR_GP_PIN(5, 17), RCAR_GP_PIN(5, 18),
2179 };
2180
2181 static const unsigned int i2c1_b_mux[] = {
2182 SCL1_B_MARK, SDA1_B_MARK,
2183 };
2184
2185 static const unsigned int i2c1_c_pins[] = {
2186 /* SCL, SDA */
2187 RCAR_GP_PIN(3, 0), RCAR_GP_PIN(3, 5),
2188 };
2189
2190 static const unsigned int i2c1_c_mux[] = {
2191 SCL1_C_MARK, SDA1_C_MARK,
2192 };
2193
2194 static const unsigned int i2c1_d_pins[] = {
2195 /* SCL, SDA */
2196 RCAR_GP_PIN(6, 16), RCAR_GP_PIN(6, 15),
2197 };
2198
2199 static const unsigned int i2c1_d_mux[] = {
2200 SCL1_D_MARK, SDA1_D_MARK,
2201 };
2202
2203 static const unsigned int i2c2_a_pins[] = {
2204 /* SCL, SDA */
2205 RCAR_GP_PIN(5, 4), RCAR_GP_PIN(5, 0),
2206 };
2207
2208 static const unsigned int i2c2_a_mux[] = {
2209 SCL2_A_MARK, SDA2_A_MARK,
2210 };
2211
2212 static const unsigned int i2c2_b_pins[] = {
2213 /* SCL, SDA */
2214 RCAR_GP_PIN(3, 12), RCAR_GP_PIN(3, 13),
2215 };
2216
2217 static const unsigned int i2c2_b_mux[] = {
2218 SCL2_B_MARK, SDA2_B_MARK,
2219 };
2220
2221 static const unsigned int i2c2_c_pins[] = {
2222 /* SCL, SDA */
2223 RCAR_GP_PIN(3, 4), RCAR_GP_PIN(3, 3),
2224 };
2225
2226 static const unsigned int i2c2_c_mux[] = {
2227 SCL2_C_MARK, SDA2_C_MARK,
2228 };
2229
2230 static const unsigned int i2c2_d_pins[] = {
2231 /* SCL, SDA */
2232 RCAR_GP_PIN(6, 11), RCAR_GP_PIN(6, 12),
2233 };
2234
2235 static const unsigned int i2c2_d_mux[] = {
2236 SCL2_D_MARK, SDA2_D_MARK,
2237 };
2238
2239 static const unsigned int i2c2_e_pins[] = {
2240 /* SCL, SDA */
2241 RCAR_GP_PIN(3, 5), RCAR_GP_PIN(3, 0),
2242 };
2243
2244 static const unsigned int i2c2_e_mux[] = {
2245 SCL2_E_MARK, SDA2_E_MARK,
2246 };
2247
2248 static const unsigned int i2c4_pins[] = {
2249 /* SCL, SDA */
2250 RCAR_GP_PIN(0, 16), RCAR_GP_PIN(0, 17),
2251 };
2252
2253 static const unsigned int i2c4_mux[] = {
2254 SCL4_MARK, SDA4_MARK,
2255 };
2256
2257 static const unsigned int i2c5_pins[] = {
2258 /* SCL, SDA */
2259 RCAR_GP_PIN(1, 21), RCAR_GP_PIN(1, 22),
2260 };
2261
2262 static const unsigned int i2c5_mux[] = {
2263 SCL5_MARK, SDA5_MARK,
2264 };
2265
2266 static const unsigned int i2c6_a_pins[] = {
2267 /* SCL, SDA */
2268 RCAR_GP_PIN(1, 11), RCAR_GP_PIN(1, 8),
2269 };
2270
2271 static const unsigned int i2c6_a_mux[] = {
2272 SCL6_A_MARK, SDA6_A_MARK,
2273 };
2274
2275 static const unsigned int i2c6_b_pins[] = {
2276 /* SCL, SDA */
2277 RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 1),
2278 };
2279
2280 static const unsigned int i2c6_b_mux[] = {
2281 SCL6_B_MARK, SDA6_B_MARK,
2282 };
2283
2284 static const unsigned int i2c7_a_pins[] = {
2285 /* SCL, SDA */
2286 RCAR_GP_PIN(2, 24), RCAR_GP_PIN(2, 25),
2287 };
2288
2289 static const unsigned int i2c7_a_mux[] = {
2290 SCL7_A_MARK, SDA7_A_MARK,
2291 };
2292
2293 static const unsigned int i2c7_b_pins[] = {
2294 /* SCL, SDA */
2295 RCAR_GP_PIN(0, 13), RCAR_GP_PIN(0, 14),
2296 };
2297
2298 static const unsigned int i2c7_b_mux[] = {
2299 SCL7_B_MARK, SDA7_B_MARK,
2300 };
2301
2302 /* - INTC-EX ---------------------------------------------------------------- */
2303 static const unsigned int intc_ex_irq0_pins[] = {
2304 /* IRQ0 */
2305 RCAR_GP_PIN(1, 0),
2306 };
2307 static const unsigned int intc_ex_irq0_mux[] = {
2308 IRQ0_MARK,
2309 };
2310 static const unsigned int intc_ex_irq1_pins[] = {
2311 /* IRQ1 */
2312 RCAR_GP_PIN(1, 1),
2313 };
2314 static const unsigned int intc_ex_irq1_mux[] = {
2315 IRQ1_MARK,
2316 };
2317 static const unsigned int intc_ex_irq2_pins[] = {
2318 /* IRQ2 */
2319 RCAR_GP_PIN(1, 2),
2320 };
2321 static const unsigned int intc_ex_irq2_mux[] = {
2322 IRQ2_MARK,
2323 };
2324 static const unsigned int intc_ex_irq3_pins[] = {
2325 /* IRQ3 */
2326 RCAR_GP_PIN(1, 9),
2327 };
2328 static const unsigned int intc_ex_irq3_mux[] = {
2329 IRQ3_MARK,
2330 };
2331 static const unsigned int intc_ex_irq4_pins[] = {
2332 /* IRQ4 */
2333 RCAR_GP_PIN(1, 10),
2334 };
2335 static const unsigned int intc_ex_irq4_mux[] = {
2336 IRQ4_MARK,
2337 };
2338 static const unsigned int intc_ex_irq5_pins[] = {
2339 /* IRQ5 */
2340 RCAR_GP_PIN(0, 7),
2341 };
2342 static const unsigned int intc_ex_irq5_mux[] = {
2343 IRQ5_MARK,
2344 };
2345
2346 /* - MSIOF0 ----------------------------------------------------------------- */
2347 static const unsigned int msiof0_clk_pins[] = {
2348 /* SCK */
2349 RCAR_GP_PIN(5, 10),
2350 };
2351
2352 static const unsigned int msiof0_clk_mux[] = {
2353 MSIOF0_SCK_MARK,
2354 };
2355
2356 static const unsigned int msiof0_sync_pins[] = {
2357 /* SYNC */
2358 RCAR_GP_PIN(5, 13),
2359 };
2360
2361 static const unsigned int msiof0_sync_mux[] = {
2362 MSIOF0_SYNC_MARK,
2363 };
2364
2365 static const unsigned int msiof0_ss1_pins[] = {
2366 /* SS1 */
2367 RCAR_GP_PIN(5, 14),
2368 };
2369
2370 static const unsigned int msiof0_ss1_mux[] = {
2371 MSIOF0_SS1_MARK,
2372 };
2373
2374 static const unsigned int msiof0_ss2_pins[] = {
2375 /* SS2 */
2376 RCAR_GP_PIN(5, 15),
2377 };
2378
2379 static const unsigned int msiof0_ss2_mux[] = {
2380 MSIOF0_SS2_MARK,
2381 };
2382
2383 static const unsigned int msiof0_txd_pins[] = {
2384 /* TXD */
2385 RCAR_GP_PIN(5, 12),
2386 };
2387
2388 static const unsigned int msiof0_txd_mux[] = {
2389 MSIOF0_TXD_MARK,
2390 };
2391
2392 static const unsigned int msiof0_rxd_pins[] = {
2393 /* RXD */
2394 RCAR_GP_PIN(5, 11),
2395 };
2396
2397 static const unsigned int msiof0_rxd_mux[] = {
2398 MSIOF0_RXD_MARK,
2399 };
2400
2401 /* - MSIOF1 ----------------------------------------------------------------- */
2402 static const unsigned int msiof1_clk_pins[] = {
2403 /* SCK */
2404 RCAR_GP_PIN(1, 19),
2405 };
2406
2407 static const unsigned int msiof1_clk_mux[] = {
2408 MSIOF1_SCK_MARK,
2409 };
2410
2411 static const unsigned int msiof1_sync_pins[] = {
2412 /* SYNC */
2413 RCAR_GP_PIN(1, 16),
2414 };
2415
2416 static const unsigned int msiof1_sync_mux[] = {
2417 MSIOF1_SYNC_MARK,
2418 };
2419
2420 static const unsigned int msiof1_ss1_pins[] = {
2421 /* SS1 */
2422 RCAR_GP_PIN(1, 14),
2423 };
2424
2425 static const unsigned int msiof1_ss1_mux[] = {
2426 MSIOF1_SS1_MARK,
2427 };
2428
2429 static const unsigned int msiof1_ss2_pins[] = {
2430 /* SS2 */
2431 RCAR_GP_PIN(1, 15),
2432 };
2433
2434 static const unsigned int msiof1_ss2_mux[] = {
2435 MSIOF1_SS2_MARK,
2436 };
2437
2438 static const unsigned int msiof1_txd_pins[] = {
2439 /* TXD */
2440 RCAR_GP_PIN(1, 18),
2441 };
2442
2443 static const unsigned int msiof1_txd_mux[] = {
2444 MSIOF1_TXD_MARK,
2445 };
2446
2447 static const unsigned int msiof1_rxd_pins[] = {
2448 /* RXD */
2449 RCAR_GP_PIN(1, 17),
2450 };
2451
2452 static const unsigned int msiof1_rxd_mux[] = {
2453 MSIOF1_RXD_MARK,
2454 };
2455
2456 /* - MSIOF2 ----------------------------------------------------------------- */
2457 static const unsigned int msiof2_clk_a_pins[] = {
2458 /* SCK */
2459 RCAR_GP_PIN(0, 8),
2460 };
2461
2462 static const unsigned int msiof2_clk_a_mux[] = {
2463 MSIOF2_SCK_A_MARK,
2464 };
2465
2466 static const unsigned int msiof2_sync_a_pins[] = {
2467 /* SYNC */
2468 RCAR_GP_PIN(0, 9),
2469 };
2470
2471 static const unsigned int msiof2_sync_a_mux[] = {
2472 MSIOF2_SYNC_A_MARK,
2473 };
2474
2475 static const unsigned int msiof2_ss1_a_pins[] = {
2476 /* SS1 */
2477 RCAR_GP_PIN(0, 15),
2478 };
2479
2480 static const unsigned int msiof2_ss1_a_mux[] = {
2481 MSIOF2_SS1_A_MARK,
2482 };
2483
2484 static const unsigned int msiof2_ss2_a_pins[] = {
2485 /* SS2 */
2486 RCAR_GP_PIN(0, 14),
2487 };
2488
2489 static const unsigned int msiof2_ss2_a_mux[] = {
2490 MSIOF2_SS2_A_MARK,
2491 };
2492
2493 static const unsigned int msiof2_txd_a_pins[] = {
2494 /* TXD */
2495 RCAR_GP_PIN(0, 11),
2496 };
2497
2498 static const unsigned int msiof2_txd_a_mux[] = {
2499 MSIOF2_TXD_A_MARK,
2500 };
2501
2502 static const unsigned int msiof2_rxd_a_pins[] = {
2503 /* RXD */
2504 RCAR_GP_PIN(0, 10),
2505 };
2506
2507 static const unsigned int msiof2_rxd_a_mux[] = {
2508 MSIOF2_RXD_A_MARK,
2509 };
2510
2511 static const unsigned int msiof2_clk_b_pins[] = {
2512 /* SCK */
2513 RCAR_GP_PIN(1, 13),
2514 };
2515
2516 static const unsigned int msiof2_clk_b_mux[] = {
2517 MSIOF2_SCK_B_MARK,
2518 };
2519
2520 static const unsigned int msiof2_sync_b_pins[] = {
2521 /* SYNC */
2522 RCAR_GP_PIN(1, 10),
2523 };
2524
2525 static const unsigned int msiof2_sync_b_mux[] = {
2526 MSIOF2_SYNC_B_MARK,
2527 };
2528
2529 static const unsigned int msiof2_ss1_b_pins[] = {
2530 /* SS1 */
2531 RCAR_GP_PIN(1, 16),
2532 };
2533
2534 static const unsigned int msiof2_ss1_b_mux[] = {
2535 MSIOF2_SS1_B_MARK,
2536 };
2537
2538 static const unsigned int msiof2_ss2_b_pins[] = {
2539 /* SS2 */
2540 RCAR_GP_PIN(1, 12),
2541 };
2542
2543 static const unsigned int msiof2_ss2_b_mux[] = {
2544 MSIOF2_SS2_B_MARK,
2545 };
2546
2547 static const unsigned int msiof2_txd_b_pins[] = {
2548 /* TXD */
2549 RCAR_GP_PIN(1, 15),
2550 };
2551
2552 static const unsigned int msiof2_txd_b_mux[] = {
2553 MSIOF2_TXD_B_MARK,
2554 };
2555
2556 static const unsigned int msiof2_rxd_b_pins[] = {
2557 /* RXD */
2558 RCAR_GP_PIN(1, 14),
2559 };
2560
2561 static const unsigned int msiof2_rxd_b_mux[] = {
2562 MSIOF2_RXD_B_MARK,
2563 };
2564
2565 /* - MSIOF3 ----------------------------------------------------------------- */
2566 static const unsigned int msiof3_clk_a_pins[] = {
2567 /* SCK */
2568 RCAR_GP_PIN(0, 0),
2569 };
2570
2571 static const unsigned int msiof3_clk_a_mux[] = {
2572 MSIOF3_SCK_A_MARK,
2573 };
2574
2575 static const unsigned int msiof3_sync_a_pins[] = {
2576 /* SYNC */
2577 RCAR_GP_PIN(0, 1),
2578 };
2579
2580 static const unsigned int msiof3_sync_a_mux[] = {
2581 MSIOF3_SYNC_A_MARK,
2582 };
2583
2584 static const unsigned int msiof3_ss1_a_pins[] = {
2585 /* SS1 */
2586 RCAR_GP_PIN(0, 15),
2587 };
2588
2589 static const unsigned int msiof3_ss1_a_mux[] = {
2590 MSIOF3_SS1_A_MARK,
2591 };
2592
2593 static const unsigned int msiof3_ss2_a_pins[] = {
2594 /* SS2 */
2595 RCAR_GP_PIN(0, 4),
2596 };
2597
2598 static const unsigned int msiof3_ss2_a_mux[] = {
2599 MSIOF3_SS2_A_MARK,
2600 };
2601
2602 static const unsigned int msiof3_txd_a_pins[] = {
2603 /* TXD */
2604 RCAR_GP_PIN(0, 3),
2605 };
2606
2607 static const unsigned int msiof3_txd_a_mux[] = {
2608 MSIOF3_TXD_A_MARK,
2609 };
2610
2611 static const unsigned int msiof3_rxd_a_pins[] = {
2612 /* RXD */
2613 RCAR_GP_PIN(0, 2),
2614 };
2615
2616 static const unsigned int msiof3_rxd_a_mux[] = {
2617 MSIOF3_RXD_A_MARK,
2618 };
2619
2620 static const unsigned int msiof3_clk_b_pins[] = {
2621 /* SCK */
2622 RCAR_GP_PIN(1, 5),
2623 };
2624
2625 static const unsigned int msiof3_clk_b_mux[] = {
2626 MSIOF3_SCK_B_MARK,
2627 };
2628
2629 static const unsigned int msiof3_sync_b_pins[] = {
2630 /* SYNC */
2631 RCAR_GP_PIN(1, 4),
2632 };
2633
2634 static const unsigned int msiof3_sync_b_mux[] = {
2635 MSIOF3_SYNC_B_MARK,
2636 };
2637
2638 static const unsigned int msiof3_ss1_b_pins[] = {
2639 /* SS1 */
2640 RCAR_GP_PIN(1, 0),
2641 };
2642
2643 static const unsigned int msiof3_ss1_b_mux[] = {
2644 MSIOF3_SS1_B_MARK,
2645 };
2646
2647 static const unsigned int msiof3_txd_b_pins[] = {
2648 /* TXD */
2649 RCAR_GP_PIN(1, 7),
2650 };
2651
2652 static const unsigned int msiof3_txd_b_mux[] = {
2653 MSIOF3_TXD_B_MARK,
2654 };
2655
2656 static const unsigned int msiof3_rxd_b_pins[] = {
2657 /* RXD */
2658 RCAR_GP_PIN(1, 6),
2659 };
2660
2661 static const unsigned int msiof3_rxd_b_mux[] = {
2662 MSIOF3_RXD_B_MARK,
2663 };
2664
2665 /* - PWM0 --------------------------------------------------------------------*/
2666 static const unsigned int pwm0_a_pins[] = {
2667 /* PWM */
2668 RCAR_GP_PIN(2, 22),
2669 };
2670
2671 static const unsigned int pwm0_a_mux[] = {
2672 PWM0_A_MARK,
2673 };
2674
2675 static const unsigned int pwm0_b_pins[] = {
2676 /* PWM */
2677 RCAR_GP_PIN(6, 3),
2678 };
2679
2680 static const unsigned int pwm0_b_mux[] = {
2681 PWM0_B_MARK,
2682 };
2683
2684 /* - PWM1 --------------------------------------------------------------------*/
2685 static const unsigned int pwm1_a_pins[] = {
2686 /* PWM */
2687 RCAR_GP_PIN(2, 23),
2688 };
2689
2690 static const unsigned int pwm1_a_mux[] = {
2691 PWM1_A_MARK,
2692 };
2693
2694 static const unsigned int pwm1_b_pins[] = {
2695 /* PWM */
2696 RCAR_GP_PIN(6, 4),
2697 };
2698
2699 static const unsigned int pwm1_b_mux[] = {
2700 PWM1_B_MARK,
2701 };
2702
2703 /* - PWM2 --------------------------------------------------------------------*/
2704 static const unsigned int pwm2_a_pins[] = {
2705 /* PWM */
2706 RCAR_GP_PIN(1, 0),
2707 };
2708
2709 static const unsigned int pwm2_a_mux[] = {
2710 PWM2_A_MARK,
2711 };
2712
2713 static const unsigned int pwm2_b_pins[] = {
2714 /* PWM */
2715 RCAR_GP_PIN(1, 4),
2716 };
2717
2718 static const unsigned int pwm2_b_mux[] = {
2719 PWM2_B_MARK,
2720 };
2721
2722 static const unsigned int pwm2_c_pins[] = {
2723 /* PWM */
2724 RCAR_GP_PIN(6, 5),
2725 };
2726
2727 static const unsigned int pwm2_c_mux[] = {
2728 PWM2_C_MARK,
2729 };
2730
2731 /* - PWM3 --------------------------------------------------------------------*/
2732 static const unsigned int pwm3_a_pins[] = {
2733 /* PWM */
2734 RCAR_GP_PIN(1, 1),
2735 };
2736
2737 static const unsigned int pwm3_a_mux[] = {
2738 PWM3_A_MARK,
2739 };
2740
2741 static const unsigned int pwm3_b_pins[] = {
2742 /* PWM */
2743 RCAR_GP_PIN(1, 5),
2744 };
2745
2746 static const unsigned int pwm3_b_mux[] = {
2747 PWM3_B_MARK,
2748 };
2749
2750 static const unsigned int pwm3_c_pins[] = {
2751 /* PWM */
2752 RCAR_GP_PIN(6, 6),
2753 };
2754
2755 static const unsigned int pwm3_c_mux[] = {
2756 PWM3_C_MARK,
2757 };
2758
2759 /* - PWM4 --------------------------------------------------------------------*/
2760 static const unsigned int pwm4_a_pins[] = {
2761 /* PWM */
2762 RCAR_GP_PIN(1, 3),
2763 };
2764
2765 static const unsigned int pwm4_a_mux[] = {
2766 PWM4_A_MARK,
2767 };
2768
2769 static const unsigned int pwm4_b_pins[] = {
2770 /* PWM */
2771 RCAR_GP_PIN(6, 7),
2772 };
2773
2774 static const unsigned int pwm4_b_mux[] = {
2775 PWM4_B_MARK,
2776 };
2777
2778 /* - PWM5 --------------------------------------------------------------------*/
2779 static const unsigned int pwm5_a_pins[] = {
2780 /* PWM */
2781 RCAR_GP_PIN(2, 24),
2782 };
2783
2784 static const unsigned int pwm5_a_mux[] = {
2785 PWM5_A_MARK,
2786 };
2787
2788 static const unsigned int pwm5_b_pins[] = {
2789 /* PWM */
2790 RCAR_GP_PIN(6, 10),
2791 };
2792
2793 static const unsigned int pwm5_b_mux[] = {
2794 PWM5_B_MARK,
2795 };
2796
2797 /* - PWM6 --------------------------------------------------------------------*/
2798 static const unsigned int pwm6_a_pins[] = {
2799 /* PWM */
2800 RCAR_GP_PIN(2, 25),
2801 };
2802
2803 static const unsigned int pwm6_a_mux[] = {
2804 PWM6_A_MARK,
2805 };
2806
2807 static const unsigned int pwm6_b_pins[] = {
2808 /* PWM */
2809 RCAR_GP_PIN(6, 11),
2810 };
2811
2812 static const unsigned int pwm6_b_mux[] = {
2813 PWM6_B_MARK,
2814 };
2815
2816 /* - QSPI0 ------------------------------------------------------------------ */
2817 static const unsigned int qspi0_ctrl_pins[] = {
2818 /* QSPI0_SPCLK, QSPI0_SSL */
2819 RCAR_GP_PIN(2, 0), RCAR_GP_PIN(2, 5),
2820 };
2821 static const unsigned int qspi0_ctrl_mux[] = {
2822 QSPI0_SPCLK_MARK, QSPI0_SSL_MARK,
2823 };
2824 static const unsigned int qspi0_data2_pins[] = {
2825 /* QSPI0_MOSI_IO0, QSPI0_MISO_IO1 */
2826 RCAR_GP_PIN(2, 1), RCAR_GP_PIN(2, 2),
2827 };
2828 static const unsigned int qspi0_data2_mux[] = {
2829 QSPI0_MOSI_IO0_MARK, QSPI0_MISO_IO1_MARK,
2830 };
2831 static const unsigned int qspi0_data4_pins[] = {
2832 /* QSPI0_MOSI_IO0, QSPI0_MISO_IO1 */
2833 RCAR_GP_PIN(2, 1), RCAR_GP_PIN(2, 2),
2834 /* QSPI0_IO2, QSPI0_IO3 */
2835 RCAR_GP_PIN(2, 3), RCAR_GP_PIN(2, 4),
2836 };
2837 static const unsigned int qspi0_data4_mux[] = {
2838 QSPI0_MOSI_IO0_MARK, QSPI0_MISO_IO1_MARK,
2839 QSPI0_IO2_MARK, QSPI0_IO3_MARK,
2840 };
2841 /* - QSPI1 ------------------------------------------------------------------ */
2842 static const unsigned int qspi1_ctrl_pins[] = {
2843 /* QSPI1_SPCLK, QSPI1_SSL */
2844 RCAR_GP_PIN(2, 6), RCAR_GP_PIN(2, 11),
2845 };
2846 static const unsigned int qspi1_ctrl_mux[] = {
2847 QSPI1_SPCLK_MARK, QSPI1_SSL_MARK,
2848 };
2849 static const unsigned int qspi1_data2_pins[] = {
2850 /* QSPI1_MOSI_IO0, QSPI1_MISO_IO1 */
2851 RCAR_GP_PIN(2, 7), RCAR_GP_PIN(2, 8),
2852 };
2853 static const unsigned int qspi1_data2_mux[] = {
2854 QSPI1_MOSI_IO0_MARK, QSPI1_MISO_IO1_MARK,
2855 };
2856 static const unsigned int qspi1_data4_pins[] = {
2857 /* QSPI1_MOSI_IO0, QSPI1_MISO_IO1 */
2858 RCAR_GP_PIN(2, 7), RCAR_GP_PIN(2, 8),
2859 /* QSPI1_IO2, QSPI1_IO3 */
2860 RCAR_GP_PIN(2, 9), RCAR_GP_PIN(2, 10),
2861 };
2862 static const unsigned int qspi1_data4_mux[] = {
2863 QSPI1_MOSI_IO0_MARK, QSPI1_MISO_IO1_MARK,
2864 QSPI1_IO2_MARK, QSPI1_IO3_MARK,
2865 };
2866
2867 /* - SCIF0 ------------------------------------------------------------------ */
2868 static const unsigned int scif0_data_a_pins[] = {
2869 /* RX, TX */
2870 RCAR_GP_PIN(5, 1), RCAR_GP_PIN(5, 2),
2871 };
2872
2873 static const unsigned int scif0_data_a_mux[] = {
2874 RX0_A_MARK, TX0_A_MARK,
2875 };
2876
2877 static const unsigned int scif0_clk_a_pins[] = {
2878 /* SCK */
2879 RCAR_GP_PIN(5, 0),
2880 };
2881
2882 static const unsigned int scif0_clk_a_mux[] = {
2883 SCK0_A_MARK,
2884 };
2885
2886 static const unsigned int scif0_ctrl_a_pins[] = {
2887 /* RTS, CTS */
2888 RCAR_GP_PIN(5, 4), RCAR_GP_PIN(5, 3),
2889 };
2890
2891 static const unsigned int scif0_ctrl_a_mux[] = {
2892 RTS0_N_A_MARK, CTS0_N_A_MARK,
2893 };
2894
2895 static const unsigned int scif0_data_b_pins[] = {
2896 /* RX, TX */
2897 RCAR_GP_PIN(5, 17), RCAR_GP_PIN(5, 19),
2898 };
2899
2900 static const unsigned int scif0_data_b_mux[] = {
2901 RX0_B_MARK, TX0_B_MARK,
2902 };
2903
2904 static const unsigned int scif0_clk_b_pins[] = {
2905 /* SCK */
2906 RCAR_GP_PIN(5, 18),
2907 };
2908
2909 static const unsigned int scif0_clk_b_mux[] = {
2910 SCK0_B_MARK,
2911 };
2912
2913 /* - SCIF1 ------------------------------------------------------------------ */
2914 static const unsigned int scif1_data_pins[] = {
2915 /* RX, TX */
2916 RCAR_GP_PIN(5, 5), RCAR_GP_PIN(5, 6),
2917 };
2918
2919 static const unsigned int scif1_data_mux[] = {
2920 RX1_MARK, TX1_MARK,
2921 };
2922
2923 static const unsigned int scif1_clk_pins[] = {
2924 /* SCK */
2925 RCAR_GP_PIN(5, 16),
2926 };
2927
2928 static const unsigned int scif1_clk_mux[] = {
2929 SCK1_MARK,
2930 };
2931
2932 static const unsigned int scif1_ctrl_pins[] = {
2933 /* RTS, CTS */
2934 RCAR_GP_PIN(5, 0), RCAR_GP_PIN(5, 7),
2935 };
2936
2937 static const unsigned int scif1_ctrl_mux[] = {
2938 RTS1_N_MARK, CTS1_N_MARK,
2939 };
2940
2941 /* - SCIF2 ------------------------------------------------------------------ */
2942 static const unsigned int scif2_data_a_pins[] = {
2943 /* RX, TX */
2944 RCAR_GP_PIN(5, 9), RCAR_GP_PIN(5, 8),
2945 };
2946
2947 static const unsigned int scif2_data_a_mux[] = {
2948 RX2_A_MARK, TX2_A_MARK,
2949 };
2950
2951 static const unsigned int scif2_clk_a_pins[] = {
2952 /* SCK */
2953 RCAR_GP_PIN(5, 7),
2954 };
2955
2956 static const unsigned int scif2_clk_a_mux[] = {
2957 SCK2_A_MARK,
2958 };
2959
2960 static const unsigned int scif2_data_b_pins[] = {
2961 /* RX, TX */
2962 RCAR_GP_PIN(5, 12), RCAR_GP_PIN(5, 11),
2963 };
2964
2965 static const unsigned int scif2_data_b_mux[] = {
2966 RX2_B_MARK, TX2_B_MARK,
2967 };
2968
2969 /* - SCIF3 ------------------------------------------------------------------ */
2970 static const unsigned int scif3_data_a_pins[] = {
2971 /* RX, TX */
2972 RCAR_GP_PIN(0, 5), RCAR_GP_PIN(0, 6),
2973 };
2974
2975 static const unsigned int scif3_data_a_mux[] = {
2976 RX3_A_MARK, TX3_A_MARK,
2977 };
2978
2979 static const unsigned int scif3_clk_a_pins[] = {
2980 /* SCK */
2981 RCAR_GP_PIN(0, 1),
2982 };
2983
2984 static const unsigned int scif3_clk_a_mux[] = {
2985 SCK3_A_MARK,
2986 };
2987
2988 static const unsigned int scif3_ctrl_a_pins[] = {
2989 /* RTS, CTS */
2990 RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 7),
2991 };
2992
2993 static const unsigned int scif3_ctrl_a_mux[] = {
2994 RTS3_N_A_MARK, CTS3_N_A_MARK,
2995 };
2996
2997 static const unsigned int scif3_data_b_pins[] = {
2998 /* RX, TX */
2999 RCAR_GP_PIN(1, 8), RCAR_GP_PIN(1, 11),
3000 };
3001
3002 static const unsigned int scif3_data_b_mux[] = {
3003 RX3_B_MARK, TX3_B_MARK,
3004 };
3005
3006 static const unsigned int scif3_data_c_pins[] = {
3007 /* RX, TX */
3008 RCAR_GP_PIN(2, 23), RCAR_GP_PIN(2, 22),
3009 };
3010
3011 static const unsigned int scif3_data_c_mux[] = {
3012 RX3_C_MARK, TX3_C_MARK,
3013 };
3014
3015 static const unsigned int scif3_clk_c_pins[] = {
3016 /* SCK */
3017 RCAR_GP_PIN(2, 24),
3018 };
3019
3020 static const unsigned int scif3_clk_c_mux[] = {
3021 SCK3_C_MARK,
3022 };
3023
3024 /* - SCIF4 ------------------------------------------------------------------ */
3025 static const unsigned int scif4_data_a_pins[] = {
3026 /* RX, TX */
3027 RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
3028 };
3029
3030 static const unsigned int scif4_data_a_mux[] = {
3031 RX4_A_MARK, TX4_A_MARK,
3032 };
3033
3034 static const unsigned int scif4_clk_a_pins[] = {
3035 /* SCK */
3036 RCAR_GP_PIN(1, 5),
3037 };
3038
3039 static const unsigned int scif4_clk_a_mux[] = {
3040 SCK4_A_MARK,
3041 };
3042
3043 static const unsigned int scif4_ctrl_a_pins[] = {
3044 /* RTS, CTS */
3045 RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 3),
3046 };
3047
3048 static const unsigned int scif4_ctrl_a_mux[] = {
3049 RTS4_N_A_MARK, CTS4_N_A_MARK,
3050 };
3051
3052 static const unsigned int scif4_data_b_pins[] = {
3053 /* RX, TX */
3054 RCAR_GP_PIN(0, 13), RCAR_GP_PIN(0, 12),
3055 };
3056
3057 static const unsigned int scif4_data_b_mux[] = {
3058 RX4_B_MARK, TX4_B_MARK,
3059 };
3060
3061 static const unsigned int scif4_clk_b_pins[] = {
3062 /* SCK */
3063 RCAR_GP_PIN(0, 8),
3064 };
3065
3066 static const unsigned int scif4_clk_b_mux[] = {
3067 SCK4_B_MARK,
3068 };
3069
3070 static const unsigned int scif4_data_c_pins[] = {
3071 /* RX, TX */
3072 RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3),
3073 };
3074
3075 static const unsigned int scif4_data_c_mux[] = {
3076 RX4_C_MARK, TX4_C_MARK,
3077 };
3078
3079 static const unsigned int scif4_ctrl_c_pins[] = {
3080 /* RTS, CTS */
3081 RCAR_GP_PIN(0, 1), RCAR_GP_PIN(0, 0),
3082 };
3083
3084 static const unsigned int scif4_ctrl_c_mux[] = {
3085 RTS4_N_C_MARK, CTS4_N_C_MARK,
3086 };
3087
3088 /* - SCIF5 ------------------------------------------------------------------ */
3089 static const unsigned int scif5_data_a_pins[] = {
3090 /* RX, TX */
3091 RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 9),
3092 };
3093
3094 static const unsigned int scif5_data_a_mux[] = {
3095 RX5_A_MARK, TX5_A_MARK,
3096 };
3097
3098 static const unsigned int scif5_clk_a_pins[] = {
3099 /* SCK */
3100 RCAR_GP_PIN(1, 13),
3101 };
3102
3103 static const unsigned int scif5_clk_a_mux[] = {
3104 SCK5_A_MARK,
3105 };
3106
3107 static const unsigned int scif5_data_b_pins[] = {
3108 /* RX, TX */
3109 RCAR_GP_PIN(2, 25), RCAR_GP_PIN(2, 24),
3110 };
3111
3112 static const unsigned int scif5_data_b_mux[] = {
3113 RX5_B_MARK, TX5_B_MARK,
3114 };
3115
3116 static const unsigned int scif5_data_c_pins[] = {
3117 /* RX, TX */
3118 RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3),
3119 };
3120
3121 static const unsigned int scif5_data_c_mux[] = {
3122 RX5_C_MARK, TX5_C_MARK,
3123 };
3124
3125 /* - SCIF Clock ------------------------------------------------------------- */
3126 static const unsigned int scif_clk_a_pins[] = {
3127 /* SCIF_CLK */
3128 RCAR_GP_PIN(5, 3),
3129 };
3130
3131 static const unsigned int scif_clk_a_mux[] = {
3132 SCIF_CLK_A_MARK,
3133 };
3134
3135 static const unsigned int scif_clk_b_pins[] = {
3136 /* SCIF_CLK */
3137 RCAR_GP_PIN(5, 7),
3138 };
3139
3140 static const unsigned int scif_clk_b_mux[] = {
3141 SCIF_CLK_B_MARK,
3142 };
3143
3144 /* - SDHI0 ------------------------------------------------------------------ */
3145 static const unsigned int sdhi0_data1_pins[] = {
3146 /* D0 */
3147 RCAR_GP_PIN(3, 2),
3148 };
3149
3150 static const unsigned int sdhi0_data1_mux[] = {
3151 SD0_DAT0_MARK,
3152 };
3153
3154 static const unsigned int sdhi0_data4_pins[] = {
3155 /* D[0:3] */
3156 RCAR_GP_PIN(3, 2), RCAR_GP_PIN(3, 3),
3157 RCAR_GP_PIN(3, 4), RCAR_GP_PIN(3, 5),
3158 };
3159
3160 static const unsigned int sdhi0_data4_mux[] = {
3161 SD0_DAT0_MARK, SD0_DAT1_MARK,
3162 SD0_DAT2_MARK, SD0_DAT3_MARK,
3163 };
3164
3165 static const unsigned int sdhi0_ctrl_pins[] = {
3166 /* CLK, CMD */
3167 RCAR_GP_PIN(3, 0), RCAR_GP_PIN(3, 1),
3168 };
3169
3170 static const unsigned int sdhi0_ctrl_mux[] = {
3171 SD0_CLK_MARK, SD0_CMD_MARK,
3172 };
3173
3174 static const unsigned int sdhi0_cd_pins[] = {
3175 /* CD */
3176 RCAR_GP_PIN(3, 12),
3177 };
3178
3179 static const unsigned int sdhi0_cd_mux[] = {
3180 SD0_CD_MARK,
3181 };
3182
3183 static const unsigned int sdhi0_wp_pins[] = {
3184 /* WP */
3185 RCAR_GP_PIN(3, 13),
3186 };
3187
3188 static const unsigned int sdhi0_wp_mux[] = {
3189 SD0_WP_MARK,
3190 };
3191
3192 /* - SDHI1 ------------------------------------------------------------------ */
3193 static const unsigned int sdhi1_data1_pins[] = {
3194 /* D0 */
3195 RCAR_GP_PIN(3, 8),
3196 };
3197
3198 static const unsigned int sdhi1_data1_mux[] = {
3199 SD1_DAT0_MARK,
3200 };
3201
3202 static const unsigned int sdhi1_data4_pins[] = {
3203 /* D[0:3] */
3204 RCAR_GP_PIN(3, 8), RCAR_GP_PIN(3, 9),
3205 RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11),
3206 };
3207
3208 static const unsigned int sdhi1_data4_mux[] = {
3209 SD1_DAT0_MARK, SD1_DAT1_MARK,
3210 SD1_DAT2_MARK, SD1_DAT3_MARK,
3211 };
3212
3213 static const unsigned int sdhi1_ctrl_pins[] = {
3214 /* CLK, CMD */
3215 RCAR_GP_PIN(3, 6), RCAR_GP_PIN(3, 7),
3216 };
3217
3218 static const unsigned int sdhi1_ctrl_mux[] = {
3219 SD1_CLK_MARK, SD1_CMD_MARK,
3220 };
3221
3222 static const unsigned int sdhi1_cd_pins[] = {
3223 /* CD */
3224 RCAR_GP_PIN(3, 14),
3225 };
3226
3227 static const unsigned int sdhi1_cd_mux[] = {
3228 SD1_CD_MARK,
3229 };
3230
3231 static const unsigned int sdhi1_wp_pins[] = {
3232 /* WP */
3233 RCAR_GP_PIN(3, 15),
3234 };
3235
3236 static const unsigned int sdhi1_wp_mux[] = {
3237 SD1_WP_MARK,
3238 };
3239
3240 /* - SDHI3 ------------------------------------------------------------------ */
3241 static const unsigned int sdhi3_data1_pins[] = {
3242 /* D0 */
3243 RCAR_GP_PIN(4, 2),
3244 };
3245
3246 static const unsigned int sdhi3_data1_mux[] = {
3247 SD3_DAT0_MARK,
3248 };
3249
3250 static const unsigned int sdhi3_data4_pins[] = {
3251 /* D[0:3] */
3252 RCAR_GP_PIN(4, 2), RCAR_GP_PIN(4, 3),
3253 RCAR_GP_PIN(4, 4), RCAR_GP_PIN(4, 5),
3254 };
3255
3256 static const unsigned int sdhi3_data4_mux[] = {
3257 SD3_DAT0_MARK, SD3_DAT1_MARK,
3258 SD3_DAT2_MARK, SD3_DAT3_MARK,
3259 };
3260
3261 static const unsigned int sdhi3_data8_pins[] = {
3262 /* D[0:7] */
3263 RCAR_GP_PIN(4, 2), RCAR_GP_PIN(4, 3),
3264 RCAR_GP_PIN(4, 4), RCAR_GP_PIN(4, 5),
3265 RCAR_GP_PIN(4, 6), RCAR_GP_PIN(4, 7),
3266 RCAR_GP_PIN(4, 8), RCAR_GP_PIN(4, 9),
3267 };
3268
3269 static const unsigned int sdhi3_data8_mux[] = {
3270 SD3_DAT0_MARK, SD3_DAT1_MARK,
3271 SD3_DAT2_MARK, SD3_DAT3_MARK,
3272 SD3_DAT4_MARK, SD3_DAT5_MARK,
3273 SD3_DAT6_MARK, SD3_DAT7_MARK,
3274 };
3275
3276 static const unsigned int sdhi3_ctrl_pins[] = {
3277 /* CLK, CMD */
3278 RCAR_GP_PIN(4, 0), RCAR_GP_PIN(4, 1),
3279 };
3280
3281 static const unsigned int sdhi3_ctrl_mux[] = {
3282 SD3_CLK_MARK, SD3_CMD_MARK,
3283 };
3284
3285 static const unsigned int sdhi3_cd_pins[] = {
3286 /* CD */
3287 RCAR_GP_PIN(3, 12),
3288 };
3289
3290 static const unsigned int sdhi3_cd_mux[] = {
3291 SD3_CD_MARK,
3292 };
3293
3294 static const unsigned int sdhi3_wp_pins[] = {
3295 /* WP */
3296 RCAR_GP_PIN(3, 13),
3297 };
3298
3299 static const unsigned int sdhi3_wp_mux[] = {
3300 SD3_WP_MARK,
3301 };
3302
3303 static const unsigned int sdhi3_ds_pins[] = {
3304 /* DS */
3305 RCAR_GP_PIN(4, 10),
3306 };
3307
3308 static const unsigned int sdhi3_ds_mux[] = {
3309 SD3_DS_MARK,
3310 };
3311
3312 /* - SSI -------------------------------------------------------------------- */
3313 static const unsigned int ssi0_data_pins[] = {
3314 /* SDATA */
3315 RCAR_GP_PIN(6, 2),
3316 };
3317
3318 static const unsigned int ssi0_data_mux[] = {
3319 SSI_SDATA0_MARK,
3320 };
3321
3322 static const unsigned int ssi01239_ctrl_pins[] = {
3323 /* SCK, WS */
3324 RCAR_GP_PIN(6, 0), RCAR_GP_PIN(6, 1),
3325 };
3326
3327 static const unsigned int ssi01239_ctrl_mux[] = {
3328 SSI_SCK01239_MARK, SSI_WS01239_MARK,
3329 };
3330
3331 static const unsigned int ssi1_data_pins[] = {
3332 /* SDATA */
3333 RCAR_GP_PIN(6, 3),
3334 };
3335
3336 static const unsigned int ssi1_data_mux[] = {
3337 SSI_SDATA1_MARK,
3338 };
3339
3340 static const unsigned int ssi1_ctrl_pins[] = {
3341 /* SCK, WS */
3342 RCAR_GP_PIN(3, 14), RCAR_GP_PIN(3, 15),
3343 };
3344
3345 static const unsigned int ssi1_ctrl_mux[] = {
3346 SSI_SCK1_MARK, SSI_WS1_MARK,
3347 };
3348
3349 static const unsigned int ssi2_data_pins[] = {
3350 /* SDATA */
3351 RCAR_GP_PIN(6, 4),
3352 };
3353
3354 static const unsigned int ssi2_data_mux[] = {
3355 SSI_SDATA2_MARK,
3356 };
3357
3358 static const unsigned int ssi2_ctrl_a_pins[] = {
3359 /* SCK, WS */
3360 RCAR_GP_PIN(5, 1), RCAR_GP_PIN(5, 2),
3361 };
3362
3363 static const unsigned int ssi2_ctrl_a_mux[] = {
3364 SSI_SCK2_A_MARK, SSI_WS2_A_MARK,
3365 };
3366
3367 static const unsigned int ssi2_ctrl_b_pins[] = {
3368 /* SCK, WS */
3369 RCAR_GP_PIN(3, 12), RCAR_GP_PIN(3, 13),
3370 };
3371
3372 static const unsigned int ssi2_ctrl_b_mux[] = {
3373 SSI_SCK2_B_MARK, SSI_WS2_B_MARK,
3374 };
3375
3376 static const unsigned int ssi3_data_pins[] = {
3377 /* SDATA */
3378 RCAR_GP_PIN(6, 7),
3379 };
3380
3381 static const unsigned int ssi3_data_mux[] = {
3382 SSI_SDATA3_MARK,
3383 };
3384
3385 static const unsigned int ssi349_ctrl_pins[] = {
3386 /* SCK, WS */
3387 RCAR_GP_PIN(6, 5), RCAR_GP_PIN(6, 6),
3388 };
3389
3390 static const unsigned int ssi349_ctrl_mux[] = {
3391 SSI_SCK349_MARK, SSI_WS349_MARK,
3392 };
3393
3394 static const unsigned int ssi4_data_pins[] = {
3395 /* SDATA */
3396 RCAR_GP_PIN(6, 10),
3397 };
3398
3399 static const unsigned int ssi4_data_mux[] = {
3400 SSI_SDATA4_MARK,
3401 };
3402
3403 static const unsigned int ssi4_ctrl_pins[] = {
3404 /* SCK, WS */
3405 RCAR_GP_PIN(5, 14), RCAR_GP_PIN(5, 15),
3406 };
3407
3408 static const unsigned int ssi4_ctrl_mux[] = {
3409 SSI_SCK4_MARK, SSI_WS4_MARK,
3410 };
3411
3412 static const unsigned int ssi5_data_pins[] = {
3413 /* SDATA */
3414 RCAR_GP_PIN(6, 13),
3415 };
3416
3417 static const unsigned int ssi5_data_mux[] = {
3418 SSI_SDATA5_MARK,
3419 };
3420
3421 static const unsigned int ssi5_ctrl_pins[] = {
3422 /* SCK, WS */
3423 RCAR_GP_PIN(6, 11), RCAR_GP_PIN(6, 12),
3424 };
3425
3426 static const unsigned int ssi5_ctrl_mux[] = {
3427 SSI_SCK5_MARK, SSI_WS5_MARK,
3428 };
3429
3430 static const unsigned int ssi6_data_pins[] = {
3431 /* SDATA */
3432 RCAR_GP_PIN(6, 16),
3433 };
3434
3435 static const unsigned int ssi6_data_mux[] = {
3436 SSI_SDATA6_MARK,
3437 };
3438
3439 static const unsigned int ssi6_ctrl_pins[] = {
3440 /* SCK, WS */
3441 RCAR_GP_PIN(6, 14), RCAR_GP_PIN(6, 15),
3442 };
3443
3444 static const unsigned int ssi6_ctrl_mux[] = {
3445 SSI_SCK6_MARK, SSI_WS6_MARK,
3446 };
3447
3448 static const unsigned int ssi7_data_pins[] = {
3449 /* SDATA */
3450 RCAR_GP_PIN(5, 12),
3451 };
3452
3453 static const unsigned int ssi7_data_mux[] = {
3454 SSI_SDATA7_MARK,
3455 };
3456
3457 static const unsigned int ssi78_ctrl_pins[] = {
3458 /* SCK, WS */
3459 RCAR_GP_PIN(5, 10), RCAR_GP_PIN(5, 11),
3460 };
3461
3462 static const unsigned int ssi78_ctrl_mux[] = {
3463 SSI_SCK78_MARK, SSI_WS78_MARK,
3464 };
3465
3466 static const unsigned int ssi8_data_pins[] = {
3467 /* SDATA */
3468 RCAR_GP_PIN(5, 13),
3469 };
3470
3471 static const unsigned int ssi8_data_mux[] = {
3472 SSI_SDATA8_MARK,
3473 };
3474
3475 static const unsigned int ssi9_data_pins[] = {
3476 /* SDATA */
3477 RCAR_GP_PIN(5, 16),
3478 };
3479
3480 static const unsigned int ssi9_data_mux[] = {
3481 SSI_SDATA9_MARK,
3482 };
3483
3484 static const unsigned int ssi9_ctrl_a_pins[] = {
3485 /* SCK, WS */
3486 RCAR_GP_PIN(6, 4), RCAR_GP_PIN(6, 10),
3487 };
3488
3489 static const unsigned int ssi9_ctrl_a_mux[] = {
3490 SSI_SCK9_A_MARK, SSI_WS9_A_MARK,
3491 };
3492
3493 static const unsigned int ssi9_ctrl_b_pins[] = {
3494 /* SCK, WS */
3495 RCAR_GP_PIN(5, 5), RCAR_GP_PIN(5, 6),
3496 };
3497
3498 static const unsigned int ssi9_ctrl_b_mux[] = {
3499 SSI_SCK9_B_MARK, SSI_WS9_B_MARK,
3500 };
3501
3502 /* - TMU -------------------------------------------------------------------- */
3503 static const unsigned int tmu_tclk1_a_pins[] = {
3504 /* TCLK */
3505 RCAR_GP_PIN(3, 12),
3506 };
3507
3508 static const unsigned int tmu_tclk1_a_mux[] = {
3509 TCLK1_A_MARK,
3510 };
3511
3512 static const unsigned int tmu_tclk1_b_pins[] = {
3513 /* TCLK */
3514 RCAR_GP_PIN(5, 17),
3515 };
3516
3517 static const unsigned int tmu_tclk1_b_mux[] = {
3518 TCLK1_B_MARK,
3519 };
3520
3521 static const unsigned int tmu_tclk2_a_pins[] = {
3522 /* TCLK */
3523 RCAR_GP_PIN(3, 13),
3524 };
3525
3526 static const unsigned int tmu_tclk2_a_mux[] = {
3527 TCLK2_A_MARK,
3528 };
3529
3530 static const unsigned int tmu_tclk2_b_pins[] = {
3531 /* TCLK */
3532 RCAR_GP_PIN(5, 18),
3533 };
3534
3535 static const unsigned int tmu_tclk2_b_mux[] = {
3536 TCLK2_B_MARK,
3537 };
3538
3539 /* - USB0 ------------------------------------------------------------------- */
3540 static const unsigned int usb0_a_pins[] = {
3541 /* PWEN, OVC */
3542 RCAR_GP_PIN(6, 17), RCAR_GP_PIN(6, 9),
3543 };
3544
3545 static const unsigned int usb0_a_mux[] = {
3546 USB0_PWEN_A_MARK, USB0_OVC_A_MARK,
3547 };
3548
3549 static const unsigned int usb0_b_pins[] = {
3550 /* PWEN, OVC */
3551 RCAR_GP_PIN(6, 11), RCAR_GP_PIN(6, 12),
3552 };
3553
3554 static const unsigned int usb0_b_mux[] = {
3555 USB0_PWEN_B_MARK, USB0_OVC_B_MARK,
3556 };
3557
3558 static const unsigned int usb0_id_pins[] = {
3559 /* ID */
3560 RCAR_GP_PIN(5, 0)
3561 };
3562
3563 static const unsigned int usb0_id_mux[] = {
3564 USB0_ID_MARK,
3565 };
3566
3567 /* - USB30 ------------------------------------------------------------------ */
3568 static const unsigned int usb30_pins[] = {
3569 /* PWEN, OVC */
3570 RCAR_GP_PIN(6, 17), RCAR_GP_PIN(6, 9),
3571 };
3572
3573 static const unsigned int usb30_mux[] = {
3574 USB30_PWEN_MARK, USB30_OVC_MARK,
3575 };
3576
3577 static const unsigned int usb30_id_pins[] = {
3578 /* ID */
3579 RCAR_GP_PIN(5, 0),
3580 };
3581
3582 static const unsigned int usb30_id_mux[] = {
3583 USB3HS0_ID_MARK,
3584 };
3585
3586 /* - VIN4 ------------------------------------------------------------------- */
3587 static const unsigned int vin4_data18_a_pins[] = {
3588 RCAR_GP_PIN(2, 8), RCAR_GP_PIN(2, 9),
3589 RCAR_GP_PIN(2, 10), RCAR_GP_PIN(2, 11),
3590 RCAR_GP_PIN(2, 12), RCAR_GP_PIN(2, 13),
3591 RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
3592 RCAR_GP_PIN(1, 3), RCAR_GP_PIN(1, 10),
3593 RCAR_GP_PIN(1, 13), RCAR_GP_PIN(1, 14),
3594 RCAR_GP_PIN(1, 15), RCAR_GP_PIN(1, 16),
3595 RCAR_GP_PIN(1, 17), RCAR_GP_PIN(1, 18),
3596 RCAR_GP_PIN(1, 19), RCAR_GP_PIN(0, 1),
3597 };
3598
3599 static const unsigned int vin4_data18_a_mux[] = {
3600 VI4_DATA2_A_MARK, VI4_DATA3_A_MARK,
3601 VI4_DATA4_A_MARK, VI4_DATA5_A_MARK,
3602 VI4_DATA6_A_MARK, VI4_DATA7_A_MARK,
3603 VI4_DATA10_MARK, VI4_DATA11_MARK,
3604 VI4_DATA12_MARK, VI4_DATA13_MARK,
3605 VI4_DATA14_MARK, VI4_DATA15_MARK,
3606 VI4_DATA18_MARK, VI4_DATA19_MARK,
3607 VI4_DATA20_MARK, VI4_DATA21_MARK,
3608 VI4_DATA22_MARK, VI4_DATA23_MARK,
3609 };
3610
3611 static const union vin_data vin4_data_a_pins = {
3612 .data24 = {
3613 RCAR_GP_PIN(2, 6), RCAR_GP_PIN(2, 7),
3614 RCAR_GP_PIN(2, 8), RCAR_GP_PIN(2, 9),
3615 RCAR_GP_PIN(2, 10), RCAR_GP_PIN(2, 11),
3616 RCAR_GP_PIN(2, 12), RCAR_GP_PIN(2, 13),
3617 RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5),
3618 RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
3619 RCAR_GP_PIN(1, 3), RCAR_GP_PIN(1, 10),
3620 RCAR_GP_PIN(1, 13), RCAR_GP_PIN(1, 14),
3621 RCAR_GP_PIN(1, 9), RCAR_GP_PIN(1, 12),
3622 RCAR_GP_PIN(1, 15), RCAR_GP_PIN(1, 16),
3623 RCAR_GP_PIN(1, 17), RCAR_GP_PIN(1, 18),
3624 RCAR_GP_PIN(1, 19), RCAR_GP_PIN(0, 1),
3625 },
3626 };
3627
3628 static const union vin_data vin4_data_a_mux = {
3629 .data24 = {
3630 VI4_DATA0_A_MARK, VI4_DATA1_A_MARK,
3631 VI4_DATA2_A_MARK, VI4_DATA3_A_MARK,
3632 VI4_DATA4_A_MARK, VI4_DATA5_A_MARK,
3633 VI4_DATA6_A_MARK, VI4_DATA7_A_MARK,
3634 VI4_DATA8_MARK, VI4_DATA9_MARK,
3635 VI4_DATA10_MARK, VI4_DATA11_MARK,
3636 VI4_DATA12_MARK, VI4_DATA13_MARK,
3637 VI4_DATA14_MARK, VI4_DATA15_MARK,
3638 VI4_DATA16_MARK, VI4_DATA17_MARK,
3639 VI4_DATA18_MARK, VI4_DATA19_MARK,
3640 VI4_DATA20_MARK, VI4_DATA21_MARK,
3641 VI4_DATA22_MARK, VI4_DATA23_MARK,
3642 },
3643 };
3644
3645 static const unsigned int vin4_data18_b_pins[] = {
3646 RCAR_GP_PIN(1, 21), RCAR_GP_PIN(1, 22),
3647 RCAR_GP_PIN(0, 5), RCAR_GP_PIN(0, 6),
3648 RCAR_GP_PIN(0, 16), RCAR_GP_PIN(0, 17),
3649 RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
3650 RCAR_GP_PIN(1, 3), RCAR_GP_PIN(1, 10),
3651 RCAR_GP_PIN(1, 13), RCAR_GP_PIN(1, 14),
3652 RCAR_GP_PIN(1, 15), RCAR_GP_PIN(1, 16),
3653 RCAR_GP_PIN(1, 17), RCAR_GP_PIN(1, 18),
3654 RCAR_GP_PIN(1, 19), RCAR_GP_PIN(0, 1),
3655 };
3656
3657 static const unsigned int vin4_data18_b_mux[] = {
3658 VI4_DATA2_B_MARK, VI4_DATA3_B_MARK,
3659 VI4_DATA4_B_MARK, VI4_DATA5_B_MARK,
3660 VI4_DATA6_B_MARK, VI4_DATA7_B_MARK,
3661 VI4_DATA10_MARK, VI4_DATA11_MARK,
3662 VI4_DATA12_MARK, VI4_DATA13_MARK,
3663 VI4_DATA14_MARK, VI4_DATA15_MARK,
3664 VI4_DATA18_MARK, VI4_DATA19_MARK,
3665 VI4_DATA20_MARK, VI4_DATA21_MARK,
3666 VI4_DATA22_MARK, VI4_DATA23_MARK,
3667 };
3668
3669 static const union vin_data vin4_data_b_pins = {
3670 .data24 = {
3671 RCAR_GP_PIN(1, 8), RCAR_GP_PIN(1, 11),
3672 RCAR_GP_PIN(1, 21), RCAR_GP_PIN(1, 22),
3673 RCAR_GP_PIN(0, 5), RCAR_GP_PIN(0, 6),
3674 RCAR_GP_PIN(0, 16), RCAR_GP_PIN(0, 17),
3675 RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5),
3676 RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
3677 RCAR_GP_PIN(1, 3), RCAR_GP_PIN(1, 10),
3678 RCAR_GP_PIN(1, 13), RCAR_GP_PIN(1, 14),
3679 RCAR_GP_PIN(1, 9), RCAR_GP_PIN(1, 12),
3680 RCAR_GP_PIN(1, 15), RCAR_GP_PIN(1, 16),
3681 RCAR_GP_PIN(1, 17), RCAR_GP_PIN(1, 18),
3682 RCAR_GP_PIN(1, 19), RCAR_GP_PIN(0, 1),
3683 },
3684 };
3685
3686 static const union vin_data vin4_data_b_mux = {
3687 .data24 = {
3688 VI4_DATA0_B_MARK, VI4_DATA1_B_MARK,
3689 VI4_DATA2_B_MARK, VI4_DATA3_B_MARK,
3690 VI4_DATA4_B_MARK, VI4_DATA5_B_MARK,
3691 VI4_DATA6_B_MARK, VI4_DATA7_B_MARK,
3692 VI4_DATA8_MARK, VI4_DATA9_MARK,
3693 VI4_DATA10_MARK, VI4_DATA11_MARK,
3694 VI4_DATA12_MARK, VI4_DATA13_MARK,
3695 VI4_DATA14_MARK, VI4_DATA15_MARK,
3696 VI4_DATA16_MARK, VI4_DATA17_MARK,
3697 VI4_DATA18_MARK, VI4_DATA19_MARK,
3698 VI4_DATA20_MARK, VI4_DATA21_MARK,
3699 VI4_DATA22_MARK, VI4_DATA23_MARK,
3700 },
3701 };
3702
3703 static const unsigned int vin4_sync_pins[] = {
3704 /* HSYNC, VSYNC */
3705 RCAR_GP_PIN(2, 25), RCAR_GP_PIN(2, 24),
3706 };
3707
3708 static const unsigned int vin4_sync_mux[] = {
3709 VI4_HSYNC_N_MARK, VI4_VSYNC_N_MARK,
3710 };
3711
3712 static const unsigned int vin4_field_pins[] = {
3713 RCAR_GP_PIN(2, 23),
3714 };
3715
3716 static const unsigned int vin4_field_mux[] = {
3717 VI4_FIELD_MARK,
3718 };
3719
3720 static const unsigned int vin4_clkenb_pins[] = {
3721 RCAR_GP_PIN(1, 2),
3722 };
3723
3724 static const unsigned int vin4_clkenb_mux[] = {
3725 VI4_CLKENB_MARK,
3726 };
3727
3728 static const unsigned int vin4_clk_pins[] = {
3729 RCAR_GP_PIN(2, 22),
3730 };
3731
3732 static const unsigned int vin4_clk_mux[] = {
3733 VI4_CLK_MARK,
3734 };
3735
3736 /* - VIN5 ------------------------------------------------------------------- */
3737 static const union vin_data16 vin5_data_a_pins = {
3738 .data16 = {
3739 RCAR_GP_PIN(1, 1), RCAR_GP_PIN(1, 2),
3740 RCAR_GP_PIN(1, 19), RCAR_GP_PIN(1, 12),
3741 RCAR_GP_PIN(1, 15), RCAR_GP_PIN(1, 16),
3742 RCAR_GP_PIN(1, 17), RCAR_GP_PIN(1, 18),
3743 RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 13),
3744 RCAR_GP_PIN(0, 9), RCAR_GP_PIN(0, 11),
3745 RCAR_GP_PIN(0, 8), RCAR_GP_PIN(0, 10),
3746 RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3),
3747 },
3748 };
3749
3750 static const union vin_data16 vin5_data_a_mux = {
3751 .data16 = {
3752 VI5_DATA0_A_MARK, VI5_DATA1_A_MARK,
3753 VI5_DATA2_A_MARK, VI5_DATA3_A_MARK,
3754 VI5_DATA4_A_MARK, VI5_DATA5_A_MARK,
3755 VI5_DATA6_A_MARK, VI5_DATA7_A_MARK,
3756 VI5_DATA8_A_MARK, VI5_DATA9_A_MARK,
3757 VI5_DATA10_A_MARK, VI5_DATA11_A_MARK,
3758 VI5_DATA12_A_MARK, VI5_DATA13_A_MARK,
3759 VI5_DATA14_A_MARK, VI5_DATA15_A_MARK,
3760 },
3761 };
3762
3763 static const unsigned int vin5_data8_b_pins[] = {
3764 RCAR_GP_PIN(2, 23), RCAR_GP_PIN(0, 4),
3765 RCAR_GP_PIN(0, 7), RCAR_GP_PIN(0, 12),
3766 RCAR_GP_PIN(0, 13), RCAR_GP_PIN(0, 14),
3767 RCAR_GP_PIN(0, 16), RCAR_GP_PIN(0, 17),
3768 };
3769
3770 static const unsigned int vin5_data8_b_mux[] = {
3771 VI5_DATA0_B_MARK, VI5_DATA1_B_MARK,
3772 VI5_DATA2_B_MARK, VI5_DATA3_B_MARK,
3773 VI5_DATA4_B_MARK, VI5_DATA5_B_MARK,
3774 VI5_DATA6_B_MARK, VI5_DATA7_B_MARK,
3775 };
3776
3777 static const unsigned int vin5_sync_a_pins[] = {
3778 /* HSYNC_N, VSYNC_N */
3779 RCAR_GP_PIN(1, 8), RCAR_GP_PIN(1, 9),
3780 };
3781
3782 static const unsigned int vin5_sync_a_mux[] = {
3783 VI5_HSYNC_N_A_MARK, VI5_VSYNC_N_A_MARK,
3784 };
3785
3786 static const unsigned int vin5_field_a_pins[] = {
3787 RCAR_GP_PIN(1, 10),
3788 };
3789
3790 static const unsigned int vin5_field_a_mux[] = {
3791 VI5_FIELD_A_MARK,
3792 };
3793
3794 static const unsigned int vin5_clkenb_a_pins[] = {
3795 RCAR_GP_PIN(0, 1),
3796 };
3797
3798 static const unsigned int vin5_clkenb_a_mux[] = {
3799 VI5_CLKENB_A_MARK,
3800 };
3801
3802 static const unsigned int vin5_clk_a_pins[] = {
3803 RCAR_GP_PIN(1, 0),
3804 };
3805
3806 static const unsigned int vin5_clk_a_mux[] = {
3807 VI5_CLK_A_MARK,
3808 };
3809
3810 static const unsigned int vin5_clk_b_pins[] = {
3811 RCAR_GP_PIN(2, 22),
3812 };
3813
3814 static const unsigned int vin5_clk_b_mux[] = {
3815 VI5_CLK_B_MARK,
3816 };
3817
3818 static const struct {
3819 struct sh_pfc_pin_group common[253];
3820 #ifdef CONFIG_PINCTRL_PFC_R8A77990
3821 struct sh_pfc_pin_group automotive[21];
3822 #endif
3823 } pinmux_groups = {
3824 .common = {
3825 SH_PFC_PIN_GROUP(audio_clk_a),
3826 SH_PFC_PIN_GROUP(audio_clk_b_a),
3827 SH_PFC_PIN_GROUP(audio_clk_b_b),
3828 SH_PFC_PIN_GROUP(audio_clk_b_c),
3829 SH_PFC_PIN_GROUP(audio_clk_c_a),
3830 SH_PFC_PIN_GROUP(audio_clk_c_b),
3831 SH_PFC_PIN_GROUP(audio_clk_c_c),
3832 SH_PFC_PIN_GROUP(audio_clkout_a),
3833 SH_PFC_PIN_GROUP(audio_clkout_b),
3834 SH_PFC_PIN_GROUP(audio_clkout1_a),
3835 SH_PFC_PIN_GROUP(audio_clkout1_b),
3836 SH_PFC_PIN_GROUP(audio_clkout1_c),
3837 SH_PFC_PIN_GROUP(audio_clkout2_a),
3838 SH_PFC_PIN_GROUP(audio_clkout2_b),
3839 SH_PFC_PIN_GROUP(audio_clkout2_c),
3840 SH_PFC_PIN_GROUP(audio_clkout3_a),
3841 SH_PFC_PIN_GROUP(audio_clkout3_b),
3842 SH_PFC_PIN_GROUP(audio_clkout3_c),
3843 SH_PFC_PIN_GROUP(avb_link),
3844 SH_PFC_PIN_GROUP(avb_magic),
3845 SH_PFC_PIN_GROUP(avb_phy_int),
3846 SH_PFC_PIN_GROUP(avb_mii),
3847 SH_PFC_PIN_GROUP(avb_avtp_pps),
3848 SH_PFC_PIN_GROUP(avb_avtp_match),
3849 SH_PFC_PIN_GROUP(avb_avtp_capture),
3850 SH_PFC_PIN_GROUP(can0_data),
3851 SH_PFC_PIN_GROUP(can1_data),
3852 SH_PFC_PIN_GROUP(can_clk),
3853 SH_PFC_PIN_GROUP(canfd0_data),
3854 SH_PFC_PIN_GROUP(canfd1_data),
3855 SH_PFC_PIN_GROUP(du_rgb666),
3856 SH_PFC_PIN_GROUP(du_rgb888),
3857 SH_PFC_PIN_GROUP(du_clk_in_0),
3858 SH_PFC_PIN_GROUP(du_clk_in_1),
3859 SH_PFC_PIN_GROUP(du_clk_out_0),
3860 SH_PFC_PIN_GROUP(du_sync),
3861 SH_PFC_PIN_GROUP(du_disp_cde),
3862 SH_PFC_PIN_GROUP(du_cde),
3863 SH_PFC_PIN_GROUP(du_disp),
3864 SH_PFC_PIN_GROUP(hscif0_data_a),
3865 SH_PFC_PIN_GROUP(hscif0_clk_a),
3866 SH_PFC_PIN_GROUP(hscif0_ctrl_a),
3867 SH_PFC_PIN_GROUP(hscif0_data_b),
3868 SH_PFC_PIN_GROUP(hscif0_clk_b),
3869 SH_PFC_PIN_GROUP(hscif1_data_a),
3870 SH_PFC_PIN_GROUP(hscif1_clk_a),
3871 SH_PFC_PIN_GROUP(hscif1_data_b),
3872 SH_PFC_PIN_GROUP(hscif1_clk_b),
3873 SH_PFC_PIN_GROUP(hscif1_ctrl_b),
3874 SH_PFC_PIN_GROUP(hscif2_data_a),
3875 SH_PFC_PIN_GROUP(hscif2_clk_a),
3876 SH_PFC_PIN_GROUP(hscif2_ctrl_a),
3877 SH_PFC_PIN_GROUP(hscif2_data_b),
3878 SH_PFC_PIN_GROUP(hscif3_data_a),
3879 SH_PFC_PIN_GROUP(hscif3_data_b),
3880 SH_PFC_PIN_GROUP(hscif3_clk_b),
3881 SH_PFC_PIN_GROUP(hscif3_data_c),
3882 SH_PFC_PIN_GROUP(hscif3_clk_c),
3883 SH_PFC_PIN_GROUP(hscif3_ctrl_c),
3884 SH_PFC_PIN_GROUP(hscif3_data_d),
3885 SH_PFC_PIN_GROUP(hscif3_data_e),
3886 SH_PFC_PIN_GROUP(hscif3_ctrl_e),
3887 SH_PFC_PIN_GROUP(hscif4_data_a),
3888 SH_PFC_PIN_GROUP(hscif4_clk_a),
3889 SH_PFC_PIN_GROUP(hscif4_ctrl_a),
3890 SH_PFC_PIN_GROUP(hscif4_data_b),
3891 SH_PFC_PIN_GROUP(hscif4_clk_b),
3892 SH_PFC_PIN_GROUP(hscif4_data_c),
3893 SH_PFC_PIN_GROUP(hscif4_data_d),
3894 SH_PFC_PIN_GROUP(hscif4_data_e),
3895 SH_PFC_PIN_GROUP(i2c1_a),
3896 SH_PFC_PIN_GROUP(i2c1_b),
3897 SH_PFC_PIN_GROUP(i2c1_c),
3898 SH_PFC_PIN_GROUP(i2c1_d),
3899 SH_PFC_PIN_GROUP(i2c2_a),
3900 SH_PFC_PIN_GROUP(i2c2_b),
3901 SH_PFC_PIN_GROUP(i2c2_c),
3902 SH_PFC_PIN_GROUP(i2c2_d),
3903 SH_PFC_PIN_GROUP(i2c2_e),
3904 SH_PFC_PIN_GROUP(i2c4),
3905 SH_PFC_PIN_GROUP(i2c5),
3906 SH_PFC_PIN_GROUP(i2c6_a),
3907 SH_PFC_PIN_GROUP(i2c6_b),
3908 SH_PFC_PIN_GROUP(i2c7_a),
3909 SH_PFC_PIN_GROUP(i2c7_b),
3910 SH_PFC_PIN_GROUP(intc_ex_irq0),
3911 SH_PFC_PIN_GROUP(intc_ex_irq1),
3912 SH_PFC_PIN_GROUP(intc_ex_irq2),
3913 SH_PFC_PIN_GROUP(intc_ex_irq3),
3914 SH_PFC_PIN_GROUP(intc_ex_irq4),
3915 SH_PFC_PIN_GROUP(intc_ex_irq5),
3916 SH_PFC_PIN_GROUP(msiof0_clk),
3917 SH_PFC_PIN_GROUP(msiof0_sync),
3918 SH_PFC_PIN_GROUP(msiof0_ss1),
3919 SH_PFC_PIN_GROUP(msiof0_ss2),
3920 SH_PFC_PIN_GROUP(msiof0_txd),
3921 SH_PFC_PIN_GROUP(msiof0_rxd),
3922 SH_PFC_PIN_GROUP(msiof1_clk),
3923 SH_PFC_PIN_GROUP(msiof1_sync),
3924 SH_PFC_PIN_GROUP(msiof1_ss1),
3925 SH_PFC_PIN_GROUP(msiof1_ss2),
3926 SH_PFC_PIN_GROUP(msiof1_txd),
3927 SH_PFC_PIN_GROUP(msiof1_rxd),
3928 SH_PFC_PIN_GROUP(msiof2_clk_a),
3929 SH_PFC_PIN_GROUP(msiof2_sync_a),
3930 SH_PFC_PIN_GROUP(msiof2_ss1_a),
3931 SH_PFC_PIN_GROUP(msiof2_ss2_a),
3932 SH_PFC_PIN_GROUP(msiof2_txd_a),
3933 SH_PFC_PIN_GROUP(msiof2_rxd_a),
3934 SH_PFC_PIN_GROUP(msiof2_clk_b),
3935 SH_PFC_PIN_GROUP(msiof2_sync_b),
3936 SH_PFC_PIN_GROUP(msiof2_ss1_b),
3937 SH_PFC_PIN_GROUP(msiof2_ss2_b),
3938 SH_PFC_PIN_GROUP(msiof2_txd_b),
3939 SH_PFC_PIN_GROUP(msiof2_rxd_b),
3940 SH_PFC_PIN_GROUP(msiof3_clk_a),
3941 SH_PFC_PIN_GROUP(msiof3_sync_a),
3942 SH_PFC_PIN_GROUP(msiof3_ss1_a),
3943 SH_PFC_PIN_GROUP(msiof3_ss2_a),
3944 SH_PFC_PIN_GROUP(msiof3_txd_a),
3945 SH_PFC_PIN_GROUP(msiof3_rxd_a),
3946 SH_PFC_PIN_GROUP(msiof3_clk_b),
3947 SH_PFC_PIN_GROUP(msiof3_sync_b),
3948 SH_PFC_PIN_GROUP(msiof3_ss1_b),
3949 SH_PFC_PIN_GROUP(msiof3_txd_b),
3950 SH_PFC_PIN_GROUP(msiof3_rxd_b),
3951 SH_PFC_PIN_GROUP(pwm0_a),
3952 SH_PFC_PIN_GROUP(pwm0_b),
3953 SH_PFC_PIN_GROUP(pwm1_a),
3954 SH_PFC_PIN_GROUP(pwm1_b),
3955 SH_PFC_PIN_GROUP(pwm2_a),
3956 SH_PFC_PIN_GROUP(pwm2_b),
3957 SH_PFC_PIN_GROUP(pwm2_c),
3958 SH_PFC_PIN_GROUP(pwm3_a),
3959 SH_PFC_PIN_GROUP(pwm3_b),
3960 SH_PFC_PIN_GROUP(pwm3_c),
3961 SH_PFC_PIN_GROUP(pwm4_a),
3962 SH_PFC_PIN_GROUP(pwm4_b),
3963 SH_PFC_PIN_GROUP(pwm5_a),
3964 SH_PFC_PIN_GROUP(pwm5_b),
3965 SH_PFC_PIN_GROUP(pwm6_a),
3966 SH_PFC_PIN_GROUP(pwm6_b),
3967 SH_PFC_PIN_GROUP(qspi0_ctrl),
3968 SH_PFC_PIN_GROUP(qspi0_data2),
3969 SH_PFC_PIN_GROUP(qspi0_data4),
3970 SH_PFC_PIN_GROUP(qspi1_ctrl),
3971 SH_PFC_PIN_GROUP(qspi1_data2),
3972 SH_PFC_PIN_GROUP(qspi1_data4),
3973 SH_PFC_PIN_GROUP(scif0_data_a),
3974 SH_PFC_PIN_GROUP(scif0_clk_a),
3975 SH_PFC_PIN_GROUP(scif0_ctrl_a),
3976 SH_PFC_PIN_GROUP(scif0_data_b),
3977 SH_PFC_PIN_GROUP(scif0_clk_b),
3978 SH_PFC_PIN_GROUP(scif1_data),
3979 SH_PFC_PIN_GROUP(scif1_clk),
3980 SH_PFC_PIN_GROUP(scif1_ctrl),
3981 SH_PFC_PIN_GROUP(scif2_data_a),
3982 SH_PFC_PIN_GROUP(scif2_clk_a),
3983 SH_PFC_PIN_GROUP(scif2_data_b),
3984 SH_PFC_PIN_GROUP(scif3_data_a),
3985 SH_PFC_PIN_GROUP(scif3_clk_a),
3986 SH_PFC_PIN_GROUP(scif3_ctrl_a),
3987 SH_PFC_PIN_GROUP(scif3_data_b),
3988 SH_PFC_PIN_GROUP(scif3_data_c),
3989 SH_PFC_PIN_GROUP(scif3_clk_c),
3990 SH_PFC_PIN_GROUP(scif4_data_a),
3991 SH_PFC_PIN_GROUP(scif4_clk_a),
3992 SH_PFC_PIN_GROUP(scif4_ctrl_a),
3993 SH_PFC_PIN_GROUP(scif4_data_b),
3994 SH_PFC_PIN_GROUP(scif4_clk_b),
3995 SH_PFC_PIN_GROUP(scif4_data_c),
3996 SH_PFC_PIN_GROUP(scif4_ctrl_c),
3997 SH_PFC_PIN_GROUP(scif5_data_a),
3998 SH_PFC_PIN_GROUP(scif5_clk_a),
3999 SH_PFC_PIN_GROUP(scif5_data_b),
4000 SH_PFC_PIN_GROUP(scif5_data_c),
4001 SH_PFC_PIN_GROUP(scif_clk_a),
4002 SH_PFC_PIN_GROUP(scif_clk_b),
4003 SH_PFC_PIN_GROUP(sdhi0_data1),
4004 SH_PFC_PIN_GROUP(sdhi0_data4),
4005 SH_PFC_PIN_GROUP(sdhi0_ctrl),
4006 SH_PFC_PIN_GROUP(sdhi0_cd),
4007 SH_PFC_PIN_GROUP(sdhi0_wp),
4008 SH_PFC_PIN_GROUP(sdhi1_data1),
4009 SH_PFC_PIN_GROUP(sdhi1_data4),
4010 SH_PFC_PIN_GROUP(sdhi1_ctrl),
4011 SH_PFC_PIN_GROUP(sdhi1_cd),
4012 SH_PFC_PIN_GROUP(sdhi1_wp),
4013 SH_PFC_PIN_GROUP(sdhi3_data1),
4014 SH_PFC_PIN_GROUP(sdhi3_data4),
4015 SH_PFC_PIN_GROUP(sdhi3_data8),
4016 SH_PFC_PIN_GROUP(sdhi3_ctrl),
4017 SH_PFC_PIN_GROUP(sdhi3_cd),
4018 SH_PFC_PIN_GROUP(sdhi3_wp),
4019 SH_PFC_PIN_GROUP(sdhi3_ds),
4020 SH_PFC_PIN_GROUP(ssi0_data),
4021 SH_PFC_PIN_GROUP(ssi01239_ctrl),
4022 SH_PFC_PIN_GROUP(ssi1_data),
4023 SH_PFC_PIN_GROUP(ssi1_ctrl),
4024 SH_PFC_PIN_GROUP(ssi2_data),
4025 SH_PFC_PIN_GROUP(ssi2_ctrl_a),
4026 SH_PFC_PIN_GROUP(ssi2_ctrl_b),
4027 SH_PFC_PIN_GROUP(ssi3_data),
4028 SH_PFC_PIN_GROUP(ssi349_ctrl),
4029 SH_PFC_PIN_GROUP(ssi4_data),
4030 SH_PFC_PIN_GROUP(ssi4_ctrl),
4031 SH_PFC_PIN_GROUP(ssi5_data),
4032 SH_PFC_PIN_GROUP(ssi5_ctrl),
4033 SH_PFC_PIN_GROUP(ssi6_data),
4034 SH_PFC_PIN_GROUP(ssi6_ctrl),
4035 SH_PFC_PIN_GROUP(ssi7_data),
4036 SH_PFC_PIN_GROUP(ssi78_ctrl),
4037 SH_PFC_PIN_GROUP(ssi8_data),
4038 SH_PFC_PIN_GROUP(ssi9_data),
4039 SH_PFC_PIN_GROUP(ssi9_ctrl_a),
4040 SH_PFC_PIN_GROUP(ssi9_ctrl_b),
4041 SH_PFC_PIN_GROUP(tmu_tclk1_a),
4042 SH_PFC_PIN_GROUP(tmu_tclk1_b),
4043 SH_PFC_PIN_GROUP(tmu_tclk2_a),
4044 SH_PFC_PIN_GROUP(tmu_tclk2_b),
4045 SH_PFC_PIN_GROUP(usb0_a),
4046 SH_PFC_PIN_GROUP(usb0_b),
4047 SH_PFC_PIN_GROUP(usb0_id),
4048 SH_PFC_PIN_GROUP(usb30),
4049 SH_PFC_PIN_GROUP(usb30_id),
4050 VIN_DATA_PIN_GROUP(vin4_data, 8, _a),
4051 VIN_DATA_PIN_GROUP(vin4_data, 10, _a),
4052 VIN_DATA_PIN_GROUP(vin4_data, 12, _a),
4053 VIN_DATA_PIN_GROUP(vin4_data, 16, _a),
4054 SH_PFC_PIN_GROUP(vin4_data18_a),
4055 VIN_DATA_PIN_GROUP(vin4_data, 20, _a),
4056 VIN_DATA_PIN_GROUP(vin4_data, 24, _a),
4057 VIN_DATA_PIN_GROUP(vin4_data, 8, _b),
4058 VIN_DATA_PIN_GROUP(vin4_data, 10, _b),
4059 VIN_DATA_PIN_GROUP(vin4_data, 12, _b),
4060 VIN_DATA_PIN_GROUP(vin4_data, 16, _b),
4061 SH_PFC_PIN_GROUP(vin4_data18_b),
4062 VIN_DATA_PIN_GROUP(vin4_data, 20, _b),
4063 VIN_DATA_PIN_GROUP(vin4_data, 24, _b),
4064 SH_PFC_PIN_GROUP(vin4_sync),
4065 SH_PFC_PIN_GROUP(vin4_field),
4066 SH_PFC_PIN_GROUP(vin4_clkenb),
4067 SH_PFC_PIN_GROUP(vin4_clk),
4068 VIN_DATA_PIN_GROUP(vin5_data, 8, _a),
4069 VIN_DATA_PIN_GROUP(vin5_data, 10, _a),
4070 VIN_DATA_PIN_GROUP(vin5_data, 12, _a),
4071 VIN_DATA_PIN_GROUP(vin5_data, 16, _a),
4072 SH_PFC_PIN_GROUP(vin5_data8_b),
4073 SH_PFC_PIN_GROUP(vin5_sync_a),
4074 SH_PFC_PIN_GROUP(vin5_field_a),
4075 SH_PFC_PIN_GROUP(vin5_clkenb_a),
4076 SH_PFC_PIN_GROUP(vin5_clk_a),
4077 SH_PFC_PIN_GROUP(vin5_clk_b),
4078 },
4079 #ifdef CONFIG_PINCTRL_PFC_R8A77990
4080 .automotive = {
4081 SH_PFC_PIN_GROUP(drif0_ctrl_a),
4082 SH_PFC_PIN_GROUP(drif0_data0_a),
4083 SH_PFC_PIN_GROUP(drif0_data1_a),
4084 SH_PFC_PIN_GROUP(drif0_ctrl_b),
4085 SH_PFC_PIN_GROUP(drif0_data0_b),
4086 SH_PFC_PIN_GROUP(drif0_data1_b),
4087 SH_PFC_PIN_GROUP(drif1_ctrl),
4088 SH_PFC_PIN_GROUP(drif1_data0),
4089 SH_PFC_PIN_GROUP(drif1_data1),
4090 SH_PFC_PIN_GROUP(drif2_ctrl_a),
4091 SH_PFC_PIN_GROUP(drif2_data0_a),
4092 SH_PFC_PIN_GROUP(drif2_data1_a),
4093 SH_PFC_PIN_GROUP(drif2_ctrl_b),
4094 SH_PFC_PIN_GROUP(drif2_data0_b),
4095 SH_PFC_PIN_GROUP(drif2_data1_b),
4096 SH_PFC_PIN_GROUP(drif3_ctrl_a),
4097 SH_PFC_PIN_GROUP(drif3_data0_a),
4098 SH_PFC_PIN_GROUP(drif3_data1_a),
4099 SH_PFC_PIN_GROUP(drif3_ctrl_b),
4100 SH_PFC_PIN_GROUP(drif3_data0_b),
4101 SH_PFC_PIN_GROUP(drif3_data1_b),
4102 }
4103 #endif /* CONFIG_PINCTRL_PFC_R8A77990 */
4104 };
4105
4106 static const char * const audio_clk_groups[] = {
4107 "audio_clk_a",
4108 "audio_clk_b_a",
4109 "audio_clk_b_b",
4110 "audio_clk_b_c",
4111 "audio_clk_c_a",
4112 "audio_clk_c_b",
4113 "audio_clk_c_c",
4114 "audio_clkout_a",
4115 "audio_clkout_b",
4116 "audio_clkout1_a",
4117 "audio_clkout1_b",
4118 "audio_clkout1_c",
4119 "audio_clkout2_a",
4120 "audio_clkout2_b",
4121 "audio_clkout2_c",
4122 "audio_clkout3_a",
4123 "audio_clkout3_b",
4124 "audio_clkout3_c",
4125 };
4126
4127 static const char * const avb_groups[] = {
4128 "avb_link",
4129 "avb_magic",
4130 "avb_phy_int",
4131 "avb_mii",
4132 "avb_avtp_pps",
4133 "avb_avtp_match",
4134 "avb_avtp_capture",
4135 };
4136
4137 static const char * const can0_groups[] = {
4138 "can0_data",
4139 };
4140
4141 static const char * const can1_groups[] = {
4142 "can1_data",
4143 };
4144
4145 static const char * const can_clk_groups[] = {
4146 "can_clk",
4147 };
4148
4149 static const char * const canfd0_groups[] = {
4150 "canfd0_data",
4151 };
4152
4153 static const char * const canfd1_groups[] = {
4154 "canfd1_data",
4155 };
4156
4157 #ifdef CONFIG_PINCTRL_PFC_R8A77990
4158 static const char * const drif0_groups[] = {
4159 "drif0_ctrl_a",
4160 "drif0_data0_a",
4161 "drif0_data1_a",
4162 "drif0_ctrl_b",
4163 "drif0_data0_b",
4164 "drif0_data1_b",
4165 };
4166
4167 static const char * const drif1_groups[] = {
4168 "drif1_ctrl",
4169 "drif1_data0",
4170 "drif1_data1",
4171 };
4172
4173 static const char * const drif2_groups[] = {
4174 "drif2_ctrl_a",
4175 "drif2_data0_a",
4176 "drif2_data1_a",
4177 "drif2_ctrl_b",
4178 "drif2_data0_b",
4179 "drif2_data1_b",
4180 };
4181
4182 static const char * const drif3_groups[] = {
4183 "drif3_ctrl_a",
4184 "drif3_data0_a",
4185 "drif3_data1_a",
4186 "drif3_ctrl_b",
4187 "drif3_data0_b",
4188 "drif3_data1_b",
4189 };
4190 #endif /* CONFIG_PINCTRL_PFC_R8A77990 */
4191
4192 static const char * const du_groups[] = {
4193 "du_rgb666",
4194 "du_rgb888",
4195 "du_clk_in_0",
4196 "du_clk_in_1",
4197 "du_clk_out_0",
4198 "du_sync",
4199 "du_disp_cde",
4200 "du_cde",
4201 "du_disp",
4202 };
4203
4204 static const char * const hscif0_groups[] = {
4205 "hscif0_data_a",
4206 "hscif0_clk_a",
4207 "hscif0_ctrl_a",
4208 "hscif0_data_b",
4209 "hscif0_clk_b",
4210 };
4211
4212 static const char * const hscif1_groups[] = {
4213 "hscif1_data_a",
4214 "hscif1_clk_a",
4215 "hscif1_data_b",
4216 "hscif1_clk_b",
4217 "hscif1_ctrl_b",
4218 };
4219
4220 static const char * const hscif2_groups[] = {
4221 "hscif2_data_a",
4222 "hscif2_clk_a",
4223 "hscif2_ctrl_a",
4224 "hscif2_data_b",
4225 };
4226
4227 static const char * const hscif3_groups[] = {
4228 "hscif3_data_a",
4229 "hscif3_data_b",
4230 "hscif3_clk_b",
4231 "hscif3_data_c",
4232 "hscif3_clk_c",
4233 "hscif3_ctrl_c",
4234 "hscif3_data_d",
4235 "hscif3_data_e",
4236 "hscif3_ctrl_e",
4237 };
4238
4239 static const char * const hscif4_groups[] = {
4240 "hscif4_data_a",
4241 "hscif4_clk_a",
4242 "hscif4_ctrl_a",
4243 "hscif4_data_b",
4244 "hscif4_clk_b",
4245 "hscif4_data_c",
4246 "hscif4_data_d",
4247 "hscif4_data_e",
4248 };
4249
4250 static const char * const i2c1_groups[] = {
4251 "i2c1_a",
4252 "i2c1_b",
4253 "i2c1_c",
4254 "i2c1_d",
4255 };
4256
4257 static const char * const i2c2_groups[] = {
4258 "i2c2_a",
4259 "i2c2_b",
4260 "i2c2_c",
4261 "i2c2_d",
4262 "i2c2_e",
4263 };
4264
4265 static const char * const i2c4_groups[] = {
4266 "i2c4",
4267 };
4268
4269 static const char * const i2c5_groups[] = {
4270 "i2c5",
4271 };
4272
4273 static const char * const i2c6_groups[] = {
4274 "i2c6_a",
4275 "i2c6_b",
4276 };
4277
4278 static const char * const i2c7_groups[] = {
4279 "i2c7_a",
4280 "i2c7_b",
4281 };
4282
4283 static const char * const intc_ex_groups[] = {
4284 "intc_ex_irq0",
4285 "intc_ex_irq1",
4286 "intc_ex_irq2",
4287 "intc_ex_irq3",
4288 "intc_ex_irq4",
4289 "intc_ex_irq5",
4290 };
4291
4292 static const char * const msiof0_groups[] = {
4293 "msiof0_clk",
4294 "msiof0_sync",
4295 "msiof0_ss1",
4296 "msiof0_ss2",
4297 "msiof0_txd",
4298 "msiof0_rxd",
4299 };
4300
4301 static const char * const msiof1_groups[] = {
4302 "msiof1_clk",
4303 "msiof1_sync",
4304 "msiof1_ss1",
4305 "msiof1_ss2",
4306 "msiof1_txd",
4307 "msiof1_rxd",
4308 };
4309
4310 static const char * const msiof2_groups[] = {
4311 "msiof2_clk_a",
4312 "msiof2_sync_a",
4313 "msiof2_ss1_a",
4314 "msiof2_ss2_a",
4315 "msiof2_txd_a",
4316 "msiof2_rxd_a",
4317 "msiof2_clk_b",
4318 "msiof2_sync_b",
4319 "msiof2_ss1_b",
4320 "msiof2_ss2_b",
4321 "msiof2_txd_b",
4322 "msiof2_rxd_b",
4323 };
4324
4325 static const char * const msiof3_groups[] = {
4326 "msiof3_clk_a",
4327 "msiof3_sync_a",
4328 "msiof3_ss1_a",
4329 "msiof3_ss2_a",
4330 "msiof3_txd_a",
4331 "msiof3_rxd_a",
4332 "msiof3_clk_b",
4333 "msiof3_sync_b",
4334 "msiof3_ss1_b",
4335 "msiof3_txd_b",
4336 "msiof3_rxd_b",
4337 };
4338
4339 static const char * const pwm0_groups[] = {
4340 "pwm0_a",
4341 "pwm0_b",
4342 };
4343
4344 static const char * const pwm1_groups[] = {
4345 "pwm1_a",
4346 "pwm1_b",
4347 };
4348
4349 static const char * const pwm2_groups[] = {
4350 "pwm2_a",
4351 "pwm2_b",
4352 "pwm2_c",
4353 };
4354
4355 static const char * const pwm3_groups[] = {
4356 "pwm3_a",
4357 "pwm3_b",
4358 "pwm3_c",
4359 };
4360
4361 static const char * const pwm4_groups[] = {
4362 "pwm4_a",
4363 "pwm4_b",
4364 };
4365
4366 static const char * const pwm5_groups[] = {
4367 "pwm5_a",
4368 "pwm5_b",
4369 };
4370
4371 static const char * const pwm6_groups[] = {
4372 "pwm6_a",
4373 "pwm6_b",
4374 };
4375
4376 static const char * const qspi0_groups[] = {
4377 "qspi0_ctrl",
4378 "qspi0_data2",
4379 "qspi0_data4",
4380 };
4381
4382 static const char * const qspi1_groups[] = {
4383 "qspi1_ctrl",
4384 "qspi1_data2",
4385 "qspi1_data4",
4386 };
4387
4388 static const char * const scif0_groups[] = {
4389 "scif0_data_a",
4390 "scif0_clk_a",
4391 "scif0_ctrl_a",
4392 "scif0_data_b",
4393 "scif0_clk_b",
4394 };
4395
4396 static const char * const scif1_groups[] = {
4397 "scif1_data",
4398 "scif1_clk",
4399 "scif1_ctrl",
4400 };
4401
4402 static const char * const scif2_groups[] = {
4403 "scif2_data_a",
4404 "scif2_clk_a",
4405 "scif2_data_b",
4406 };
4407
4408 static const char * const scif3_groups[] = {
4409 "scif3_data_a",
4410 "scif3_clk_a",
4411 "scif3_ctrl_a",
4412 "scif3_data_b",
4413 "scif3_data_c",
4414 "scif3_clk_c",
4415 };
4416
4417 static const char * const scif4_groups[] = {
4418 "scif4_data_a",
4419 "scif4_clk_a",
4420 "scif4_ctrl_a",
4421 "scif4_data_b",
4422 "scif4_clk_b",
4423 "scif4_data_c",
4424 "scif4_ctrl_c",
4425 };
4426
4427 static const char * const scif5_groups[] = {
4428 "scif5_data_a",
4429 "scif5_clk_a",
4430 "scif5_data_b",
4431 "scif5_data_c",
4432 };
4433
4434 static const char * const scif_clk_groups[] = {
4435 "scif_clk_a",
4436 "scif_clk_b",
4437 };
4438
4439 static const char * const sdhi0_groups[] = {
4440 "sdhi0_data1",
4441 "sdhi0_data4",
4442 "sdhi0_ctrl",
4443 "sdhi0_cd",
4444 "sdhi0_wp",
4445 };
4446
4447 static const char * const sdhi1_groups[] = {
4448 "sdhi1_data1",
4449 "sdhi1_data4",
4450 "sdhi1_ctrl",
4451 "sdhi1_cd",
4452 "sdhi1_wp",
4453 };
4454
4455 static const char * const sdhi3_groups[] = {
4456 "sdhi3_data1",
4457 "sdhi3_data4",
4458 "sdhi3_data8",
4459 "sdhi3_ctrl",
4460 "sdhi3_cd",
4461 "sdhi3_wp",
4462 "sdhi3_ds",
4463 };
4464
4465 static const char * const ssi_groups[] = {
4466 "ssi0_data",
4467 "ssi01239_ctrl",
4468 "ssi1_data",
4469 "ssi1_ctrl",
4470 "ssi2_data",
4471 "ssi2_ctrl_a",
4472 "ssi2_ctrl_b",
4473 "ssi3_data",
4474 "ssi349_ctrl",
4475 "ssi4_data",
4476 "ssi4_ctrl",
4477 "ssi5_data",
4478 "ssi5_ctrl",
4479 "ssi6_data",
4480 "ssi6_ctrl",
4481 "ssi7_data",
4482 "ssi78_ctrl",
4483 "ssi8_data",
4484 "ssi9_data",
4485 "ssi9_ctrl_a",
4486 "ssi9_ctrl_b",
4487 };
4488
4489 static const char * const tmu_groups[] = {
4490 "tmu_tclk1_a",
4491 "tmu_tclk1_b",
4492 "tmu_tclk2_a",
4493 "tmu_tclk2_b",
4494 };
4495
4496 static const char * const usb0_groups[] = {
4497 "usb0_a",
4498 "usb0_b",
4499 "usb0_id",
4500 };
4501
4502 static const char * const usb30_groups[] = {
4503 "usb30",
4504 "usb30_id",
4505 };
4506
4507 static const char * const vin4_groups[] = {
4508 "vin4_data8_a",
4509 "vin4_data10_a",
4510 "vin4_data12_a",
4511 "vin4_data16_a",
4512 "vin4_data18_a",
4513 "vin4_data20_a",
4514 "vin4_data24_a",
4515 "vin4_data8_b",
4516 "vin4_data10_b",
4517 "vin4_data12_b",
4518 "vin4_data16_b",
4519 "vin4_data18_b",
4520 "vin4_data20_b",
4521 "vin4_data24_b",
4522 "vin4_sync",
4523 "vin4_field",
4524 "vin4_clkenb",
4525 "vin4_clk",
4526 };
4527
4528 static const char * const vin5_groups[] = {
4529 "vin5_data8_a",
4530 "vin5_data10_a",
4531 "vin5_data12_a",
4532 "vin5_data16_a",
4533 "vin5_data8_b",
4534 "vin5_sync_a",
4535 "vin5_field_a",
4536 "vin5_clkenb_a",
4537 "vin5_clk_a",
4538 "vin5_clk_b",
4539 };
4540
4541 static const struct {
4542 struct sh_pfc_function common[49];
4543 #ifdef CONFIG_PINCTRL_PFC_R8A77990
4544 struct sh_pfc_function automotive[4];
4545 #endif
4546 } pinmux_functions = {
4547 .common = {
4548 SH_PFC_FUNCTION(audio_clk),
4549 SH_PFC_FUNCTION(avb),
4550 SH_PFC_FUNCTION(can0),
4551 SH_PFC_FUNCTION(can1),
4552 SH_PFC_FUNCTION(can_clk),
4553 SH_PFC_FUNCTION(canfd0),
4554 SH_PFC_FUNCTION(canfd1),
4555 SH_PFC_FUNCTION(du),
4556 SH_PFC_FUNCTION(hscif0),
4557 SH_PFC_FUNCTION(hscif1),
4558 SH_PFC_FUNCTION(hscif2),
4559 SH_PFC_FUNCTION(hscif3),
4560 SH_PFC_FUNCTION(hscif4),
4561 SH_PFC_FUNCTION(i2c1),
4562 SH_PFC_FUNCTION(i2c2),
4563 SH_PFC_FUNCTION(i2c4),
4564 SH_PFC_FUNCTION(i2c5),
4565 SH_PFC_FUNCTION(i2c6),
4566 SH_PFC_FUNCTION(i2c7),
4567 SH_PFC_FUNCTION(intc_ex),
4568 SH_PFC_FUNCTION(msiof0),
4569 SH_PFC_FUNCTION(msiof1),
4570 SH_PFC_FUNCTION(msiof2),
4571 SH_PFC_FUNCTION(msiof3),
4572 SH_PFC_FUNCTION(pwm0),
4573 SH_PFC_FUNCTION(pwm1),
4574 SH_PFC_FUNCTION(pwm2),
4575 SH_PFC_FUNCTION(pwm3),
4576 SH_PFC_FUNCTION(pwm4),
4577 SH_PFC_FUNCTION(pwm5),
4578 SH_PFC_FUNCTION(pwm6),
4579 SH_PFC_FUNCTION(qspi0),
4580 SH_PFC_FUNCTION(qspi1),
4581 SH_PFC_FUNCTION(scif0),
4582 SH_PFC_FUNCTION(scif1),
4583 SH_PFC_FUNCTION(scif2),
4584 SH_PFC_FUNCTION(scif3),
4585 SH_PFC_FUNCTION(scif4),
4586 SH_PFC_FUNCTION(scif5),
4587 SH_PFC_FUNCTION(scif_clk),
4588 SH_PFC_FUNCTION(sdhi0),
4589 SH_PFC_FUNCTION(sdhi1),
4590 SH_PFC_FUNCTION(sdhi3),
4591 SH_PFC_FUNCTION(ssi),
4592 SH_PFC_FUNCTION(tmu),
4593 SH_PFC_FUNCTION(usb0),
4594 SH_PFC_FUNCTION(usb30),
4595 SH_PFC_FUNCTION(vin4),
4596 SH_PFC_FUNCTION(vin5),
4597 },
4598 #ifdef CONFIG_PINCTRL_PFC_R8A77990
4599 .automotive = {
4600 SH_PFC_FUNCTION(drif0),
4601 SH_PFC_FUNCTION(drif1),
4602 SH_PFC_FUNCTION(drif2),
4603 SH_PFC_FUNCTION(drif3),
4604 }
4605 #endif /* CONFIG_PINCTRL_PFC_R8A77990 */
4606 };
4607
4608 static const struct pinmux_cfg_reg pinmux_config_regs[] = {
4609 #define F_(x, y) FN_##y
4610 #define FM(x) FN_##x
4611 { PINMUX_CFG_REG("GPSR0", 0xe6060100, 32, 1, GROUP(
4612 0, 0,
4613 0, 0,
4614 0, 0,
4615 0, 0,
4616 0, 0,
4617 0, 0,
4618 0, 0,
4619 0, 0,
4620 0, 0,
4621 0, 0,
4622 0, 0,
4623 0, 0,
4624 0, 0,
4625 0, 0,
4626 GP_0_17_FN, GPSR0_17,
4627 GP_0_16_FN, GPSR0_16,
4628 GP_0_15_FN, GPSR0_15,
4629 GP_0_14_FN, GPSR0_14,
4630 GP_0_13_FN, GPSR0_13,
4631 GP_0_12_FN, GPSR0_12,
4632 GP_0_11_FN, GPSR0_11,
4633 GP_0_10_FN, GPSR0_10,
4634 GP_0_9_FN, GPSR0_9,
4635 GP_0_8_FN, GPSR0_8,
4636 GP_0_7_FN, GPSR0_7,
4637 GP_0_6_FN, GPSR0_6,
4638 GP_0_5_FN, GPSR0_5,
4639 GP_0_4_FN, GPSR0_4,
4640 GP_0_3_FN, GPSR0_3,
4641 GP_0_2_FN, GPSR0_2,
4642 GP_0_1_FN, GPSR0_1,
4643 GP_0_0_FN, GPSR0_0, ))
4644 },
4645 { PINMUX_CFG_REG("GPSR1", 0xe6060104, 32, 1, GROUP(
4646 0, 0,
4647 0, 0,
4648 0, 0,
4649 0, 0,
4650 0, 0,
4651 0, 0,
4652 0, 0,
4653 0, 0,
4654 0, 0,
4655 GP_1_22_FN, GPSR1_22,
4656 GP_1_21_FN, GPSR1_21,
4657 GP_1_20_FN, GPSR1_20,
4658 GP_1_19_FN, GPSR1_19,
4659 GP_1_18_FN, GPSR1_18,
4660 GP_1_17_FN, GPSR1_17,
4661 GP_1_16_FN, GPSR1_16,
4662 GP_1_15_FN, GPSR1_15,
4663 GP_1_14_FN, GPSR1_14,
4664 GP_1_13_FN, GPSR1_13,
4665 GP_1_12_FN, GPSR1_12,
4666 GP_1_11_FN, GPSR1_11,
4667 GP_1_10_FN, GPSR1_10,
4668 GP_1_9_FN, GPSR1_9,
4669 GP_1_8_FN, GPSR1_8,
4670 GP_1_7_FN, GPSR1_7,
4671 GP_1_6_FN, GPSR1_6,
4672 GP_1_5_FN, GPSR1_5,
4673 GP_1_4_FN, GPSR1_4,
4674 GP_1_3_FN, GPSR1_3,
4675 GP_1_2_FN, GPSR1_2,
4676 GP_1_1_FN, GPSR1_1,
4677 GP_1_0_FN, GPSR1_0, ))
4678 },
4679 { PINMUX_CFG_REG("GPSR2", 0xe6060108, 32, 1, GROUP(
4680 0, 0,
4681 0, 0,
4682 0, 0,
4683 0, 0,
4684 0, 0,
4685 0, 0,
4686 GP_2_25_FN, GPSR2_25,
4687 GP_2_24_FN, GPSR2_24,
4688 GP_2_23_FN, GPSR2_23,
4689 GP_2_22_FN, GPSR2_22,
4690 GP_2_21_FN, GPSR2_21,
4691 GP_2_20_FN, GPSR2_20,
4692 GP_2_19_FN, GPSR2_19,
4693 GP_2_18_FN, GPSR2_18,
4694 GP_2_17_FN, GPSR2_17,
4695 GP_2_16_FN, GPSR2_16,
4696 GP_2_15_FN, GPSR2_15,
4697 GP_2_14_FN, GPSR2_14,
4698 GP_2_13_FN, GPSR2_13,
4699 GP_2_12_FN, GPSR2_12,
4700 GP_2_11_FN, GPSR2_11,
4701 GP_2_10_FN, GPSR2_10,
4702 GP_2_9_FN, GPSR2_9,
4703 GP_2_8_FN, GPSR2_8,
4704 GP_2_7_FN, GPSR2_7,
4705 GP_2_6_FN, GPSR2_6,
4706 GP_2_5_FN, GPSR2_5,
4707 GP_2_4_FN, GPSR2_4,
4708 GP_2_3_FN, GPSR2_3,
4709 GP_2_2_FN, GPSR2_2,
4710 GP_2_1_FN, GPSR2_1,
4711 GP_2_0_FN, GPSR2_0, ))
4712 },
4713 { PINMUX_CFG_REG("GPSR3", 0xe606010c, 32, 1, GROUP(
4714 0, 0,
4715 0, 0,
4716 0, 0,
4717 0, 0,
4718 0, 0,
4719 0, 0,
4720 0, 0,
4721 0, 0,
4722 0, 0,
4723 0, 0,
4724 0, 0,
4725 0, 0,
4726 0, 0,
4727 0, 0,
4728 0, 0,
4729 0, 0,
4730 GP_3_15_FN, GPSR3_15,
4731 GP_3_14_FN, GPSR3_14,
4732 GP_3_13_FN, GPSR3_13,
4733 GP_3_12_FN, GPSR3_12,
4734 GP_3_11_FN, GPSR3_11,
4735 GP_3_10_FN, GPSR3_10,
4736 GP_3_9_FN, GPSR3_9,
4737 GP_3_8_FN, GPSR3_8,
4738 GP_3_7_FN, GPSR3_7,
4739 GP_3_6_FN, GPSR3_6,
4740 GP_3_5_FN, GPSR3_5,
4741 GP_3_4_FN, GPSR3_4,
4742 GP_3_3_FN, GPSR3_3,
4743 GP_3_2_FN, GPSR3_2,
4744 GP_3_1_FN, GPSR3_1,
4745 GP_3_0_FN, GPSR3_0, ))
4746 },
4747 { PINMUX_CFG_REG("GPSR4", 0xe6060110, 32, 1, GROUP(
4748 0, 0,
4749 0, 0,
4750 0, 0,
4751 0, 0,
4752 0, 0,
4753 0, 0,
4754 0, 0,
4755 0, 0,
4756 0, 0,
4757 0, 0,
4758 0, 0,
4759 0, 0,
4760 0, 0,
4761 0, 0,
4762 0, 0,
4763 0, 0,
4764 0, 0,
4765 0, 0,
4766 0, 0,
4767 0, 0,
4768 0, 0,
4769 GP_4_10_FN, GPSR4_10,
4770 GP_4_9_FN, GPSR4_9,
4771 GP_4_8_FN, GPSR4_8,
4772 GP_4_7_FN, GPSR4_7,
4773 GP_4_6_FN, GPSR4_6,
4774 GP_4_5_FN, GPSR4_5,
4775 GP_4_4_FN, GPSR4_4,
4776 GP_4_3_FN, GPSR4_3,
4777 GP_4_2_FN, GPSR4_2,
4778 GP_4_1_FN, GPSR4_1,
4779 GP_4_0_FN, GPSR4_0, ))
4780 },
4781 { PINMUX_CFG_REG("GPSR5", 0xe6060114, 32, 1, GROUP(
4782 0, 0,
4783 0, 0,
4784 0, 0,
4785 0, 0,
4786 0, 0,
4787 0, 0,
4788 0, 0,
4789 0, 0,
4790 0, 0,
4791 0, 0,
4792 0, 0,
4793 0, 0,
4794 GP_5_19_FN, GPSR5_19,
4795 GP_5_18_FN, GPSR5_18,
4796 GP_5_17_FN, GPSR5_17,
4797 GP_5_16_FN, GPSR5_16,
4798 GP_5_15_FN, GPSR5_15,
4799 GP_5_14_FN, GPSR5_14,
4800 GP_5_13_FN, GPSR5_13,
4801 GP_5_12_FN, GPSR5_12,
4802 GP_5_11_FN, GPSR5_11,
4803 GP_5_10_FN, GPSR5_10,
4804 GP_5_9_FN, GPSR5_9,
4805 GP_5_8_FN, GPSR5_8,
4806 GP_5_7_FN, GPSR5_7,
4807 GP_5_6_FN, GPSR5_6,
4808 GP_5_5_FN, GPSR5_5,
4809 GP_5_4_FN, GPSR5_4,
4810 GP_5_3_FN, GPSR5_3,
4811 GP_5_2_FN, GPSR5_2,
4812 GP_5_1_FN, GPSR5_1,
4813 GP_5_0_FN, GPSR5_0, ))
4814 },
4815 { PINMUX_CFG_REG("GPSR6", 0xe6060118, 32, 1, GROUP(
4816 0, 0,
4817 0, 0,
4818 0, 0,
4819 0, 0,
4820 0, 0,
4821 0, 0,
4822 0, 0,
4823 0, 0,
4824 0, 0,
4825 0, 0,
4826 0, 0,
4827 0, 0,
4828 0, 0,
4829 0, 0,
4830 GP_6_17_FN, GPSR6_17,
4831 GP_6_16_FN, GPSR6_16,
4832 GP_6_15_FN, GPSR6_15,
4833 GP_6_14_FN, GPSR6_14,
4834 GP_6_13_FN, GPSR6_13,
4835 GP_6_12_FN, GPSR6_12,
4836 GP_6_11_FN, GPSR6_11,
4837 GP_6_10_FN, GPSR6_10,
4838 GP_6_9_FN, GPSR6_9,
4839 GP_6_8_FN, GPSR6_8,
4840 GP_6_7_FN, GPSR6_7,
4841 GP_6_6_FN, GPSR6_6,
4842 GP_6_5_FN, GPSR6_5,
4843 GP_6_4_FN, GPSR6_4,
4844 GP_6_3_FN, GPSR6_3,
4845 GP_6_2_FN, GPSR6_2,
4846 GP_6_1_FN, GPSR6_1,
4847 GP_6_0_FN, GPSR6_0, ))
4848 },
4849 #undef F_
4850 #undef FM
4851
4852 #define F_(x, y) x,
4853 #define FM(x) FN_##x,
4854 { PINMUX_CFG_REG("IPSR0", 0xe6060200, 32, 4, GROUP(
4855 IP0_31_28
4856 IP0_27_24
4857 IP0_23_20
4858 IP0_19_16
4859 IP0_15_12
4860 IP0_11_8
4861 IP0_7_4
4862 IP0_3_0 ))
4863 },
4864 { PINMUX_CFG_REG("IPSR1", 0xe6060204, 32, 4, GROUP(
4865 IP1_31_28
4866 IP1_27_24
4867 IP1_23_20
4868 IP1_19_16
4869 IP1_15_12
4870 IP1_11_8
4871 IP1_7_4
4872 IP1_3_0 ))
4873 },
4874 { PINMUX_CFG_REG("IPSR2", 0xe6060208, 32, 4, GROUP(
4875 IP2_31_28
4876 IP2_27_24
4877 IP2_23_20
4878 IP2_19_16
4879 IP2_15_12
4880 IP2_11_8
4881 IP2_7_4
4882 IP2_3_0 ))
4883 },
4884 { PINMUX_CFG_REG("IPSR3", 0xe606020c, 32, 4, GROUP(
4885 IP3_31_28
4886 IP3_27_24
4887 IP3_23_20
4888 IP3_19_16
4889 IP3_15_12
4890 IP3_11_8
4891 IP3_7_4
4892 IP3_3_0 ))
4893 },
4894 { PINMUX_CFG_REG("IPSR4", 0xe6060210, 32, 4, GROUP(
4895 IP4_31_28
4896 IP4_27_24
4897 IP4_23_20
4898 IP4_19_16
4899 IP4_15_12
4900 IP4_11_8
4901 IP4_7_4
4902 IP4_3_0 ))
4903 },
4904 { PINMUX_CFG_REG("IPSR5", 0xe6060214, 32, 4, GROUP(
4905 IP5_31_28
4906 IP5_27_24
4907 IP5_23_20
4908 IP5_19_16
4909 IP5_15_12
4910 IP5_11_8
4911 IP5_7_4
4912 IP5_3_0 ))
4913 },
4914 { PINMUX_CFG_REG("IPSR6", 0xe6060218, 32, 4, GROUP(
4915 IP6_31_28
4916 IP6_27_24
4917 IP6_23_20
4918 IP6_19_16
4919 IP6_15_12
4920 IP6_11_8
4921 IP6_7_4
4922 IP6_3_0 ))
4923 },
4924 { PINMUX_CFG_REG("IPSR7", 0xe606021c, 32, 4, GROUP(
4925 IP7_31_28
4926 IP7_27_24
4927 IP7_23_20
4928 IP7_19_16
4929 IP7_15_12
4930 IP7_11_8
4931 IP7_7_4
4932 IP7_3_0 ))
4933 },
4934 { PINMUX_CFG_REG("IPSR8", 0xe6060220, 32, 4, GROUP(
4935 IP8_31_28
4936 IP8_27_24
4937 IP8_23_20
4938 IP8_19_16
4939 IP8_15_12
4940 IP8_11_8
4941 IP8_7_4
4942 IP8_3_0 ))
4943 },
4944 { PINMUX_CFG_REG("IPSR9", 0xe6060224, 32, 4, GROUP(
4945 IP9_31_28
4946 IP9_27_24
4947 IP9_23_20
4948 IP9_19_16
4949 IP9_15_12
4950 IP9_11_8
4951 IP9_7_4
4952 IP9_3_0 ))
4953 },
4954 { PINMUX_CFG_REG("IPSR10", 0xe6060228, 32, 4, GROUP(
4955 IP10_31_28
4956 IP10_27_24
4957 IP10_23_20
4958 IP10_19_16
4959 IP10_15_12
4960 IP10_11_8
4961 IP10_7_4
4962 IP10_3_0 ))
4963 },
4964 { PINMUX_CFG_REG("IPSR11", 0xe606022c, 32, 4, GROUP(
4965 IP11_31_28
4966 IP11_27_24
4967 IP11_23_20
4968 IP11_19_16
4969 IP11_15_12
4970 IP11_11_8
4971 IP11_7_4
4972 IP11_3_0 ))
4973 },
4974 { PINMUX_CFG_REG("IPSR12", 0xe6060230, 32, 4, GROUP(
4975 IP12_31_28
4976 IP12_27_24
4977 IP12_23_20
4978 IP12_19_16
4979 IP12_15_12
4980 IP12_11_8
4981 IP12_7_4
4982 IP12_3_0 ))
4983 },
4984 { PINMUX_CFG_REG("IPSR13", 0xe6060234, 32, 4, GROUP(
4985 IP13_31_28
4986 IP13_27_24
4987 IP13_23_20
4988 IP13_19_16
4989 IP13_15_12
4990 IP13_11_8
4991 IP13_7_4
4992 IP13_3_0 ))
4993 },
4994 { PINMUX_CFG_REG("IPSR14", 0xe6060238, 32, 4, GROUP(
4995 IP14_31_28
4996 IP14_27_24
4997 IP14_23_20
4998 IP14_19_16
4999 IP14_15_12
5000 IP14_11_8
5001 IP14_7_4
5002 IP14_3_0 ))
5003 },
5004 { PINMUX_CFG_REG("IPSR15", 0xe606023c, 32, 4, GROUP(
5005 IP15_31_28
5006 IP15_27_24
5007 IP15_23_20
5008 IP15_19_16
5009 IP15_15_12
5010 IP15_11_8
5011 IP15_7_4
5012 IP15_3_0 ))
5013 },
5014 #undef F_
5015 #undef FM
5016
5017 #define F_(x, y) x,
5018 #define FM(x) FN_##x,
5019 { PINMUX_CFG_REG_VAR("MOD_SEL0", 0xe6060500, 32,
5020 GROUP(1, 2, 1, 2, 1, 1, 1, 1, 2, 3, 1, 1,
5021 1, 2, 2, 1, 1, 1, 2, 1, 1, 1, 2),
5022 GROUP(
5023 /* RESERVED 31 */
5024 0, 0,
5025 MOD_SEL0_30_29
5026 MOD_SEL0_28
5027 MOD_SEL0_27_26
5028 MOD_SEL0_25
5029 MOD_SEL0_24
5030 MOD_SEL0_23
5031 MOD_SEL0_22
5032 MOD_SEL0_21_20
5033 MOD_SEL0_19_18_17
5034 MOD_SEL0_16
5035 MOD_SEL0_15
5036 MOD_SEL0_14
5037 MOD_SEL0_13_12
5038 MOD_SEL0_11_10
5039 MOD_SEL0_9
5040 MOD_SEL0_8
5041 MOD_SEL0_7
5042 MOD_SEL0_6_5
5043 MOD_SEL0_4
5044 MOD_SEL0_3
5045 MOD_SEL0_2
5046 MOD_SEL0_1_0 ))
5047 },
5048 { PINMUX_CFG_REG_VAR("MOD_SEL1", 0xe6060504, 32,
5049 GROUP(1, 1, 1, 1, 1, 1, 1, 3, 3, 1, 1, 1,
5050 1, 2, 2, 2, 1, 1, 2, 1, 4),
5051 GROUP(
5052 MOD_SEL1_31
5053 MOD_SEL1_30
5054 MOD_SEL1_29
5055 MOD_SEL1_28
5056 /* RESERVED 27 */
5057 0, 0,
5058 MOD_SEL1_26
5059 MOD_SEL1_25
5060 MOD_SEL1_24_23_22
5061 MOD_SEL1_21_20_19
5062 MOD_SEL1_18
5063 MOD_SEL1_17
5064 MOD_SEL1_16
5065 MOD_SEL1_15
5066 MOD_SEL1_14_13
5067 MOD_SEL1_12_11
5068 MOD_SEL1_10_9
5069 MOD_SEL1_8
5070 MOD_SEL1_7
5071 MOD_SEL1_6_5
5072 MOD_SEL1_4
5073 /* RESERVED 3, 2, 1, 0 */
5074 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 ))
5075 },
5076 { },
5077 };
5078
5079 enum ioctrl_regs {
5080 POCCTRL0,
5081 TDSELCTRL,
5082 };
5083
5084 static const struct pinmux_ioctrl_reg pinmux_ioctrl_regs[] = {
5085 [POCCTRL0] = { 0xe6060380, },
5086 [TDSELCTRL] = { 0xe60603c0, },
5087 { /* sentinel */ },
5088 };
5089
r8a77990_pin_to_pocctrl(struct sh_pfc * pfc,unsigned int pin,u32 * pocctrl)5090 static int r8a77990_pin_to_pocctrl(struct sh_pfc *pfc, unsigned int pin,
5091 u32 *pocctrl)
5092 {
5093 int bit = -EINVAL;
5094
5095 *pocctrl = pinmux_ioctrl_regs[POCCTRL0].reg;
5096
5097 if (pin >= RCAR_GP_PIN(3, 0) && pin <= RCAR_GP_PIN(3, 11))
5098 bit = pin & 0x1f;
5099
5100 if (pin >= RCAR_GP_PIN(4, 0) && pin <= RCAR_GP_PIN(4, 10))
5101 bit = (pin & 0x1f) + 19;
5102
5103 return bit;
5104 }
5105
5106 static const struct pinmux_bias_reg pinmux_bias_regs[] = {
5107 { PINMUX_BIAS_REG("PUEN0", 0xe6060400, "PUD0", 0xe6060440) {
5108 [0] = RCAR_GP_PIN(2, 23), /* RD# */
5109 [1] = RCAR_GP_PIN(2, 22), /* BS# */
5110 [2] = RCAR_GP_PIN(2, 21), /* AVB_PHY_INT */
5111 [3] = PIN_AVB_MDC, /* AVB_MDC */
5112 [4] = PIN_AVB_MDIO, /* AVB_MDIO */
5113 [5] = RCAR_GP_PIN(2, 20), /* AVB_TXCREFCLK */
5114 [6] = PIN_AVB_TD3, /* AVB_TD3 */
5115 [7] = PIN_AVB_TD2, /* AVB_TD2 */
5116 [8] = PIN_AVB_TD1, /* AVB_TD1 */
5117 [9] = PIN_AVB_TD0, /* AVB_TD0 */
5118 [10] = PIN_AVB_TXC, /* AVB_TXC */
5119 [11] = PIN_AVB_TX_CTL, /* AVB_TX_CTL */
5120 [12] = RCAR_GP_PIN(2, 19), /* AVB_RD3 */
5121 [13] = RCAR_GP_PIN(2, 18), /* AVB_RD2 */
5122 [14] = RCAR_GP_PIN(2, 17), /* AVB_RD1 */
5123 [15] = RCAR_GP_PIN(2, 16), /* AVB_RD0 */
5124 [16] = RCAR_GP_PIN(2, 15), /* AVB_RXC */
5125 [17] = RCAR_GP_PIN(2, 14), /* AVB_RX_CTL */
5126 [18] = RCAR_GP_PIN(2, 13), /* RPC_RESET# */
5127 [19] = RCAR_GP_PIN(2, 12), /* RPC_INT# */
5128 [20] = RCAR_GP_PIN(2, 11), /* QSPI1_SSL */
5129 [21] = RCAR_GP_PIN(2, 10), /* QSPI1_IO3 */
5130 [22] = RCAR_GP_PIN(2, 9), /* QSPI1_IO2 */
5131 [23] = RCAR_GP_PIN(2, 8), /* QSPI1_MISO/IO1 */
5132 [24] = RCAR_GP_PIN(2, 7), /* QSPI1_MOSI/IO0 */
5133 [25] = RCAR_GP_PIN(2, 6), /* QSPI1_SPCLK */
5134 [26] = RCAR_GP_PIN(2, 5), /* QSPI0_SSL */
5135 [27] = RCAR_GP_PIN(2, 4), /* QSPI0_IO3 */
5136 [28] = RCAR_GP_PIN(2, 3), /* QSPI0_IO2 */
5137 [29] = RCAR_GP_PIN(2, 2), /* QSPI0_MISO/IO1 */
5138 [30] = RCAR_GP_PIN(2, 1), /* QSPI0_MOSI/IO0 */
5139 [31] = RCAR_GP_PIN(2, 0), /* QSPI0_SPCLK */
5140 } },
5141 { PINMUX_BIAS_REG("PUEN1", 0xe6060404, "PUD1", 0xe6060444) {
5142 [0] = RCAR_GP_PIN(0, 4), /* D4 */
5143 [1] = RCAR_GP_PIN(0, 3), /* D3 */
5144 [2] = RCAR_GP_PIN(0, 2), /* D2 */
5145 [3] = RCAR_GP_PIN(0, 1), /* D1 */
5146 [4] = RCAR_GP_PIN(0, 0), /* D0 */
5147 [5] = RCAR_GP_PIN(1, 22), /* WE0# */
5148 [6] = RCAR_GP_PIN(1, 21), /* CS0# */
5149 [7] = RCAR_GP_PIN(1, 20), /* CLKOUT */
5150 [8] = RCAR_GP_PIN(1, 19), /* A19 */
5151 [9] = RCAR_GP_PIN(1, 18), /* A18 */
5152 [10] = RCAR_GP_PIN(1, 17), /* A17 */
5153 [11] = RCAR_GP_PIN(1, 16), /* A16 */
5154 [12] = RCAR_GP_PIN(1, 15), /* A15 */
5155 [13] = RCAR_GP_PIN(1, 14), /* A14 */
5156 [14] = RCAR_GP_PIN(1, 13), /* A13 */
5157 [15] = RCAR_GP_PIN(1, 12), /* A12 */
5158 [16] = RCAR_GP_PIN(1, 11), /* A11 */
5159 [17] = RCAR_GP_PIN(1, 10), /* A10 */
5160 [18] = RCAR_GP_PIN(1, 9), /* A9 */
5161 [19] = RCAR_GP_PIN(1, 8), /* A8 */
5162 [20] = RCAR_GP_PIN(1, 7), /* A7 */
5163 [21] = RCAR_GP_PIN(1, 6), /* A6 */
5164 [22] = RCAR_GP_PIN(1, 5), /* A5 */
5165 [23] = RCAR_GP_PIN(1, 4), /* A4 */
5166 [24] = RCAR_GP_PIN(1, 3), /* A3 */
5167 [25] = RCAR_GP_PIN(1, 2), /* A2 */
5168 [26] = RCAR_GP_PIN(1, 1), /* A1 */
5169 [27] = RCAR_GP_PIN(1, 0), /* A0 */
5170 [28] = SH_PFC_PIN_NONE,
5171 [29] = SH_PFC_PIN_NONE,
5172 [30] = RCAR_GP_PIN(2, 25), /* PUEN_EX_WAIT0 */
5173 [31] = RCAR_GP_PIN(2, 24), /* PUEN_RD/WR# */
5174 } },
5175 { PINMUX_BIAS_REG("PUEN2", 0xe6060408, "PUD2", 0xe6060448) {
5176 [0] = RCAR_GP_PIN(3, 1), /* SD0_CMD */
5177 [1] = RCAR_GP_PIN(3, 0), /* SD0_CLK */
5178 [2] = PIN_ASEBRK, /* ASEBRK */
5179 [3] = SH_PFC_PIN_NONE,
5180 [4] = PIN_TDI, /* TDI */
5181 [5] = PIN_TMS, /* TMS */
5182 [6] = PIN_TCK, /* TCK */
5183 [7] = PIN_TRST_N, /* TRST# */
5184 [8] = SH_PFC_PIN_NONE,
5185 [9] = SH_PFC_PIN_NONE,
5186 [10] = SH_PFC_PIN_NONE,
5187 [11] = SH_PFC_PIN_NONE,
5188 [12] = SH_PFC_PIN_NONE,
5189 [13] = SH_PFC_PIN_NONE,
5190 [14] = SH_PFC_PIN_NONE,
5191 [15] = PIN_FSCLKST_N, /* FSCLKST# */
5192 [16] = RCAR_GP_PIN(0, 17), /* SDA4 */
5193 [17] = RCAR_GP_PIN(0, 16), /* SCL4 */
5194 [18] = SH_PFC_PIN_NONE,
5195 [19] = SH_PFC_PIN_NONE,
5196 [20] = PIN_PRESETOUT_N, /* PRESETOUT# */
5197 [21] = RCAR_GP_PIN(0, 15), /* D15 */
5198 [22] = RCAR_GP_PIN(0, 14), /* D14 */
5199 [23] = RCAR_GP_PIN(0, 13), /* D13 */
5200 [24] = RCAR_GP_PIN(0, 12), /* D12 */
5201 [25] = RCAR_GP_PIN(0, 11), /* D11 */
5202 [26] = RCAR_GP_PIN(0, 10), /* D10 */
5203 [27] = RCAR_GP_PIN(0, 9), /* D9 */
5204 [28] = RCAR_GP_PIN(0, 8), /* D8 */
5205 [29] = RCAR_GP_PIN(0, 7), /* D7 */
5206 [30] = RCAR_GP_PIN(0, 6), /* D6 */
5207 [31] = RCAR_GP_PIN(0, 5), /* D5 */
5208 } },
5209 { PINMUX_BIAS_REG("PUEN3", 0xe606040c, "PUD3", 0xe606044c) {
5210 [0] = RCAR_GP_PIN(5, 0), /* SCK0_A */
5211 [1] = RCAR_GP_PIN(5, 4), /* RTS0#_A */
5212 [2] = RCAR_GP_PIN(5, 3), /* CTS0#_A */
5213 [3] = RCAR_GP_PIN(5, 2), /* TX0_A */
5214 [4] = RCAR_GP_PIN(5, 1), /* RX0_A */
5215 [5] = SH_PFC_PIN_NONE,
5216 [6] = SH_PFC_PIN_NONE,
5217 [7] = RCAR_GP_PIN(3, 15), /* SD1_WP */
5218 [8] = RCAR_GP_PIN(3, 14), /* SD1_CD */
5219 [9] = RCAR_GP_PIN(3, 13), /* SD0_WP */
5220 [10] = RCAR_GP_PIN(3, 12), /* SD0_CD */
5221 [11] = RCAR_GP_PIN(4, 10), /* SD3_DS */
5222 [12] = RCAR_GP_PIN(4, 9), /* SD3_DAT7 */
5223 [13] = RCAR_GP_PIN(4, 8), /* SD3_DAT6 */
5224 [14] = RCAR_GP_PIN(4, 7), /* SD3_DAT5 */
5225 [15] = RCAR_GP_PIN(4, 6), /* SD3_DAT4 */
5226 [16] = RCAR_GP_PIN(4, 5), /* SD3_DAT3 */
5227 [17] = RCAR_GP_PIN(4, 4), /* SD3_DAT2 */
5228 [18] = RCAR_GP_PIN(4, 3), /* SD3_DAT1 */
5229 [19] = RCAR_GP_PIN(4, 2), /* SD3_DAT0 */
5230 [20] = RCAR_GP_PIN(4, 1), /* SD3_CMD */
5231 [21] = RCAR_GP_PIN(4, 0), /* SD3_CLK */
5232 [22] = RCAR_GP_PIN(3, 11), /* SD1_DAT3 */
5233 [23] = RCAR_GP_PIN(3, 10), /* SD1_DAT2 */
5234 [24] = RCAR_GP_PIN(3, 9), /* SD1_DAT1 */
5235 [25] = RCAR_GP_PIN(3, 8), /* SD1_DAT0 */
5236 [26] = RCAR_GP_PIN(3, 7), /* SD1_CMD */
5237 [27] = RCAR_GP_PIN(3, 6), /* SD1_CLK */
5238 [28] = RCAR_GP_PIN(3, 5), /* SD0_DAT3 */
5239 [29] = RCAR_GP_PIN(3, 4), /* SD0_DAT2 */
5240 [30] = RCAR_GP_PIN(3, 3), /* SD0_DAT1 */
5241 [31] = RCAR_GP_PIN(3, 2), /* SD0_DAT0 */
5242 } },
5243 { PINMUX_BIAS_REG("PUEN4", 0xe6060410, "PUD4", 0xe6060450) {
5244 [0] = RCAR_GP_PIN(6, 8), /* AUDIO_CLKA */
5245 [1] = RCAR_GP_PIN(6, 16), /* SSI_SDATA6 */
5246 [2] = RCAR_GP_PIN(6, 15), /* SSI_WS6 */
5247 [3] = RCAR_GP_PIN(6, 14), /* SSI_SCK6 */
5248 [4] = RCAR_GP_PIN(6, 13), /* SSI_SDATA5 */
5249 [5] = RCAR_GP_PIN(6, 12), /* SSI_WS5 */
5250 [6] = RCAR_GP_PIN(6, 11), /* SSI_SCK5 */
5251 [7] = RCAR_GP_PIN(6, 10), /* SSI_SDATA4 */
5252 [8] = RCAR_GP_PIN(6, 7), /* SSI_SDATA3 */
5253 [9] = RCAR_GP_PIN(6, 6), /* SSI_WS349 */
5254 [10] = RCAR_GP_PIN(6, 5), /* SSI_SCK349 */
5255 [11] = RCAR_GP_PIN(6, 4), /* SSI_SDATA2 */
5256 [12] = RCAR_GP_PIN(6, 3), /* SSI_SDATA1 */
5257 [13] = RCAR_GP_PIN(6, 2), /* SSI_SDATA0 */
5258 [14] = RCAR_GP_PIN(6, 1), /* SSI_WS01239 */
5259 [15] = RCAR_GP_PIN(6, 0), /* SSI_SCK01239 */
5260 [16] = PIN_MLB_REF, /* MLB_REF */
5261 [17] = RCAR_GP_PIN(5, 19), /* MLB_DAT */
5262 [18] = RCAR_GP_PIN(5, 18), /* MLB_SIG */
5263 [19] = RCAR_GP_PIN(5, 17), /* MLB_CLK */
5264 [20] = RCAR_GP_PIN(5, 16), /* SSI_SDATA9 */
5265 [21] = RCAR_GP_PIN(5, 15), /* MSIOF0_SS2 */
5266 [22] = RCAR_GP_PIN(5, 14), /* MSIOF0_SS1 */
5267 [23] = RCAR_GP_PIN(5, 13), /* MSIOF0_SYNC */
5268 [24] = RCAR_GP_PIN(5, 12), /* MSIOF0_TXD */
5269 [25] = RCAR_GP_PIN(5, 11), /* MSIOF0_RXD */
5270 [26] = RCAR_GP_PIN(5, 10), /* MSIOF0_SCK */
5271 [27] = RCAR_GP_PIN(5, 9), /* RX2_A */
5272 [28] = RCAR_GP_PIN(5, 8), /* TX2_A */
5273 [29] = RCAR_GP_PIN(5, 7), /* SCK2_A */
5274 [30] = RCAR_GP_PIN(5, 6), /* TX1 */
5275 [31] = RCAR_GP_PIN(5, 5), /* RX1 */
5276 } },
5277 { PINMUX_BIAS_REG("PUEN5", 0xe6060414, "PUD5", 0xe6060454) {
5278 [0] = SH_PFC_PIN_NONE,
5279 [1] = SH_PFC_PIN_NONE,
5280 [2] = SH_PFC_PIN_NONE,
5281 [3] = SH_PFC_PIN_NONE,
5282 [4] = SH_PFC_PIN_NONE,
5283 [5] = SH_PFC_PIN_NONE,
5284 [6] = SH_PFC_PIN_NONE,
5285 [7] = SH_PFC_PIN_NONE,
5286 [8] = SH_PFC_PIN_NONE,
5287 [9] = SH_PFC_PIN_NONE,
5288 [10] = SH_PFC_PIN_NONE,
5289 [11] = SH_PFC_PIN_NONE,
5290 [12] = SH_PFC_PIN_NONE,
5291 [13] = SH_PFC_PIN_NONE,
5292 [14] = SH_PFC_PIN_NONE,
5293 [15] = SH_PFC_PIN_NONE,
5294 [16] = SH_PFC_PIN_NONE,
5295 [17] = SH_PFC_PIN_NONE,
5296 [18] = SH_PFC_PIN_NONE,
5297 [19] = SH_PFC_PIN_NONE,
5298 [20] = SH_PFC_PIN_NONE,
5299 [21] = SH_PFC_PIN_NONE,
5300 [22] = SH_PFC_PIN_NONE,
5301 [23] = SH_PFC_PIN_NONE,
5302 [24] = SH_PFC_PIN_NONE,
5303 [25] = SH_PFC_PIN_NONE,
5304 [26] = SH_PFC_PIN_NONE,
5305 [27] = SH_PFC_PIN_NONE,
5306 [28] = SH_PFC_PIN_NONE,
5307 [29] = SH_PFC_PIN_NONE,
5308 [30] = RCAR_GP_PIN(6, 9), /* PUEN_USB30_OVC */
5309 [31] = RCAR_GP_PIN(6, 17), /* PUEN_USB30_PWEN */
5310 } },
5311 { /* sentinel */ },
5312 };
5313
r8a77990_pinmux_get_bias(struct sh_pfc * pfc,unsigned int pin)5314 static unsigned int r8a77990_pinmux_get_bias(struct sh_pfc *pfc,
5315 unsigned int pin)
5316 {
5317 const struct pinmux_bias_reg *reg;
5318 unsigned int bit;
5319
5320 reg = sh_pfc_pin_to_bias_reg(pfc, pin, &bit);
5321 if (!reg)
5322 return PIN_CONFIG_BIAS_DISABLE;
5323
5324 if (!(sh_pfc_read(pfc, reg->puen) & BIT(bit)))
5325 return PIN_CONFIG_BIAS_DISABLE;
5326 else if (sh_pfc_read(pfc, reg->pud) & BIT(bit))
5327 return PIN_CONFIG_BIAS_PULL_UP;
5328 else
5329 return PIN_CONFIG_BIAS_PULL_DOWN;
5330 }
5331
r8a77990_pinmux_set_bias(struct sh_pfc * pfc,unsigned int pin,unsigned int bias)5332 static void r8a77990_pinmux_set_bias(struct sh_pfc *pfc, unsigned int pin,
5333 unsigned int bias)
5334 {
5335 const struct pinmux_bias_reg *reg;
5336 u32 enable, updown;
5337 unsigned int bit;
5338
5339 reg = sh_pfc_pin_to_bias_reg(pfc, pin, &bit);
5340 if (!reg)
5341 return;
5342
5343 enable = sh_pfc_read(pfc, reg->puen) & ~BIT(bit);
5344 if (bias != PIN_CONFIG_BIAS_DISABLE)
5345 enable |= BIT(bit);
5346
5347 updown = sh_pfc_read(pfc, reg->pud) & ~BIT(bit);
5348 if (bias == PIN_CONFIG_BIAS_PULL_UP)
5349 updown |= BIT(bit);
5350
5351 sh_pfc_write(pfc, reg->pud, updown);
5352 sh_pfc_write(pfc, reg->puen, enable);
5353 }
5354
5355 static const struct sh_pfc_soc_operations r8a77990_pinmux_ops = {
5356 .pin_to_pocctrl = r8a77990_pin_to_pocctrl,
5357 .get_bias = r8a77990_pinmux_get_bias,
5358 .set_bias = r8a77990_pinmux_set_bias,
5359 };
5360
5361 #ifdef CONFIG_PINCTRL_PFC_R8A774C0
5362 const struct sh_pfc_soc_info r8a774c0_pinmux_info = {
5363 .name = "r8a774c0_pfc",
5364 .ops = &r8a77990_pinmux_ops,
5365 .unlock_reg = 0xe6060000, /* PMMR */
5366
5367 .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
5368
5369 .pins = pinmux_pins,
5370 .nr_pins = ARRAY_SIZE(pinmux_pins),
5371 .groups = pinmux_groups.common,
5372 .nr_groups = ARRAY_SIZE(pinmux_groups.common),
5373 .functions = pinmux_functions.common,
5374 .nr_functions = ARRAY_SIZE(pinmux_functions.common),
5375
5376 .cfg_regs = pinmux_config_regs,
5377 .bias_regs = pinmux_bias_regs,
5378 .ioctrl_regs = pinmux_ioctrl_regs,
5379
5380 .pinmux_data = pinmux_data,
5381 .pinmux_data_size = ARRAY_SIZE(pinmux_data),
5382 };
5383 #endif
5384
5385 #ifdef CONFIG_PINCTRL_PFC_R8A77990
5386 const struct sh_pfc_soc_info r8a77990_pinmux_info = {
5387 .name = "r8a77990_pfc",
5388 .ops = &r8a77990_pinmux_ops,
5389 .unlock_reg = 0xe6060000, /* PMMR */
5390
5391 .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
5392
5393 .pins = pinmux_pins,
5394 .nr_pins = ARRAY_SIZE(pinmux_pins),
5395 .groups = pinmux_groups.common,
5396 .nr_groups = ARRAY_SIZE(pinmux_groups.common) +
5397 ARRAY_SIZE(pinmux_groups.automotive),
5398 .functions = pinmux_functions.common,
5399 .nr_functions = ARRAY_SIZE(pinmux_functions.common) +
5400 ARRAY_SIZE(pinmux_functions.automotive),
5401
5402 .cfg_regs = pinmux_config_regs,
5403 .bias_regs = pinmux_bias_regs,
5404 .ioctrl_regs = pinmux_ioctrl_regs,
5405
5406 .pinmux_data = pinmux_data,
5407 .pinmux_data_size = ARRAY_SIZE(pinmux_data),
5408 };
5409 #endif
5410