1 /* SPDX-License-Identifier: GPL-2.0 */
2 /*
3  * Copyright 2008-2016 Freescale Semiconductor, Inc.
4  * Copyright 2017-2018 NXP Semiconductor
5  */
6 
7 #ifndef FSL_DDR_MEMCTL_H
8 #define FSL_DDR_MEMCTL_H
9 
10 /*
11  * Pick a basic DDR Technology.
12  */
13 #include <ddr_spd.h>
14 #include <fsl_ddrc_version.h>
15 
16 #define SDRAM_TYPE_DDR1		2
17 #define SDRAM_TYPE_DDR2		3
18 #define SDRAM_TYPE_LPDDR1	6
19 #define SDRAM_TYPE_DDR3		7
20 #define SDRAM_TYPE_DDR4		5
21 
22 #define DDR_BL4		4	/* burst length 4 */
23 #define DDR_BC4		DDR_BL4	/* burst chop for ddr3 */
24 #define DDR_OTF		6	/* on-the-fly BC4 and BL8 */
25 #define DDR_BL8		8	/* burst length 8 */
26 
27 #define DDR3_RTT_OFF		0
28 #define DDR3_RTT_60_OHM		1 /* RTT_Nom = RZQ/4 */
29 #define DDR3_RTT_120_OHM	2 /* RTT_Nom = RZQ/2 */
30 #define DDR3_RTT_40_OHM		3 /* RTT_Nom = RZQ/6 */
31 #define DDR3_RTT_20_OHM		4 /* RTT_Nom = RZQ/12 */
32 #define DDR3_RTT_30_OHM		5 /* RTT_Nom = RZQ/8 */
33 
34 #define DDR4_RTT_OFF		0
35 #define DDR4_RTT_60_OHM		1	/* RZQ/4 */
36 #define DDR4_RTT_120_OHM	2	/* RZQ/2 */
37 #define DDR4_RTT_40_OHM		3	/* RZQ/6 */
38 #define DDR4_RTT_240_OHM	4	/* RZQ/1 */
39 #define DDR4_RTT_48_OHM		5	/* RZQ/5 */
40 #define DDR4_RTT_80_OHM		6	/* RZQ/3 */
41 #define DDR4_RTT_34_OHM		7	/* RZQ/7 */
42 
43 #define DDR2_RTT_OFF		0
44 #define DDR2_RTT_75_OHM		1
45 #define DDR2_RTT_150_OHM	2
46 #define DDR2_RTT_50_OHM		3
47 
48 #if defined(CONFIG_SYS_FSL_DDR1)
49 #define FSL_DDR_MIN_TCKE_PULSE_WIDTH_DDR	(1)
50 typedef ddr1_spd_eeprom_t generic_spd_eeprom_t;
51 #ifndef CONFIG_FSL_SDRAM_TYPE
52 #define CONFIG_FSL_SDRAM_TYPE	SDRAM_TYPE_DDR1
53 #endif
54 #elif defined(CONFIG_SYS_FSL_DDR2)
55 #define FSL_DDR_MIN_TCKE_PULSE_WIDTH_DDR	(3)
56 typedef ddr2_spd_eeprom_t generic_spd_eeprom_t;
57 #ifndef CONFIG_FSL_SDRAM_TYPE
58 #define CONFIG_FSL_SDRAM_TYPE	SDRAM_TYPE_DDR2
59 #endif
60 #elif defined(CONFIG_SYS_FSL_DDR3)
61 typedef ddr3_spd_eeprom_t generic_spd_eeprom_t;
62 #ifndef CONFIG_FSL_SDRAM_TYPE
63 #define CONFIG_FSL_SDRAM_TYPE	SDRAM_TYPE_DDR3
64 #endif
65 #elif defined(CONFIG_SYS_FSL_DDR4)
66 #define FSL_DDR_MIN_TCKE_PULSE_WIDTH_DDR	(3)	/* FIXME */
67 typedef struct ddr4_spd_eeprom_s generic_spd_eeprom_t;
68 #ifndef CONFIG_FSL_SDRAM_TYPE
69 #define CONFIG_FSL_SDRAM_TYPE	SDRAM_TYPE_DDR4
70 #endif
71 #endif	/* #if defined(CONFIG_SYS_FSL_DDR1) */
72 
73 #define FSL_DDR_ODT_NEVER		0x0
74 #define FSL_DDR_ODT_CS			0x1
75 #define FSL_DDR_ODT_ALL_OTHER_CS	0x2
76 #define FSL_DDR_ODT_OTHER_DIMM		0x3
77 #define FSL_DDR_ODT_ALL			0x4
78 #define FSL_DDR_ODT_SAME_DIMM		0x5
79 #define FSL_DDR_ODT_CS_AND_OTHER_DIMM	0x6
80 #define FSL_DDR_ODT_OTHER_CS_ONSAMEDIMM	0x7
81 
82 /* define bank(chip select) interleaving mode */
83 #define FSL_DDR_CS0_CS1			0x40
84 #define FSL_DDR_CS2_CS3			0x20
85 #define FSL_DDR_CS0_CS1_AND_CS2_CS3	(FSL_DDR_CS0_CS1 | FSL_DDR_CS2_CS3)
86 #define FSL_DDR_CS0_CS1_CS2_CS3		(FSL_DDR_CS0_CS1_AND_CS2_CS3 | 0x04)
87 
88 /* define memory controller interleaving mode */
89 #define FSL_DDR_CACHE_LINE_INTERLEAVING	0x0
90 #define FSL_DDR_PAGE_INTERLEAVING	0x1
91 #define FSL_DDR_BANK_INTERLEAVING	0x2
92 #define FSL_DDR_SUPERBANK_INTERLEAVING	0x3
93 #define FSL_DDR_256B_INTERLEAVING	0x8
94 #define FSL_DDR_3WAY_1KB_INTERLEAVING	0xA
95 #define FSL_DDR_3WAY_4KB_INTERLEAVING	0xC
96 #define FSL_DDR_3WAY_8KB_INTERLEAVING	0xD
97 /* placeholder for 4-way interleaving */
98 #define FSL_DDR_4WAY_1KB_INTERLEAVING	0x1A
99 #define FSL_DDR_4WAY_4KB_INTERLEAVING	0x1C
100 #define FSL_DDR_4WAY_8KB_INTERLEAVING	0x1D
101 
102 #define SDRAM_CS_CONFIG_EN		0x80000000
103 
104 /* DDR_SDRAM_CFG - DDR SDRAM Control Configuration
105  */
106 #define SDRAM_CFG_MEM_EN		0x80000000
107 #define SDRAM_CFG_SREN			0x40000000
108 #define SDRAM_CFG_ECC_EN		0x20000000
109 #define SDRAM_CFG_RD_EN			0x10000000
110 #define SDRAM_CFG_SDRAM_TYPE_DDR1	0x02000000
111 #define SDRAM_CFG_SDRAM_TYPE_DDR2	0x03000000
112 #define SDRAM_CFG_SDRAM_TYPE_MASK	0x07000000
113 #define SDRAM_CFG_SDRAM_TYPE_SHIFT	24
114 #define SDRAM_CFG_DYN_PWR		0x00200000
115 #define SDRAM_CFG_DBW_MASK		0x00180000
116 #define SDRAM_CFG_DBW_SHIFT		19
117 #define SDRAM_CFG_32_BE			0x00080000
118 #define SDRAM_CFG_16_BE			0x00100000
119 #define SDRAM_CFG_8_BE			0x00040000
120 #define SDRAM_CFG_NCAP			0x00020000
121 #define SDRAM_CFG_2T_EN			0x00008000
122 #define SDRAM_CFG_BI			0x00000001
123 
124 #define SDRAM_CFG2_FRC_SR		0x80000000
125 #define SDRAM_CFG2_D_INIT		0x00000010
126 #define SDRAM_CFG2_AP_EN		0x00000020
127 #define SDRAM_CFG2_ODT_CFG_MASK		0x00600000
128 #define SDRAM_CFG2_ODT_NEVER		0
129 #define SDRAM_CFG2_ODT_ONLY_WRITE	1
130 #define SDRAM_CFG2_ODT_ONLY_READ	2
131 #define SDRAM_CFG2_ODT_ALWAYS		3
132 
133 #define SDRAM_INTERVAL_BSTOPRE	0x3FFF
134 #define TIMING_CFG_2_CPO_MASK	0x0F800000
135 
136 #if defined(CONFIG_SYS_FSL_DDR_VER) && \
137 	(CONFIG_SYS_FSL_DDR_VER > FSL_DDR_VER_4_4)
138 #define RD_TO_PRE_MASK		0xf
139 #define RD_TO_PRE_SHIFT		13
140 #define WR_DATA_DELAY_MASK	0xf
141 #define WR_DATA_DELAY_SHIFT	9
142 #else
143 #define RD_TO_PRE_MASK		0x7
144 #define RD_TO_PRE_SHIFT		13
145 #define WR_DATA_DELAY_MASK	0x7
146 #define WR_DATA_DELAY_SHIFT	10
147 #endif
148 
149 /* DDR_EOR register */
150 #define DDR_EOR_RD_REOD_DIS	0x07000000
151 #define DDR_EOR_WD_REOD_DIS	0x00100000
152 
153 /* DDR_MD_CNTL */
154 #define MD_CNTL_MD_EN		0x80000000
155 #define MD_CNTL_CS_SEL_CS0	0x00000000
156 #define MD_CNTL_CS_SEL_CS1	0x10000000
157 #define MD_CNTL_CS_SEL_CS2	0x20000000
158 #define MD_CNTL_CS_SEL_CS3	0x30000000
159 #define MD_CNTL_CS_SEL_CS0_CS1	0x40000000
160 #define MD_CNTL_CS_SEL_CS2_CS3	0x50000000
161 #define MD_CNTL_MD_SEL_MR	0x00000000
162 #define MD_CNTL_MD_SEL_EMR	0x01000000
163 #define MD_CNTL_MD_SEL_EMR2	0x02000000
164 #define MD_CNTL_MD_SEL_EMR3	0x03000000
165 #define MD_CNTL_SET_REF		0x00800000
166 #define MD_CNTL_SET_PRE		0x00400000
167 #define MD_CNTL_CKE_CNTL_LOW	0x00100000
168 #define MD_CNTL_CKE_CNTL_HIGH	0x00200000
169 #define MD_CNTL_WRCW		0x00080000
170 #define MD_CNTL_MD_VALUE(x)	(x & 0x0000FFFF)
171 #define MD_CNTL_CS_SEL(x)	(((x) & 0x7) << 28)
172 #define MD_CNTL_MD_SEL(x)	(((x) & 0xf) << 24)
173 
174 /* DDR_CDR1 */
175 #define DDR_CDR1_DHC_EN	0x80000000
176 #define DDR_CDR1_V0PT9_EN	0x40000000
177 #define DDR_CDR1_ODT_SHIFT	17
178 #define DDR_CDR1_ODT_MASK	0x6
179 #define DDR_CDR2_ODT_MASK	0x1
180 #define DDR_CDR1_ODT(x) ((x & DDR_CDR1_ODT_MASK) << DDR_CDR1_ODT_SHIFT)
181 #define DDR_CDR2_ODT(x) (x & DDR_CDR2_ODT_MASK)
182 #define DDR_CDR2_VREF_OVRD(x)	(0x00008080 | ((((x) - 37) & 0x3F) << 8))
183 #define DDR_CDR2_VREF_TRAIN_EN	0x00000080
184 #define DDR_CDR2_VREF_RANGE_2	0x00000040
185 
186 /* DDR ERR_DISABLE */
187 #define DDR_ERR_DISABLE_APED	(1 << 8)  /* Address parity error disable */
188 
189 /* Mode Registers */
190 #define DDR_MR5_CA_PARITY_LAT_4_CLK	0x1 /* for DDR4-1600/1866/2133 */
191 #define DDR_MR5_CA_PARITY_LAT_5_CLK	0x2 /* for DDR4-2400 */
192 
193 /* DEBUG_26 register */
194 #define DDR_CAS_TO_PRE_SUB_MASK  0x0000f000 /* CAS to preamble subtract value */
195 #define DDR_CAS_TO_PRE_SUB_SHIFT 12
196 
197 /* DEBUG_29 register */
198 #define DDR_TX_BD_DIS	(1 << 10) /* Transmit Bit Deskew Disable */
199 
200 
201 #if (defined(CONFIG_SYS_FSL_DDR_VER) && \
202 	(CONFIG_SYS_FSL_DDR_VER >= FSL_DDR_VER_4_7))
203 #ifdef CONFIG_SYS_FSL_DDR3L
204 #define DDR_CDR_ODT_OFF		0x0
205 #define DDR_CDR_ODT_120ohm	0x1
206 #define DDR_CDR_ODT_200ohm	0x2
207 #define DDR_CDR_ODT_75ohm	0x3
208 #define DDR_CDR_ODT_60ohm	0x5
209 #define DDR_CDR_ODT_46ohm	0x7
210 #elif defined(CONFIG_SYS_FSL_DDR4)
211 #define DDR_CDR_ODT_OFF		0x0
212 #define DDR_CDR_ODT_100ohm	0x1
213 #define DDR_CDR_ODT_120OHM	0x2
214 #define DDR_CDR_ODT_80ohm	0x3
215 #define DDR_CDR_ODT_60ohm	0x4
216 #define DDR_CDR_ODT_40ohm	0x5
217 #define DDR_CDR_ODT_50ohm	0x6
218 #define DDR_CDR_ODT_30ohm	0x7
219 #else
220 #define DDR_CDR_ODT_OFF		0x0
221 #define DDR_CDR_ODT_120ohm	0x1
222 #define DDR_CDR_ODT_180ohm	0x2
223 #define DDR_CDR_ODT_75ohm	0x3
224 #define DDR_CDR_ODT_110ohm	0x4
225 #define DDR_CDR_ODT_60hm	0x5
226 #define DDR_CDR_ODT_70ohm	0x6
227 #define DDR_CDR_ODT_47ohm	0x7
228 #endif /* DDR3L */
229 #else
230 #define DDR_CDR_ODT_75ohm	0x0
231 #define DDR_CDR_ODT_55ohm	0x1
232 #define DDR_CDR_ODT_60ohm	0x2
233 #define DDR_CDR_ODT_50ohm	0x3
234 #define DDR_CDR_ODT_150ohm	0x4
235 #define DDR_CDR_ODT_43ohm	0x5
236 #define DDR_CDR_ODT_120ohm	0x6
237 #endif
238 
239 #define DDR_INIT_ADDR_EXT_UIA	(1 << 31)
240 
241 /* Record of register values computed */
242 typedef struct fsl_ddr_cfg_regs_s {
243 	struct {
244 		unsigned int bnds;
245 		unsigned int config;
246 		unsigned int config_2;
247 	} cs[CONFIG_CHIP_SELECTS_PER_CTRL];
248 	unsigned int timing_cfg_3;
249 	unsigned int timing_cfg_0;
250 	unsigned int timing_cfg_1;
251 	unsigned int timing_cfg_2;
252 	unsigned int ddr_sdram_cfg;
253 	unsigned int ddr_sdram_cfg_2;
254 	unsigned int ddr_sdram_cfg_3;
255 	unsigned int ddr_sdram_mode;
256 	unsigned int ddr_sdram_mode_2;
257 	unsigned int ddr_sdram_mode_3;
258 	unsigned int ddr_sdram_mode_4;
259 	unsigned int ddr_sdram_mode_5;
260 	unsigned int ddr_sdram_mode_6;
261 	unsigned int ddr_sdram_mode_7;
262 	unsigned int ddr_sdram_mode_8;
263 	unsigned int ddr_sdram_mode_9;
264 	unsigned int ddr_sdram_mode_10;
265 	unsigned int ddr_sdram_mode_11;
266 	unsigned int ddr_sdram_mode_12;
267 	unsigned int ddr_sdram_mode_13;
268 	unsigned int ddr_sdram_mode_14;
269 	unsigned int ddr_sdram_mode_15;
270 	unsigned int ddr_sdram_mode_16;
271 	unsigned int ddr_sdram_md_cntl;
272 	unsigned int ddr_sdram_interval;
273 	unsigned int ddr_data_init;
274 	unsigned int ddr_sdram_clk_cntl;
275 	unsigned int ddr_init_addr;
276 	unsigned int ddr_init_ext_addr;
277 	unsigned int timing_cfg_4;
278 	unsigned int timing_cfg_5;
279 	unsigned int timing_cfg_6;
280 	unsigned int timing_cfg_7;
281 	unsigned int timing_cfg_8;
282 	unsigned int timing_cfg_9;
283 	unsigned int ddr_zq_cntl;
284 	unsigned int ddr_wrlvl_cntl;
285 	unsigned int ddr_wrlvl_cntl_2;
286 	unsigned int ddr_wrlvl_cntl_3;
287 	unsigned int ddr_sr_cntr;
288 	unsigned int ddr_sdram_rcw_1;
289 	unsigned int ddr_sdram_rcw_2;
290 	unsigned int ddr_sdram_rcw_3;
291 	unsigned int ddr_sdram_rcw_4;
292 	unsigned int ddr_sdram_rcw_5;
293 	unsigned int ddr_sdram_rcw_6;
294 	unsigned int dq_map_0;
295 	unsigned int dq_map_1;
296 	unsigned int dq_map_2;
297 	unsigned int dq_map_3;
298 	unsigned int ddr_eor;
299 	unsigned int ddr_cdr1;
300 	unsigned int ddr_cdr2;
301 	unsigned int err_disable;
302 	unsigned int err_int_en;
303 	unsigned int debug[64];
304 } fsl_ddr_cfg_regs_t;
305 
306 typedef struct memctl_options_partial_s {
307 	unsigned int all_dimms_ecc_capable;
308 	unsigned int all_dimms_tckmax_ps;
309 	unsigned int all_dimms_burst_lengths_bitmask;
310 	unsigned int all_dimms_registered;
311 	unsigned int all_dimms_unbuffered;
312 	/*	unsigned int lowest_common_spd_caslat; */
313 	unsigned int all_dimms_minimum_trcd_ps;
314 } memctl_options_partial_t;
315 
316 #define DDR_DATA_BUS_WIDTH_64 0
317 #define DDR_DATA_BUS_WIDTH_32 1
318 #define DDR_DATA_BUS_WIDTH_16 2
319 #define DDR_CSWL_CS0	0x04000001
320 /*
321  * Generalized parameters for memory controller configuration,
322  * might be a little specific to the FSL memory controller
323  */
324 typedef struct memctl_options_s {
325 	/*
326 	 * Memory organization parameters
327 	 *
328 	 * if DIMM is present in the system
329 	 * where DIMMs are with respect to chip select
330 	 * where chip selects are with respect to memory boundaries
331 	 */
332 	unsigned int registered_dimm_en;    /* use registered DIMM support */
333 
334 	/* Options local to a Chip Select */
335 	struct cs_local_opts_s {
336 		unsigned int auto_precharge;
337 		unsigned int odt_rd_cfg;
338 		unsigned int odt_wr_cfg;
339 		unsigned int odt_rtt_norm;
340 		unsigned int odt_rtt_wr;
341 	} cs_local_opts[CONFIG_CHIP_SELECTS_PER_CTRL];
342 
343 	/* Special configurations for chip select */
344 	unsigned int memctl_interleaving;
345 	unsigned int memctl_interleaving_mode;
346 	unsigned int ba_intlv_ctl;
347 	unsigned int addr_hash;
348 
349 	/* Operational mode parameters */
350 	unsigned int ecc_mode;	 /* Use ECC? */
351 	/* Initialize ECC using memory controller? */
352 	unsigned int ecc_init_using_memctl;
353 	unsigned int dqs_config;	/* Use DQS? maybe only with DDR2? */
354 	/* SREN - self-refresh during sleep */
355 	unsigned int self_refresh_in_sleep;
356 	/* SR_IE - Self-refresh interrupt enable */
357 	unsigned int self_refresh_interrupt_en;
358 	unsigned int dynamic_power;	/* DYN_PWR */
359 	/* memory data width to use (16-bit, 32-bit, 64-bit) */
360 	unsigned int data_bus_width;
361 	unsigned int burst_length;	/* BL4, OTF and BL8 */
362 	/* On-The-Fly Burst Chop enable */
363 	unsigned int otf_burst_chop_en;
364 	/* mirrior DIMMs for DDR3 */
365 	unsigned int mirrored_dimm;
366 	unsigned int quad_rank_present;
367 	unsigned int ap_en;	/* address parity enable for RDIMM/DDR4-UDIMM */
368 	unsigned int x4_en;	/* enable x4 devices */
369 	unsigned int package_3ds;
370 
371 	/* Global Timing Parameters */
372 	unsigned int cas_latency_override;
373 	unsigned int cas_latency_override_value;
374 	unsigned int use_derated_caslat;
375 	unsigned int additive_latency_override;
376 	unsigned int additive_latency_override_value;
377 
378 	unsigned int clk_adjust;		/* */
379 	unsigned int cpo_override;		/* override timing_cfg_2[CPO]*/
380 	unsigned int cpo_sample;		/* optimize debug_29[24:31] */
381 	unsigned int write_data_delay;		/* DQS adjust */
382 
383 	unsigned int cswl_override;
384 	unsigned int wrlvl_override;
385 	unsigned int wrlvl_sample;		/* Write leveling */
386 	unsigned int wrlvl_start;
387 	unsigned int wrlvl_ctl_2;
388 	unsigned int wrlvl_ctl_3;
389 
390 	unsigned int half_strength_driver_enable;
391 	unsigned int twot_en;
392 	unsigned int threet_en;
393 	unsigned int bstopre;
394 	unsigned int tfaw_window_four_activates_ps;	/* tFAW --  FOUR_ACT */
395 
396 	/* Rtt impedance */
397 	unsigned int rtt_override;		/* rtt_override enable */
398 	unsigned int rtt_override_value;	/* that is Rtt_Nom for DDR3 */
399 	unsigned int rtt_wr_override_value;	/* this is Rtt_WR for DDR3 */
400 
401 	/* Automatic self refresh */
402 	unsigned int auto_self_refresh_en;
403 	unsigned int sr_it;
404 	/* ZQ calibration */
405 	unsigned int zq_en;
406 	/* Write leveling */
407 	unsigned int wrlvl_en;
408 	/* RCW override for RDIMM */
409 	unsigned int rcw_override;
410 	unsigned int rcw_1;
411 	unsigned int rcw_2;
412 	unsigned int rcw_3;
413 	/* control register 1 */
414 	unsigned int ddr_cdr1;
415 	unsigned int ddr_cdr2;
416 
417 	unsigned int trwt_override;
418 	unsigned int trwt;			/* read-to-write turnaround */
419 } memctl_options_t;
420 
421 phys_size_t fsl_ddr_sdram(void);
422 phys_size_t fsl_ddr_sdram_size(void);
423 phys_size_t fsl_other_ddr_sdram(unsigned long long base,
424 				unsigned int first_ctrl,
425 				unsigned int num_ctrls,
426 				unsigned int dimm_slots_per_ctrl,
427 				int (*board_need_reset)(void),
428 				void (*board_reset)(void),
429 				void (*board_de_reset)(void));
430 extern int fsl_use_spd(void);
431 void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs,
432 			     unsigned int ctrl_num, int step);
433 u32 fsl_ddr_get_intl3r(void);
434 void print_ddr_info(unsigned int start_ctrl);
435 
__board_assert_mem_reset(void)436 static void __board_assert_mem_reset(void)
437 {
438 }
439 
__board_deassert_mem_reset(void)440 static void __board_deassert_mem_reset(void)
441 {
442 }
443 
444 void board_assert_mem_reset(void)
445 	__attribute__((weak, alias("__board_assert_mem_reset")));
446 
447 void board_deassert_mem_reset(void)
448 	__attribute__((weak, alias("__board_deassert_mem_reset")));
449 
__board_need_mem_reset(void)450 static int __board_need_mem_reset(void)
451 {
452 	return 0;
453 }
454 
455 int board_need_mem_reset(void)
456 	__attribute__((weak, alias("__board_need_mem_reset")));
457 
458 #if defined(CONFIG_DEEP_SLEEP)
459 void board_mem_sleep_setup(void);
460 bool is_warm_boot(void);
461 int fsl_dp_resume(void);
462 #endif
463 
464 /*
465  * The 85xx boards have a common prototype for fixed_sdram so put the
466  * declaration here.
467  */
468 #ifdef CONFIG_MPC85xx
469 extern phys_size_t fixed_sdram(void);
470 #endif
471 
472 #if defined(CONFIG_DDR_ECC)
473 extern void ddr_enable_ecc(unsigned int dram_size);
474 #endif
475 
476 
477 typedef struct fixed_ddr_parm{
478 	int min_freq;
479 	int max_freq;
480 	fsl_ddr_cfg_regs_t *ddr_settings;
481 } fixed_ddr_parm_t;
482 
483 /**
484  * fsl_initdram() - Set up the SDRAM
485  *
486  * @return 0 if OK, -ve on error
487  */
488 int fsl_initdram(void);
489 
490 #endif
491