1 /* SPDX-License-Identifier: GPL-2.0+ */
2 /*
3  * Freescale USB Controller
4  *
5  * Copyright 2013 Freescale Semiconductor, Inc.
6  */
7 
8 #ifndef _ASM_FSL_USB_H_
9 #define _ASM_FSL_USB_H_
10 
11 #ifdef CONFIG_SYS_FSL_USB_DUAL_PHY_ENABLE
12 struct ccsr_usb_port_ctrl {
13 	u32	ctrl;
14 	u32	drvvbuscfg;
15 	u32	pwrfltcfg;
16 	u32	sts;
17 	u8	res_14[0xc];
18 	u32	bistcfg;
19 	u32	biststs;
20 	u32	abistcfg;
21 	u32	abiststs;
22 	u8	res_30[0x10];
23 	u32	xcvrprg;
24 	u32	anaprg;
25 	u32	anadrv;
26 	u32	anasts;
27 };
28 
29 struct ccsr_usb_phy {
30 	u32	id;
31 	struct ccsr_usb_port_ctrl port1;
32 	u8	res_50[0xc];
33 	u32	tvr;
34 	u32	pllprg[4];
35 	u8	res_70[0x4];
36 	u32	anaccfg;
37 	u32	dbg;
38 	u8	res_7c[0x4];
39 	struct ccsr_usb_port_ctrl port2;
40 	u8	res_dc[0x334];
41 };
42 
43 #define CONFIG_SYS_FSL_USB_CTRL_PHY_EN (1 << 0)
44 #define CONFIG_SYS_FSL_USB_DRVVBUS_CR_EN (1 << 1)
45 #define CONFIG_SYS_FSL_USB_PWRFLT_CR_EN (1 << 1)
46 #define CONFIG_SYS_FSL_USB_PLLPRG1_PHY_DIV (1 << 0)
47 #define CONFIG_SYS_FSL_USB_PLLPRG2_PHY2_CLK_EN (1 << 0)
48 #define CONFIG_SYS_FSL_USB_PLLPRG2_PHY1_CLK_EN (1 << 1)
49 #define CONFIG_SYS_FSL_USB_PLLPRG2_FRAC_LPF_EN (1 << 13)
50 #ifdef CONFIG_SYS_FSL_SINGLE_SOURCE_CLK
51 #define CONFIG_SYS_FSL_USB_PLLPRG2_REF_DIV_INTERNAL_CLK (5 << 4)
52 #define CONFIG_SYS_FSL_USB_PLLPRG2_MFI_INTERNAL_CLK (6 << 16)
53 #define CONFIG_SYS_FSL_USB_INTERNAL_SOC_CLK_EN (1 << 20)
54 #endif
55 #define CONFIG_SYS_FSL_USB_PLLPRG2_REF_DIV (1 << 4)
56 #define CONFIG_SYS_FSL_USB_PLLPRG2_MFI (5 << 16)
57 #define CONFIG_SYS_FSL_USB_PLLPRG2_PLL_EN (1 << 21)
58 #define CONFIG_SYS_FSL_USB_SYS_CLK_VALID (1 << 0)
59 #define CONFIG_SYS_FSL_USB_XCVRPRG_HS_DCNT_PROG_EN (1 << 7)
60 #define CONFIG_SYS_FSL_USB_XCVRPRG_HS_DCNT_PROG_MASK (3 << 4)
61 
62 #define INC_DCNT_THRESHOLD_25MV        (0 << 4)
63 #define INC_DCNT_THRESHOLD_50MV        (1 << 4)
64 #define DEC_DCNT_THRESHOLD_25MV        (2 << 4)
65 #define DEC_DCNT_THRESHOLD_50MV        (3 << 4)
66 #else
67 struct ccsr_usb_phy {
68 	u32     config1;
69 	u32     config2;
70 	u32     config3;
71 	u32     config4;
72 	u32     config5;
73 	u32     status1;
74 	u32	usb_enable_override;
75 	u8	res[0xe4];
76 };
77 #define CONFIG_SYS_FSL_USB_HS_DISCNCT_INC (3 << 22)
78 #define CONFIG_SYS_FSL_USB_RX_AUTO_CAL_RD_WR_SEL (1 << 20)
79 #define CONFIG_SYS_FSL_USB_SQUELCH_PROG_WR_0 13
80 #define CONFIG_SYS_FSL_USB_SQUELCH_PROG_WR_3 16
81 #define CONFIG_SYS_FSL_USB_SQUELCH_PROG_RD_0 0
82 #define CONFIG_SYS_FSL_USB_SQUELCH_PROG_RD_3 3
83 #define CONFIG_SYS_FSL_USB_ENABLE_OVERRIDE 1
84 #define CONFIG_SYS_FSL_USB_SQUELCH_PROG_MASK 0x07
85 #endif
86 
87 /* USB Erratum Checking code */
88 #if defined(CONFIG_PPC) || defined(CONFIG_ARM)
89 bool has_dual_phy(void);
90 bool has_erratum_a005275(void);
91 bool has_erratum_a006261(void);
92 bool has_erratum_a007075(void);
93 bool has_erratum_a007798(void);
94 bool has_erratum_a007792(void);
95 bool has_erratum_a005697(void);
96 bool has_erratum_a004477(void);
97 bool has_erratum_a008751(void);
98 bool has_erratum_a010151(void);
99 #endif
100 #endif /*_ASM_FSL_USB_H_ */
101