1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * sun50i H616 platform dram controller driver
4 *
5 * While controller is very similar to that in H6, PHY is completely
6 * unknown. That's why this driver has plenty of magic numbers. Some
7 * meaning was nevertheless deduced from strings found in boot0 and
8 * known meaning of some dram parameters.
9 * This driver only supports DDR3 memory and omits logic for all
10 * other supported types supported by hardware.
11 *
12 * (C) Copyright 2020 Jernej Skrabec <jernej.skrabec@siol.net>
13 *
14 */
15 #include <common.h>
16 #include <init.h>
17 #include <log.h>
18 #include <asm/io.h>
19 #include <asm/arch/clock.h>
20 #include <asm/arch/dram.h>
21 #include <asm/arch/cpu.h>
22 #include <linux/bitops.h>
23 #include <linux/delay.h>
24 #include <linux/kconfig.h>
25
26 enum {
27 MBUS_QOS_LOWEST = 0,
28 MBUS_QOS_LOW,
29 MBUS_QOS_HIGH,
30 MBUS_QOS_HIGHEST
31 };
32
mbus_configure_port(u8 port,bool bwlimit,bool priority,u8 qos,u8 waittime,u8 acs,u16 bwl0,u16 bwl1,u16 bwl2)33 inline void mbus_configure_port(u8 port,
34 bool bwlimit,
35 bool priority,
36 u8 qos,
37 u8 waittime,
38 u8 acs,
39 u16 bwl0,
40 u16 bwl1,
41 u16 bwl2)
42 {
43 struct sunxi_mctl_com_reg * const mctl_com =
44 (struct sunxi_mctl_com_reg *)SUNXI_DRAM_COM_BASE;
45
46 const u32 cfg0 = ( (bwlimit ? (1 << 0) : 0)
47 | (priority ? (1 << 1) : 0)
48 | ((qos & 0x3) << 2)
49 | ((waittime & 0xf) << 4)
50 | ((acs & 0xff) << 8)
51 | (bwl0 << 16) );
52 const u32 cfg1 = ((u32)bwl2 << 16) | (bwl1 & 0xffff);
53
54 debug("MBUS port %d cfg0 %08x cfg1 %08x\n", port, cfg0, cfg1);
55 writel_relaxed(cfg0, &mctl_com->master[port].cfg0);
56 writel_relaxed(cfg1, &mctl_com->master[port].cfg1);
57 }
58
59 #define MBUS_CONF(port, bwlimit, qos, acs, bwl0, bwl1, bwl2) \
60 mbus_configure_port(port, bwlimit, false, \
61 MBUS_QOS_ ## qos, 0, acs, bwl0, bwl1, bwl2)
62
mctl_set_master_priority(void)63 static void mctl_set_master_priority(void)
64 {
65 struct sunxi_mctl_com_reg * const mctl_com =
66 (struct sunxi_mctl_com_reg *)SUNXI_DRAM_COM_BASE;
67
68 /* enable bandwidth limit windows and set windows size 1us */
69 writel(399, &mctl_com->tmr);
70 writel(BIT(16), &mctl_com->bwcr);
71
72 MBUS_CONF( 0, true, HIGHEST, 0, 256, 128, 100);
73 MBUS_CONF( 1, true, HIGH, 0, 1536, 1400, 256);
74 MBUS_CONF( 2, true, HIGHEST, 0, 512, 256, 96);
75 MBUS_CONF( 3, true, HIGH, 0, 256, 100, 80);
76 MBUS_CONF( 4, true, HIGH, 2, 8192, 5500, 5000);
77 MBUS_CONF( 5, true, HIGH, 2, 100, 64, 32);
78 MBUS_CONF( 6, true, HIGH, 2, 100, 64, 32);
79 MBUS_CONF( 8, true, HIGH, 0, 256, 128, 64);
80 MBUS_CONF(11, true, HIGH, 0, 256, 128, 100);
81 MBUS_CONF(14, true, HIGH, 0, 1024, 256, 64);
82 MBUS_CONF(16, true, HIGHEST, 6, 8192, 2800, 2400);
83 MBUS_CONF(21, true, HIGHEST, 6, 2048, 768, 512);
84 MBUS_CONF(25, true, HIGHEST, 0, 100, 64, 32);
85 MBUS_CONF(26, true, HIGH, 2, 8192, 5500, 5000);
86 MBUS_CONF(37, true, HIGH, 0, 256, 128, 64);
87 MBUS_CONF(38, true, HIGH, 2, 100, 64, 32);
88 MBUS_CONF(39, true, HIGH, 2, 8192, 5500, 5000);
89 MBUS_CONF(40, true, HIGH, 2, 100, 64, 32);
90
91 dmb();
92 }
93
mctl_sys_init(struct dram_para * para)94 static void mctl_sys_init(struct dram_para *para)
95 {
96 struct sunxi_ccm_reg * const ccm =
97 (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
98 struct sunxi_mctl_com_reg * const mctl_com =
99 (struct sunxi_mctl_com_reg *)SUNXI_DRAM_COM_BASE;
100 struct sunxi_mctl_ctl_reg * const mctl_ctl =
101 (struct sunxi_mctl_ctl_reg *)SUNXI_DRAM_CTL0_BASE;
102
103 /* Put all DRAM-related blocks to reset state */
104 clrbits_le32(&ccm->mbus_cfg, MBUS_ENABLE);
105 clrbits_le32(&ccm->mbus_cfg, MBUS_RESET);
106 clrbits_le32(&ccm->dram_gate_reset, BIT(GATE_SHIFT));
107 udelay(5);
108 clrbits_le32(&ccm->dram_gate_reset, BIT(RESET_SHIFT));
109 clrbits_le32(&ccm->pll5_cfg, CCM_PLL5_CTRL_EN);
110 clrbits_le32(&ccm->dram_clk_cfg, DRAM_MOD_RESET);
111
112 udelay(5);
113
114 /* Set PLL5 rate to doubled DRAM clock rate */
115 writel(CCM_PLL5_CTRL_EN | CCM_PLL5_LOCK_EN | CCM_PLL5_OUT_EN |
116 CCM_PLL5_CTRL_N(para->clk * 2 / 24 - 1), &ccm->pll5_cfg);
117 mctl_await_completion(&ccm->pll5_cfg, CCM_PLL5_LOCK, CCM_PLL5_LOCK);
118
119 /* Configure DRAM mod clock */
120 writel(DRAM_CLK_SRC_PLL5, &ccm->dram_clk_cfg);
121 writel(BIT(RESET_SHIFT), &ccm->dram_gate_reset);
122 udelay(5);
123 setbits_le32(&ccm->dram_gate_reset, BIT(GATE_SHIFT));
124
125 /* Disable all channels */
126 writel(0, &mctl_com->maer0);
127 writel(0, &mctl_com->maer1);
128 writel(0, &mctl_com->maer2);
129
130 /* Configure MBUS and enable DRAM mod reset */
131 setbits_le32(&ccm->mbus_cfg, MBUS_RESET);
132 setbits_le32(&ccm->mbus_cfg, MBUS_ENABLE);
133
134 clrbits_le32(&mctl_com->unk_0x500, BIT(25));
135
136 setbits_le32(&ccm->dram_clk_cfg, DRAM_MOD_RESET);
137 udelay(5);
138
139 /* Unknown hack, which enables access of mctl_ctl regs */
140 writel(0x8000, &mctl_ctl->clken);
141 }
142
mctl_set_addrmap(struct dram_para * para)143 static void mctl_set_addrmap(struct dram_para *para)
144 {
145 struct sunxi_mctl_ctl_reg * const mctl_ctl =
146 (struct sunxi_mctl_ctl_reg *)SUNXI_DRAM_CTL0_BASE;
147 u8 cols = para->cols;
148 u8 rows = para->rows;
149 u8 ranks = para->ranks;
150
151 if (!para->bus_full_width)
152 cols -= 1;
153
154 /* Ranks */
155 if (ranks == 2)
156 mctl_ctl->addrmap[0] = rows + cols - 3;
157 else
158 mctl_ctl->addrmap[0] = 0x1F;
159
160 /* Banks, hardcoded to 8 banks now */
161 mctl_ctl->addrmap[1] = (cols - 2) | (cols - 2) << 8 | (cols - 2) << 16;
162
163 /* Columns */
164 mctl_ctl->addrmap[2] = 0;
165 switch (cols) {
166 case 7:
167 mctl_ctl->addrmap[3] = 0x1F1F1F00;
168 mctl_ctl->addrmap[4] = 0x1F1F;
169 break;
170 case 8:
171 mctl_ctl->addrmap[3] = 0x1F1F0000;
172 mctl_ctl->addrmap[4] = 0x1F1F;
173 break;
174 case 9:
175 mctl_ctl->addrmap[3] = 0x1F000000;
176 mctl_ctl->addrmap[4] = 0x1F1F;
177 break;
178 case 10:
179 mctl_ctl->addrmap[3] = 0;
180 mctl_ctl->addrmap[4] = 0x1F1F;
181 break;
182 case 11:
183 mctl_ctl->addrmap[3] = 0;
184 mctl_ctl->addrmap[4] = 0x1F00;
185 break;
186 case 12:
187 mctl_ctl->addrmap[3] = 0;
188 mctl_ctl->addrmap[4] = 0;
189 break;
190 default:
191 panic("Unsupported DRAM configuration: column number invalid\n");
192 }
193
194 /* Rows */
195 mctl_ctl->addrmap[5] = (cols - 3) | ((cols - 3) << 8) | ((cols - 3) << 16) | ((cols - 3) << 24);
196 switch (rows) {
197 case 13:
198 mctl_ctl->addrmap[6] = (cols - 3) | 0x0F0F0F00;
199 mctl_ctl->addrmap[7] = 0x0F0F;
200 break;
201 case 14:
202 mctl_ctl->addrmap[6] = (cols - 3) | ((cols - 3) << 8) | 0x0F0F0000;
203 mctl_ctl->addrmap[7] = 0x0F0F;
204 break;
205 case 15:
206 mctl_ctl->addrmap[6] = (cols - 3) | ((cols - 3) << 8) | ((cols - 3) << 16) | 0x0F000000;
207 mctl_ctl->addrmap[7] = 0x0F0F;
208 break;
209 case 16:
210 mctl_ctl->addrmap[6] = (cols - 3) | ((cols - 3) << 8) | ((cols - 3) << 16) | ((cols - 3) << 24);
211 mctl_ctl->addrmap[7] = 0x0F0F;
212 break;
213 case 17:
214 mctl_ctl->addrmap[6] = (cols - 3) | ((cols - 3) << 8) | ((cols - 3) << 16) | ((cols - 3) << 24);
215 mctl_ctl->addrmap[7] = (cols - 3) | 0x0F00;
216 break;
217 case 18:
218 mctl_ctl->addrmap[6] = (cols - 3) | ((cols - 3) << 8) | ((cols - 3) << 16) | ((cols - 3) << 24);
219 mctl_ctl->addrmap[7] = (cols - 3) | ((cols - 3) << 8);
220 break;
221 default:
222 panic("Unsupported DRAM configuration: row number invalid\n");
223 }
224
225 /* Bank groups, DDR4 only */
226 mctl_ctl->addrmap[8] = 0x3F3F;
227 }
228
229 static const u8 phy_init[] = {
230 0x07, 0x0b, 0x02, 0x16, 0x0d, 0x0e, 0x14, 0x19,
231 0x0a, 0x15, 0x03, 0x13, 0x04, 0x0c, 0x10, 0x06,
232 0x0f, 0x11, 0x1a, 0x01, 0x12, 0x17, 0x00, 0x08,
233 0x09, 0x05, 0x18
234 };
235
mctl_phy_configure_odt(void)236 static void mctl_phy_configure_odt(void)
237 {
238 writel_relaxed(0xe, SUNXI_DRAM_PHY0_BASE + 0x388);
239 writel_relaxed(0xe, SUNXI_DRAM_PHY0_BASE + 0x38c);
240
241 writel_relaxed(0xe, SUNXI_DRAM_PHY0_BASE + 0x3c8);
242 writel_relaxed(0xe, SUNXI_DRAM_PHY0_BASE + 0x3cc);
243
244 writel_relaxed(0xe, SUNXI_DRAM_PHY0_BASE + 0x408);
245 writel_relaxed(0xe, SUNXI_DRAM_PHY0_BASE + 0x40c);
246
247 writel_relaxed(0xe, SUNXI_DRAM_PHY0_BASE + 0x448);
248 writel_relaxed(0xe, SUNXI_DRAM_PHY0_BASE + 0x44c);
249
250 writel_relaxed(0xe, SUNXI_DRAM_PHY0_BASE + 0x340);
251 writel_relaxed(0xe, SUNXI_DRAM_PHY0_BASE + 0x344);
252
253 writel_relaxed(0xe, SUNXI_DRAM_PHY0_BASE + 0x348);
254 writel_relaxed(0xe, SUNXI_DRAM_PHY0_BASE + 0x34c);
255
256 writel_relaxed(0x8, SUNXI_DRAM_PHY0_BASE + 0x380);
257 writel_relaxed(0x8, SUNXI_DRAM_PHY0_BASE + 0x384);
258
259 writel_relaxed(0x8, SUNXI_DRAM_PHY0_BASE + 0x3c0);
260 writel_relaxed(0x8, SUNXI_DRAM_PHY0_BASE + 0x3c4);
261
262 writel_relaxed(0x8, SUNXI_DRAM_PHY0_BASE + 0x400);
263 writel_relaxed(0x8, SUNXI_DRAM_PHY0_BASE + 0x404);
264
265 writel_relaxed(0x8, SUNXI_DRAM_PHY0_BASE + 0x440);
266 writel_relaxed(0x8, SUNXI_DRAM_PHY0_BASE + 0x444);
267
268 dmb();
269 }
270
mctl_phy_write_leveling(struct dram_para * para)271 static bool mctl_phy_write_leveling(struct dram_para *para)
272 {
273 bool result = true;
274 u32 val;
275
276 clrsetbits_le32(SUNXI_DRAM_PHY0_BASE + 8, 0xc0, 0x80);
277 writel(4, SUNXI_DRAM_PHY0_BASE + 0xc);
278 writel(0x40, SUNXI_DRAM_PHY0_BASE + 0x10);
279
280 setbits_le32(SUNXI_DRAM_PHY0_BASE + 8, 4);
281
282 if (para->bus_full_width)
283 val = 0xf;
284 else
285 val = 3;
286
287 mctl_await_completion((u32*)(SUNXI_DRAM_PHY0_BASE + 0x188), val, val);
288
289 clrbits_le32(SUNXI_DRAM_PHY0_BASE + 8, 4);
290
291 val = readl(SUNXI_DRAM_PHY0_BASE + 0x258);
292 if (val == 0 || val == 0x3f)
293 result = false;
294 val = readl(SUNXI_DRAM_PHY0_BASE + 0x25c);
295 if (val == 0 || val == 0x3f)
296 result = false;
297 val = readl(SUNXI_DRAM_PHY0_BASE + 0x318);
298 if (val == 0 || val == 0x3f)
299 result = false;
300 val = readl(SUNXI_DRAM_PHY0_BASE + 0x31c);
301 if (val == 0 || val == 0x3f)
302 result = false;
303
304 clrbits_le32(SUNXI_DRAM_PHY0_BASE + 8, 0xc0);
305
306 if (para->ranks == 2) {
307 clrsetbits_le32(SUNXI_DRAM_PHY0_BASE + 8, 0xc0, 0x40);
308
309 setbits_le32(SUNXI_DRAM_PHY0_BASE + 8, 4);
310
311 if (para->bus_full_width)
312 val = 0xf;
313 else
314 val = 3;
315
316 mctl_await_completion((u32*)(SUNXI_DRAM_PHY0_BASE + 0x188), val, val);
317
318 clrbits_le32(SUNXI_DRAM_PHY0_BASE + 8, 4);
319 }
320
321 clrbits_le32(SUNXI_DRAM_PHY0_BASE + 8, 0xc0);
322
323 return result;
324 }
325
mctl_phy_read_calibration(struct dram_para * para)326 static bool mctl_phy_read_calibration(struct dram_para *para)
327 {
328 bool result = true;
329 u32 val, tmp;
330
331 clrsetbits_le32(SUNXI_DRAM_PHY0_BASE + 8, 0x30, 0x20);
332
333 setbits_le32(SUNXI_DRAM_PHY0_BASE + 8, 1);
334
335 if (para->bus_full_width)
336 val = 0xf;
337 else
338 val = 3;
339
340 while ((readl(SUNXI_DRAM_PHY0_BASE + 0x184) & val) != val) {
341 if (readl(SUNXI_DRAM_PHY0_BASE + 0x184) & 0x20) {
342 result = false;
343 break;
344 }
345 }
346
347 clrbits_le32(SUNXI_DRAM_PHY0_BASE + 8, 1);
348
349 clrbits_le32(SUNXI_DRAM_PHY0_BASE + 8, 0x30);
350
351 if (para->ranks == 2) {
352 clrsetbits_le32(SUNXI_DRAM_PHY0_BASE + 8, 0x30, 0x10);
353
354 setbits_le32(SUNXI_DRAM_PHY0_BASE + 8, 1);
355
356 while ((readl(SUNXI_DRAM_PHY0_BASE + 0x184) & val) != val) {
357 if (readl(SUNXI_DRAM_PHY0_BASE + 0x184) & 0x20) {
358 result = false;
359 break;
360 }
361 }
362
363 setbits_le32(SUNXI_DRAM_PHY0_BASE + 8, 1);
364 }
365
366 clrbits_le32(SUNXI_DRAM_PHY0_BASE + 8, 0x30);
367
368 val = readl(SUNXI_DRAM_PHY0_BASE + 0x274) & 7;
369 tmp = readl(SUNXI_DRAM_PHY0_BASE + 0x26c) & 7;
370 if (val < tmp)
371 val = tmp;
372 tmp = readl(SUNXI_DRAM_PHY0_BASE + 0x32c) & 7;
373 if (val < tmp)
374 val = tmp;
375 tmp = readl(SUNXI_DRAM_PHY0_BASE + 0x334) & 7;
376 if (val < tmp)
377 val = tmp;
378 clrsetbits_le32(SUNXI_DRAM_PHY0_BASE + 0x38, 0x7, (val + 2) & 7);
379
380 setbits_le32(SUNXI_DRAM_PHY0_BASE + 4, 0x20);
381
382 return result;
383 }
384
mctl_phy_read_training(struct dram_para * para)385 static bool mctl_phy_read_training(struct dram_para *para)
386 {
387 u32 val1, val2, *ptr1, *ptr2;
388 bool result = true;
389 int i;
390
391 clrsetbits_le32(SUNXI_DRAM_PHY0_BASE + 0x198, 3, 2);
392 clrsetbits_le32(SUNXI_DRAM_PHY0_BASE + 0x804, 0x3f, 0xf);
393 clrsetbits_le32(SUNXI_DRAM_PHY0_BASE + 0x808, 0x3f, 0xf);
394 clrsetbits_le32(SUNXI_DRAM_PHY0_BASE + 0xa04, 0x3f, 0xf);
395 clrsetbits_le32(SUNXI_DRAM_PHY0_BASE + 0xa08, 0x3f, 0xf);
396
397 setbits_le32(SUNXI_DRAM_PHY0_BASE + 0x190, 6);
398 setbits_le32(SUNXI_DRAM_PHY0_BASE + 0x190, 1);
399
400 mctl_await_completion((u32*)(SUNXI_DRAM_PHY0_BASE + 0x840), 0xc, 0xc);
401 if (readl(SUNXI_DRAM_PHY0_BASE + 0x840) & 3)
402 result = false;
403
404 if (para->bus_full_width) {
405 mctl_await_completion((u32*)(SUNXI_DRAM_PHY0_BASE + 0xa40), 0xc, 0xc);
406 if (readl(SUNXI_DRAM_PHY0_BASE + 0xa40) & 3)
407 result = false;
408 }
409
410 ptr1 = (u32*)(SUNXI_DRAM_PHY0_BASE + 0x898);
411 ptr2 = (u32*)(SUNXI_DRAM_PHY0_BASE + 0x850);
412 for (i = 0; i < 9; i++) {
413 val1 = readl(&ptr1[i]);
414 val2 = readl(&ptr2[i]);
415 if (val1 - val2 <= 6)
416 result = false;
417 }
418 ptr1 = (u32*)(SUNXI_DRAM_PHY0_BASE + 0x8bc);
419 ptr2 = (u32*)(SUNXI_DRAM_PHY0_BASE + 0x874);
420 for (i = 0; i < 9; i++) {
421 val1 = readl(&ptr1[i]);
422 val2 = readl(&ptr2[i]);
423 if (val1 - val2 <= 6)
424 result = false;
425 }
426
427 if (para->bus_full_width) {
428 ptr1 = (u32*)(SUNXI_DRAM_PHY0_BASE + 0xa98);
429 ptr2 = (u32*)(SUNXI_DRAM_PHY0_BASE + 0xa50);
430 for (i = 0; i < 9; i++) {
431 val1 = readl(&ptr1[i]);
432 val2 = readl(&ptr2[i]);
433 if (val1 - val2 <= 6)
434 result = false;
435 }
436
437 ptr1 = (u32*)(SUNXI_DRAM_PHY0_BASE + 0xabc);
438 ptr2 = (u32*)(SUNXI_DRAM_PHY0_BASE + 0xa74);
439 for (i = 0; i < 9; i++) {
440 val1 = readl(&ptr1[i]);
441 val2 = readl(&ptr2[i]);
442 if (val1 - val2 <= 6)
443 result = false;
444 }
445 }
446
447 clrbits_le32(SUNXI_DRAM_PHY0_BASE + 0x190, 3);
448
449 if (para->ranks == 2) {
450 /* maybe last parameter should be 1? */
451 clrsetbits_le32(SUNXI_DRAM_PHY0_BASE + 0x198, 3, 2);
452
453 setbits_le32(SUNXI_DRAM_PHY0_BASE + 0x190, 6);
454 setbits_le32(SUNXI_DRAM_PHY0_BASE + 0x190, 1);
455
456 mctl_await_completion((u32*)(SUNXI_DRAM_PHY0_BASE + 0x840), 0xc, 0xc);
457 if (readl(SUNXI_DRAM_PHY0_BASE + 0x840) & 3)
458 result = false;
459
460 if (para->bus_full_width) {
461 mctl_await_completion((u32*)(SUNXI_DRAM_PHY0_BASE + 0xa40), 0xc, 0xc);
462 if (readl(SUNXI_DRAM_PHY0_BASE + 0xa40) & 3)
463 result = false;
464 }
465
466 clrbits_le32(SUNXI_DRAM_PHY0_BASE + 0x190, 3);
467 }
468
469 clrbits_le32(SUNXI_DRAM_PHY0_BASE + 0x198, 3);
470
471 return result;
472 }
473
mctl_phy_write_training(struct dram_para * para)474 static bool mctl_phy_write_training(struct dram_para *para)
475 {
476 u32 val1, val2, *ptr1, *ptr2;
477 bool result = true;
478 int i;
479
480 writel(0, SUNXI_DRAM_PHY0_BASE + 0x134);
481 writel(0, SUNXI_DRAM_PHY0_BASE + 0x138);
482 writel(0, SUNXI_DRAM_PHY0_BASE + 0x19c);
483 writel(0, SUNXI_DRAM_PHY0_BASE + 0x1a0);
484
485 clrsetbits_le32(SUNXI_DRAM_PHY0_BASE + 0x198, 0xc, 8);
486
487 setbits_le32(SUNXI_DRAM_PHY0_BASE + 0x190, 0x10);
488 setbits_le32(SUNXI_DRAM_PHY0_BASE + 0x190, 0x20);
489
490 mctl_await_completion((u32*)(SUNXI_DRAM_PHY0_BASE + 0x8e0), 3, 3);
491 if (readl(SUNXI_DRAM_PHY0_BASE + 0x8e0) & 0xc)
492 result = false;
493
494 if (para->bus_full_width) {
495 mctl_await_completion((u32*)(SUNXI_DRAM_PHY0_BASE + 0xae0), 3, 3);
496 if (readl(SUNXI_DRAM_PHY0_BASE + 0xae0) & 0xc)
497 result = false;
498 }
499
500 ptr1 = (u32*)(SUNXI_DRAM_PHY0_BASE + 0x938);
501 ptr2 = (u32*)(SUNXI_DRAM_PHY0_BASE + 0x8f0);
502 for (i = 0; i < 9; i++) {
503 val1 = readl(&ptr1[i]);
504 val2 = readl(&ptr2[i]);
505 if (val1 - val2 <= 6)
506 result = false;
507 }
508 ptr1 = (u32*)(SUNXI_DRAM_PHY0_BASE + 0x95c);
509 ptr2 = (u32*)(SUNXI_DRAM_PHY0_BASE + 0x914);
510 for (i = 0; i < 9; i++) {
511 val1 = readl(&ptr1[i]);
512 val2 = readl(&ptr2[i]);
513 if (val1 - val2 <= 6)
514 result = false;
515 }
516
517 if (para->bus_full_width) {
518 ptr1 = (u32*)(SUNXI_DRAM_PHY0_BASE + 0xb38);
519 ptr2 = (u32*)(SUNXI_DRAM_PHY0_BASE + 0xaf0);
520 for (i = 0; i < 9; i++) {
521 val1 = readl(&ptr1[i]);
522 val2 = readl(&ptr2[i]);
523 if (val1 - val2 <= 6)
524 result = false;
525 }
526 ptr1 = (u32*)(SUNXI_DRAM_PHY0_BASE + 0xb5c);
527 ptr2 = (u32*)(SUNXI_DRAM_PHY0_BASE + 0xb14);
528 for (i = 0; i < 9; i++) {
529 val1 = readl(&ptr1[i]);
530 val2 = readl(&ptr2[i]);
531 if (val1 - val2 <= 6)
532 result = false;
533 }
534 }
535
536 clrbits_le32(SUNXI_DRAM_PHY0_BASE + 0x190, 0x60);
537
538 if (para->ranks == 2) {
539 clrsetbits_le32(SUNXI_DRAM_PHY0_BASE + 0x198, 0xc, 4);
540
541 setbits_le32(SUNXI_DRAM_PHY0_BASE + 0x190, 0x10);
542 setbits_le32(SUNXI_DRAM_PHY0_BASE + 0x190, 0x20);
543
544 mctl_await_completion((u32*)(SUNXI_DRAM_PHY0_BASE + 0x8e0), 3, 3);
545 if (readl(SUNXI_DRAM_PHY0_BASE + 0x8e0) & 0xc)
546 result = false;
547
548 if (para->bus_full_width) {
549 mctl_await_completion((u32*)(SUNXI_DRAM_PHY0_BASE + 0xae0), 3, 3);
550 if (readl(SUNXI_DRAM_PHY0_BASE + 0xae0) & 0xc)
551 result = false;
552 }
553
554 clrbits_le32(SUNXI_DRAM_PHY0_BASE + 0x190, 0x60);
555 }
556
557 clrbits_le32(SUNXI_DRAM_PHY0_BASE + 0x198, 0xc);
558
559 return result;
560 }
561
mctl_phy_bit_delay_compensation(struct dram_para * para)562 static bool mctl_phy_bit_delay_compensation(struct dram_para *para)
563 {
564 u32 *ptr;
565 int i;
566
567 clrbits_le32(SUNXI_DRAM_PHY0_BASE + 0x60, 1);
568 setbits_le32(SUNXI_DRAM_PHY0_BASE + 8, 8);
569 clrbits_le32(SUNXI_DRAM_PHY0_BASE + 0x190, 0x10);
570
571 ptr = (u32*)(SUNXI_DRAM_PHY0_BASE + 0x484);
572 for (i = 0; i < 9; i++) {
573 writel_relaxed(0x16, ptr);
574 writel_relaxed(0x16, ptr + 0x30);
575 ptr += 2;
576 }
577 writel_relaxed(0x1c, SUNXI_DRAM_PHY0_BASE + 0x4d0);
578 writel_relaxed(0x1c, SUNXI_DRAM_PHY0_BASE + 0x590);
579 writel_relaxed(0x1c, SUNXI_DRAM_PHY0_BASE + 0x4cc);
580 writel_relaxed(0x1c, SUNXI_DRAM_PHY0_BASE + 0x58c);
581
582 ptr = (u32*)(SUNXI_DRAM_PHY0_BASE + 0x4d8);
583 for (i = 0; i < 9; i++) {
584 writel_relaxed(0x1a, ptr);
585 writel_relaxed(0x1a, ptr + 0x30);
586 ptr += 2;
587 }
588 writel_relaxed(0x1e, SUNXI_DRAM_PHY0_BASE + 0x524);
589 writel_relaxed(0x1e, SUNXI_DRAM_PHY0_BASE + 0x5e4);
590 writel_relaxed(0x1e, SUNXI_DRAM_PHY0_BASE + 0x520);
591 writel_relaxed(0x1e, SUNXI_DRAM_PHY0_BASE + 0x5e0);
592
593 ptr = (u32*)(SUNXI_DRAM_PHY0_BASE + 0x604);
594 for (i = 0; i < 9; i++) {
595 writel_relaxed(0x1a, ptr);
596 writel_relaxed(0x1a, ptr + 0x30);
597 ptr += 2;
598 }
599 writel_relaxed(0x1e, SUNXI_DRAM_PHY0_BASE + 0x650);
600 writel_relaxed(0x1e, SUNXI_DRAM_PHY0_BASE + 0x710);
601 writel_relaxed(0x1e, SUNXI_DRAM_PHY0_BASE + 0x64c);
602 writel_relaxed(0x1e, SUNXI_DRAM_PHY0_BASE + 0x70c);
603
604 ptr = (u32*)(SUNXI_DRAM_PHY0_BASE + 0x658);
605 for (i = 0; i < 9; i++) {
606 writel_relaxed(0x1a, ptr);
607 writel_relaxed(0x1a, ptr + 0x30);
608 ptr += 2;
609 }
610 writel_relaxed(0x1e, SUNXI_DRAM_PHY0_BASE + 0x6a4);
611 writel_relaxed(0x1e, SUNXI_DRAM_PHY0_BASE + 0x764);
612 writel_relaxed(0x1e, SUNXI_DRAM_PHY0_BASE + 0x6a0);
613 writel_relaxed(0x1e, SUNXI_DRAM_PHY0_BASE + 0x760);
614
615 dmb();
616
617 setbits_le32(SUNXI_DRAM_PHY0_BASE + 0x60, 1);
618
619 /* second part */
620 clrbits_le32(SUNXI_DRAM_PHY0_BASE + 0x54, 0x80);
621 clrbits_le32(SUNXI_DRAM_PHY0_BASE + 0x190, 4);
622
623 ptr = (u32*)(SUNXI_DRAM_PHY0_BASE + 0x480);
624 for (i = 0; i < 9; i++) {
625 writel_relaxed(0x10, ptr);
626 writel_relaxed(0x10, ptr + 0x30);
627 ptr += 2;
628 }
629 writel_relaxed(0x18, SUNXI_DRAM_PHY0_BASE + 0x528);
630 writel_relaxed(0x18, SUNXI_DRAM_PHY0_BASE + 0x5e8);
631 writel_relaxed(0x18, SUNXI_DRAM_PHY0_BASE + 0x4c8);
632 writel_relaxed(0x18, SUNXI_DRAM_PHY0_BASE + 0x588);
633
634 ptr = (u32*)(SUNXI_DRAM_PHY0_BASE + 0x4d4);
635 for (i = 0; i < 9; i++) {
636 writel_relaxed(0x12, ptr);
637 writel_relaxed(0x12, ptr + 0x30);
638 ptr += 2;
639 }
640 writel_relaxed(0x1a, SUNXI_DRAM_PHY0_BASE + 0x52c);
641 writel_relaxed(0x1a, SUNXI_DRAM_PHY0_BASE + 0x5ec);
642 writel_relaxed(0x1a, SUNXI_DRAM_PHY0_BASE + 0x51c);
643 writel_relaxed(0x1a, SUNXI_DRAM_PHY0_BASE + 0x5dc);
644
645 ptr = (u32*)(SUNXI_DRAM_PHY0_BASE + 0x600);
646 for (i = 0; i < 9; i++) {
647 writel_relaxed(0x12, ptr);
648 writel_relaxed(0x12, ptr + 0x30);
649 ptr += 2;
650 }
651 writel_relaxed(0x1a, SUNXI_DRAM_PHY0_BASE + 0x6a8);
652 writel_relaxed(0x1a, SUNXI_DRAM_PHY0_BASE + 0x768);
653 writel_relaxed(0x1a, SUNXI_DRAM_PHY0_BASE + 0x648);
654 writel_relaxed(0x1a, SUNXI_DRAM_PHY0_BASE + 0x708);
655
656 ptr = (u32*)(SUNXI_DRAM_PHY0_BASE + 0x654);
657 for (i = 0; i < 9; i++) {
658 writel_relaxed(0x14, ptr);
659 writel_relaxed(0x14, ptr + 0x30);
660 ptr += 2;
661 }
662 writel_relaxed(0x1c, SUNXI_DRAM_PHY0_BASE + 0x6ac);
663 writel_relaxed(0x1c, SUNXI_DRAM_PHY0_BASE + 0x76c);
664 writel_relaxed(0x1c, SUNXI_DRAM_PHY0_BASE + 0x69c);
665 writel_relaxed(0x1c, SUNXI_DRAM_PHY0_BASE + 0x75c);
666
667 dmb();
668
669 setbits_le32(SUNXI_DRAM_PHY0_BASE + 0x54, 0x80);
670
671 return true;
672 }
673
mctl_phy_init(struct dram_para * para)674 static bool mctl_phy_init(struct dram_para *para)
675 {
676 struct sunxi_mctl_com_reg * const mctl_com =
677 (struct sunxi_mctl_com_reg *)SUNXI_DRAM_COM_BASE;
678 struct sunxi_mctl_ctl_reg * const mctl_ctl =
679 (struct sunxi_mctl_ctl_reg *)SUNXI_DRAM_CTL0_BASE;
680 u32 val, *ptr;
681 int i;
682
683 if (para->bus_full_width)
684 val = 0xf;
685 else
686 val = 3;
687 clrsetbits_le32(SUNXI_DRAM_PHY0_BASE + 0x3c, 0xf, val);
688
689 writel(0xd, SUNXI_DRAM_PHY0_BASE + 0x14);
690 writel(0xd, SUNXI_DRAM_PHY0_BASE + 0x35c);
691 writel(0xd, SUNXI_DRAM_PHY0_BASE + 0x368);
692 writel(0xd, SUNXI_DRAM_PHY0_BASE + 0x374);
693
694 writel(0, SUNXI_DRAM_PHY0_BASE + 0x18);
695 writel(0, SUNXI_DRAM_PHY0_BASE + 0x360);
696 writel(0, SUNXI_DRAM_PHY0_BASE + 0x36c);
697 writel(0, SUNXI_DRAM_PHY0_BASE + 0x378);
698
699 writel(9, SUNXI_DRAM_PHY0_BASE + 0x1c);
700 writel(9, SUNXI_DRAM_PHY0_BASE + 0x364);
701 writel(9, SUNXI_DRAM_PHY0_BASE + 0x370);
702 writel(9, SUNXI_DRAM_PHY0_BASE + 0x37c);
703
704 ptr = (u32*)(SUNXI_DRAM_PHY0_BASE + 0xc0);
705 for (i = 0; i < ARRAY_SIZE(phy_init); i++)
706 writel(phy_init[i], &ptr[i]);
707
708 if (IS_ENABLED(CONFIG_DRAM_SUN50I_H616_UNKNOWN_FEATURE)) {
709 ptr = (u32*)(SUNXI_DRAM_PHY0_BASE + 0x780);
710 for (i = 0; i < 32; i++)
711 writel(0x16, &ptr[i]);
712 writel(0xe, SUNXI_DRAM_PHY0_BASE + 0x78c);
713 writel(0xe, SUNXI_DRAM_PHY0_BASE + 0x7a4);
714 writel(0xe, SUNXI_DRAM_PHY0_BASE + 0x7b8);
715 writel(0x8, SUNXI_DRAM_PHY0_BASE + 0x7d4);
716 writel(0xe, SUNXI_DRAM_PHY0_BASE + 0x7dc);
717 writel(0xe, SUNXI_DRAM_PHY0_BASE + 0x7e0);
718 }
719
720 writel(0x80, SUNXI_DRAM_PHY0_BASE + 0x3dc);
721 writel(0x80, SUNXI_DRAM_PHY0_BASE + 0x45c);
722
723 if (IS_ENABLED(DRAM_ODT_EN))
724 mctl_phy_configure_odt();
725
726 clrsetbits_le32(SUNXI_DRAM_PHY0_BASE + 4, 7, 0xa);
727
728 if (para->clk <= 672)
729 writel(0xf, SUNXI_DRAM_PHY0_BASE + 0x20);
730 if (para->clk > 500) {
731 clrbits_le32(SUNXI_DRAM_PHY0_BASE + 0x144, BIT(7));
732 clrbits_le32(SUNXI_DRAM_PHY0_BASE + 0x14c, 0xe0);
733 } else {
734 setbits_le32(SUNXI_DRAM_PHY0_BASE + 0x144, BIT(7));
735 clrsetbits_le32(SUNXI_DRAM_PHY0_BASE + 0x14c, 0xe0, 0x20);
736 }
737
738 clrbits_le32(SUNXI_DRAM_PHY0_BASE + 0x14c, 8);
739
740 mctl_await_completion((u32*)(SUNXI_DRAM_PHY0_BASE + 0x180), 4, 4);
741
742 writel(0x37, SUNXI_DRAM_PHY0_BASE + 0x58);
743 clrbits_le32(&mctl_com->unk_0x500, 0x200);
744
745 writel(0, &mctl_ctl->swctl);
746 setbits_le32(&mctl_ctl->dfimisc, 1);
747
748 /* start DFI init */
749 setbits_le32(&mctl_ctl->dfimisc, 0x20);
750 writel(1, &mctl_ctl->swctl);
751 mctl_await_completion(&mctl_ctl->swstat, 1, 1);
752 /* poll DFI init complete */
753 mctl_await_completion(&mctl_ctl->dfistat, 1, 1);
754 writel(0, &mctl_ctl->swctl);
755 clrbits_le32(&mctl_ctl->dfimisc, 0x20);
756
757 clrbits_le32(&mctl_ctl->pwrctl, 0x20);
758 writel(1, &mctl_ctl->swctl);
759 mctl_await_completion(&mctl_ctl->swstat, 1, 1);
760 mctl_await_completion(&mctl_ctl->statr, 3, 1);
761
762 writel(0, &mctl_ctl->swctl);
763 clrbits_le32(&mctl_ctl->dfimisc, 1);
764
765 writel(1, &mctl_ctl->swctl);
766 mctl_await_completion(&mctl_ctl->swstat, 1, 1);
767
768 writel(0x1f14, &mctl_ctl->mrctrl1);
769 writel(0x80000030, &mctl_ctl->mrctrl0);
770 mctl_await_completion(&mctl_ctl->mrctrl0, BIT(31), 0);
771
772 writel(4, &mctl_ctl->mrctrl1);
773 writel(0x80001030, &mctl_ctl->mrctrl0);
774 mctl_await_completion(&mctl_ctl->mrctrl0, BIT(31), 0);
775
776 writel(0x20, &mctl_ctl->mrctrl1);
777 writel(0x80002030, &mctl_ctl->mrctrl0);
778 mctl_await_completion(&mctl_ctl->mrctrl0, BIT(31), 0);
779
780 writel(0, &mctl_ctl->mrctrl1);
781 writel(0x80003030, &mctl_ctl->mrctrl0);
782 mctl_await_completion(&mctl_ctl->mrctrl0, BIT(31), 0);
783
784 writel(0, SUNXI_DRAM_PHY0_BASE + 0x54);
785
786 writel(0, &mctl_ctl->swctl);
787 clrbits_le32(&mctl_ctl->rfshctl3, 1);
788 writel(1, &mctl_ctl->swctl);
789
790 if (IS_ENABLED(CONFIG_DRAM_SUN50I_H616_WRITE_LEVELING)) {
791 for (i = 0; i < 5; i++)
792 if (mctl_phy_write_leveling(para))
793 break;
794 if (i == 5) {
795 debug("write leveling failed!\n");
796 return false;
797 }
798 }
799
800 if (IS_ENABLED(CONFIG_DRAM_SUN50I_H616_READ_CALIBRATION)) {
801 for (i = 0; i < 5; i++)
802 if (mctl_phy_read_calibration(para))
803 break;
804 if (i == 5) {
805 debug("read calibration failed!\n");
806 return false;
807 }
808 }
809
810 if (IS_ENABLED(CONFIG_DRAM_SUN50I_H616_READ_TRAINING)) {
811 for (i = 0; i < 5; i++)
812 if (mctl_phy_read_training(para))
813 break;
814 if (i == 5) {
815 debug("read training failed!\n");
816 return false;
817 }
818 }
819
820 if (IS_ENABLED(CONFIG_DRAM_SUN50I_H616_WRITE_TRAINING)) {
821 for (i = 0; i < 5; i++)
822 if (mctl_phy_write_training(para))
823 break;
824 if (i == 5) {
825 debug("write training failed!\n");
826 return false;
827 }
828 }
829
830 if (IS_ENABLED(CONFIG_DRAM_SUN50I_H616_BIT_DELAY_COMPENSATION))
831 mctl_phy_bit_delay_compensation(para);
832
833 clrbits_le32(SUNXI_DRAM_PHY0_BASE + 0x60, 4);
834
835 return true;
836 }
837
mctl_ctrl_init(struct dram_para * para)838 static bool mctl_ctrl_init(struct dram_para *para)
839 {
840 struct sunxi_mctl_com_reg * const mctl_com =
841 (struct sunxi_mctl_com_reg *)SUNXI_DRAM_COM_BASE;
842 struct sunxi_mctl_ctl_reg * const mctl_ctl =
843 (struct sunxi_mctl_ctl_reg *)SUNXI_DRAM_CTL0_BASE;
844 u32 reg_val;
845
846 clrsetbits_le32(&mctl_com->unk_0x500, BIT(24), 0x200);
847 writel(0x8000, &mctl_ctl->clken);
848
849 setbits_le32(&mctl_com->unk_0x008, 0xff00);
850
851 clrsetbits_le32(&mctl_ctl->sched[0], 0xff00, 0x3000);
852
853 writel(0, &mctl_ctl->hwlpctl);
854
855 setbits_le32(&mctl_com->unk_0x008, 0xff00);
856
857 reg_val = MSTR_BURST_LENGTH(8) | MSTR_ACTIVE_RANKS(para->ranks);
858 reg_val |= MSTR_DEVICETYPE_DDR3 | MSTR_2TMODE;
859 if (para->bus_full_width)
860 reg_val |= MSTR_BUSWIDTH_FULL;
861 else
862 reg_val |= MSTR_BUSWIDTH_HALF;
863 writel(BIT(31) | BIT(30) | reg_val, &mctl_ctl->mstr);
864
865 if (para->ranks == 2)
866 writel(0x0303, &mctl_ctl->odtmap);
867 else
868 writel(0x0201, &mctl_ctl->odtmap);
869
870 writel(0x06000400, &mctl_ctl->odtcfg);
871 writel(0x06000400, &mctl_ctl->unk_0x2240);
872 writel(0x06000400, &mctl_ctl->unk_0x3240);
873 writel(0x06000400, &mctl_ctl->unk_0x4240);
874
875 setbits_le32(&mctl_com->cr, BIT(31));
876
877 mctl_set_addrmap(para);
878
879 mctl_set_timing_params(para);
880
881 writel(0, &mctl_ctl->pwrctl);
882
883 setbits_le32(&mctl_ctl->dfiupd[0], BIT(31) | BIT(30));
884 setbits_le32(&mctl_ctl->zqctl[0], BIT(31) | BIT(30));
885 setbits_le32(&mctl_ctl->unk_0x2180, BIT(31) | BIT(30));
886 setbits_le32(&mctl_ctl->unk_0x3180, BIT(31) | BIT(30));
887 setbits_le32(&mctl_ctl->unk_0x4180, BIT(31) | BIT(30));
888
889 setbits_le32(&mctl_ctl->rfshctl3, BIT(0));
890 clrbits_le32(&mctl_ctl->dfimisc, BIT(0));
891
892 writel(0, &mctl_com->maer0);
893 writel(0, &mctl_com->maer1);
894 writel(0, &mctl_com->maer2);
895
896 writel(0x20, &mctl_ctl->pwrctl);
897 setbits_le32(&mctl_ctl->clken, BIT(8));
898
899 clrsetbits_le32(&mctl_com->unk_0x500, BIT(24), 0x300);
900 /* this write seems to enable PHY MMIO region */
901 setbits_le32(&mctl_com->unk_0x500, BIT(24));
902
903 if (!mctl_phy_init(para))
904 return false;
905
906 writel(0, &mctl_ctl->swctl);
907 clrbits_le32(&mctl_ctl->rfshctl3, BIT(0));
908
909 setbits_le32(&mctl_com->unk_0x014, BIT(31));
910 writel(0xffffffff, &mctl_com->maer0);
911 writel(0x7ff, &mctl_com->maer1);
912 writel(0xffff, &mctl_com->maer2);
913
914 writel(1, &mctl_ctl->swctl);
915 mctl_await_completion(&mctl_ctl->swstat, 1, 1);
916
917 return true;
918 }
919
mctl_core_init(struct dram_para * para)920 static bool mctl_core_init(struct dram_para *para)
921 {
922 mctl_sys_init(para);
923
924 return mctl_ctrl_init(para);
925 }
926
mctl_auto_detect_rank_width(struct dram_para * para)927 static void mctl_auto_detect_rank_width(struct dram_para *para)
928 {
929 /* this is minimum size that it's supported */
930 para->cols = 8;
931 para->rows = 13;
932
933 /*
934 * Strategy here is to test most demanding combination first and least
935 * demanding last, otherwise HW might not be fully utilized. For
936 * example, half bus width and rank = 1 combination would also work
937 * on HW with full bus width and rank = 2, but only 1/4 RAM would be
938 * visible.
939 */
940
941 debug("testing 32-bit width, rank = 2\n");
942 para->bus_full_width = 1;
943 para->ranks = 2;
944 if (mctl_core_init(para))
945 return;
946
947 debug("testing 32-bit width, rank = 1\n");
948 para->bus_full_width = 1;
949 para->ranks = 1;
950 if (mctl_core_init(para))
951 return;
952
953 debug("testing 16-bit width, rank = 2\n");
954 para->bus_full_width = 0;
955 para->ranks = 2;
956 if (mctl_core_init(para))
957 return;
958
959 debug("testing 16-bit width, rank = 1\n");
960 para->bus_full_width = 0;
961 para->ranks = 1;
962 if (mctl_core_init(para))
963 return;
964
965 panic("This DRAM setup is currently not supported.\n");
966 }
967
mctl_auto_detect_dram_size(struct dram_para * para)968 static void mctl_auto_detect_dram_size(struct dram_para *para)
969 {
970 /* detect row address bits */
971 para->cols = 8;
972 para->rows = 18;
973 mctl_core_init(para);
974
975 for (para->rows = 13; para->rows < 18; para->rows++) {
976 /* 8 banks, 8 bit per byte and 16/32 bit width */
977 if (mctl_mem_matches((1 << (para->rows + para->cols +
978 4 + para->bus_full_width))))
979 break;
980 }
981
982 /* detect column address bits */
983 para->cols = 11;
984 mctl_core_init(para);
985
986 for (para->cols = 8; para->cols < 11; para->cols++) {
987 /* 8 bits per byte and 16/32 bit width */
988 if (mctl_mem_matches(1 << (para->cols + 1 +
989 para->bus_full_width)))
990 break;
991 }
992 }
993
mctl_calc_size(struct dram_para * para)994 static unsigned long mctl_calc_size(struct dram_para *para)
995 {
996 u8 width = para->bus_full_width ? 4 : 2;
997
998 /* 8 banks */
999 return (1ULL << (para->cols + para->rows + 3)) * width * para->ranks;
1000 }
1001
sunxi_dram_init(void)1002 unsigned long sunxi_dram_init(void)
1003 {
1004 struct dram_para para = {
1005 .clk = CONFIG_DRAM_CLK,
1006 .type = SUNXI_DRAM_TYPE_DDR3,
1007 };
1008 unsigned long size;
1009
1010 setbits_le32(0x7010310, BIT(8));
1011 clrbits_le32(0x7010318, 0x3f);
1012
1013 mctl_auto_detect_rank_width(¶);
1014 mctl_auto_detect_dram_size(¶);
1015
1016 mctl_core_init(¶);
1017
1018 size = mctl_calc_size(¶);
1019
1020 mctl_set_master_priority();
1021
1022 return size;
1023 };
1024