1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * (C) Copyright 2013 Keymile AG
4 * Valentin Longchamp <valentin.longchamp@keymile.com>
5 *
6 * Copyright 2011,2012 Freescale Semiconductor, Inc.
7 */
8
9 #include <common.h>
10 #include <command.h>
11 #include <env.h>
12 #include <fdt_support.h>
13 #include <image.h>
14 #include <init.h>
15 #include <netdev.h>
16 #include <linux/compiler.h>
17 #include <asm/mmu.h>
18 #include <asm/processor.h>
19 #include <asm/cache.h>
20 #include <asm/immap_85xx.h>
21 #include <asm/fsl_law.h>
22 #include <asm/fsl_serdes.h>
23 #include <asm/fsl_portals.h>
24 #include <asm/fsl_liodn.h>
25 #include <fm_eth.h>
26
27 #include "../common/common.h"
28 #include "../common/qrio.h"
29 #include "kmp204x.h"
30
31 static uchar ivm_content[CONFIG_SYS_IVM_EEPROM_MAX_LEN];
32
checkboard(void)33 int checkboard(void)
34 {
35 printf("Board: Keymile %s\n", CONFIG_SYS_CONFIG_NAME);
36
37 return 0;
38 }
39
40 #define ZL30158_RST 8
41 #define BFTIC4_RST 0
42 #define RSTRQSR1_WDT_RR 0x00200000
43 #define RSTRQSR1_SW_RR 0x00100000
44
board_early_init_f(void)45 int board_early_init_f(void)
46 {
47 ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
48 bool cpuwd_flag = false;
49
50 /* configure mode for uP reset request */
51 qrio_uprstreq(UPREQ_CORE_RST);
52
53 /* board only uses the DDR_MCK0, so disable the DDR_MCK1/2/3 */
54 setbits_be32(&gur->ddrclkdr, 0x001f000f);
55
56 /* set reset reason according CPU register */
57 if ((gur->rstrqsr1 & (RSTRQSR1_WDT_RR | RSTRQSR1_SW_RR)) ==
58 RSTRQSR1_WDT_RR)
59 cpuwd_flag = true;
60
61 qrio_cpuwd_flag(cpuwd_flag);
62 /* clear CPU bits by writing 1 */
63 setbits_be32(&gur->rstrqsr1, RSTRQSR1_WDT_RR | RSTRQSR1_SW_RR);
64
65 /* set the BFTIC's prstcfg to reset at power-up and unit reset only */
66 qrio_prstcfg(BFTIC4_RST, PRSTCFG_POWUP_UNIT_RST);
67 /* and enable WD on it */
68 qrio_wdmask(BFTIC4_RST, true);
69
70 /* set the ZL30138's prstcfg to reset at power-up only */
71 qrio_prstcfg(ZL30158_RST, PRSTCFG_POWUP_RST);
72 /* and take it out of reset as soon as possible (needed for Hooper) */
73 qrio_prst(ZL30158_RST, false, false);
74
75 return 0;
76 }
77
board_early_init_r(void)78 int board_early_init_r(void)
79 {
80 int ret = 0;
81 /* Flush d-cache and invalidate i-cache of any FLASH data */
82 flush_dcache();
83 invalidate_icache();
84
85 set_liodns();
86 setup_qbman_portals();
87
88 ret = trigger_fpga_config();
89 if (ret)
90 printf("error triggering PCIe FPGA config\n");
91
92 /* enable the Unit LED (red) & Boot LED (on) */
93 qrio_set_leds();
94
95 /* enable Application Buffer */
96 qrio_enable_app_buffer();
97
98 return 0;
99 }
100
get_board_sys_clk(unsigned long dummy)101 unsigned long get_board_sys_clk(unsigned long dummy)
102 {
103 return 66666666;
104 }
105
106 #define ETH_FRONT_PHY_RST 15
107 #define QSFP2_RST 11
108 #define QSFP1_RST 10
109 #define ZL30343_RST 9
110
misc_init_f(void)111 int misc_init_f(void)
112 {
113 /* configure QRIO pis for i2c deblocking */
114 i2c_deblock_gpio_cfg();
115
116 /* configure the front phy's prstcfg and take it out of reset */
117 qrio_prstcfg(ETH_FRONT_PHY_RST, PRSTCFG_POWUP_UNIT_CORE_RST);
118 qrio_prst(ETH_FRONT_PHY_RST, false, false);
119
120 /* set the ZL30343 prstcfg to reset at power-up only */
121 qrio_prstcfg(ZL30343_RST, PRSTCFG_POWUP_RST);
122 /* and enable the WD on it */
123 qrio_wdmask(ZL30343_RST, true);
124
125 /* set the QSFPs' prstcfg to reset at power-up and unit rst only */
126 qrio_prstcfg(QSFP1_RST, PRSTCFG_POWUP_UNIT_RST);
127 qrio_prstcfg(QSFP2_RST, PRSTCFG_POWUP_UNIT_RST);
128
129 /* and enable the WD on them */
130 qrio_wdmask(QSFP1_RST, true);
131 qrio_wdmask(QSFP2_RST, true);
132
133 return 0;
134 }
135
136 #define NUM_SRDS_BANKS 2
137
misc_init_r(void)138 int misc_init_r(void)
139 {
140 serdes_corenet_t *regs = (void *)CONFIG_SYS_FSL_CORENET_SERDES_ADDR;
141 u32 expected[NUM_SRDS_BANKS] = {SRDS_PLLCR0_RFCK_SEL_100,
142 SRDS_PLLCR0_RFCK_SEL_125};
143 unsigned int i;
144
145 /* check SERDES reference clocks */
146 for (i = 0; i < NUM_SRDS_BANKS; i++) {
147 u32 actual = in_be32(®s->bank[i].pllcr0);
148 actual &= SRDS_PLLCR0_RFCK_SEL_MASK;
149 if (actual != expected[i]) {
150 printf("Warning: SERDES bank %u expects reference \
151 clock %sMHz, but actual is %sMHz\n", i + 1,
152 serdes_clock_to_string(expected[i]),
153 serdes_clock_to_string(actual));
154 }
155 }
156
157 ivm_read_eeprom(ivm_content, CONFIG_SYS_IVM_EEPROM_MAX_LEN,
158 CONFIG_PIGGY_MAC_ADDRESS_OFFSET);
159 return 0;
160 }
161
162 #if defined(CONFIG_HUSH_INIT_VAR)
hush_init_var(void)163 int hush_init_var(void)
164 {
165 ivm_analyze_eeprom(ivm_content, CONFIG_SYS_IVM_EEPROM_MAX_LEN);
166 return 0;
167 }
168 #endif
169
170 #if defined(CONFIG_LAST_STAGE_INIT)
171
last_stage_init(void)172 int last_stage_init(void)
173 {
174 #if defined(CONFIG_KMCOGE4)
175 /* on KMCOGE4, the BFTIC4 is on the LBAPP2 */
176 struct bfticu_iomap *bftic4 =
177 (struct bfticu_iomap *)CONFIG_SYS_LBAPP2_BASE;
178 u8 dip_switch = in_8((u8 *)&(bftic4->mswitch)) & BFTICU_DIPSWITCH_MASK;
179
180 if (dip_switch != 0) {
181 /* start bootloader */
182 puts("DIP: Enabled\n");
183 env_set("actual_bank", "0");
184 }
185 #endif
186 set_km_env();
187
188 return 0;
189 }
190 #endif
191
192 #ifdef CONFIG_SYS_DPAA_FMAN
fdt_fixup_fman_mac_addresses(void * blob)193 void fdt_fixup_fman_mac_addresses(void *blob)
194 {
195 int node, i, ret;
196 char *tmp, *end;
197 unsigned char mac_addr[6];
198
199 /* get the mac addr from env */
200 tmp = env_get("ethaddr");
201 if (!tmp) {
202 printf("ethaddr env variable not defined\n");
203 return;
204 }
205 for (i = 0; i < 6; i++) {
206 mac_addr[i] = tmp ? simple_strtoul(tmp, &end, 16) : 0;
207 if (tmp)
208 tmp = (*end) ? end+1 : end;
209 }
210
211 /* find the correct fdt ethernet path and correct it */
212 node = fdt_path_offset(blob, "/soc/fman/ethernet@e8000");
213 if (node < 0) {
214 printf("no /soc/fman/ethernet path offset\n");
215 return;
216 }
217 ret = fdt_setprop(blob, node, "local-mac-address", &mac_addr, 6);
218 if (ret) {
219 printf("error setting local-mac-address property\n");
220 return;
221 }
222 }
223 #endif
224
ft_board_setup(void * blob,struct bd_info * bd)225 int ft_board_setup(void *blob, struct bd_info *bd)
226 {
227 phys_addr_t base;
228 phys_size_t size;
229
230 ft_cpu_setup(blob, bd);
231
232 base = env_get_bootm_low();
233 size = env_get_bootm_size();
234
235 fdt_fixup_memory(blob, (u64)base, (u64)size);
236
237 #if defined(CONFIG_HAS_FSL_DR_USB) || defined(CONFIG_HAS_FSL_MPH_USB)
238 fsl_fdt_fixup_dr_usb(blob, bd);
239 #endif
240
241 #ifdef CONFIG_PCI
242 pci_of_setup(blob, bd);
243 #endif
244
245 fdt_fixup_liodn(blob);
246 #ifdef CONFIG_SYS_DPAA_FMAN
247 fdt_fixup_fman_ethernet(blob);
248 fdt_fixup_fman_mac_addresses(blob);
249 #endif
250
251 return 0;
252 }
253
254 #if defined(CONFIG_POST)
255
256 /* DIC26_SELFTEST GPIO used to start factory test sw */
257 #define SELFTEST_PORT QRIO_GPIO_A
258 #define SELFTEST_PIN 31
259
post_hotkeys_pressed(void)260 int post_hotkeys_pressed(void)
261 {
262 qrio_gpio_direction_input(SELFTEST_PORT, SELFTEST_PIN);
263 return qrio_get_gpio(SELFTEST_PORT, SELFTEST_PIN);
264 }
265 #endif
266